Datasheet FQL40N50 Datasheet (Fairchild Semiconductor)

Page 1
FQL40N50
500V N-Channel MOSFET
FQL40N50
May 2001
TM
QFET
General Description
Features
• 40A, 500V, R
• Low gate charge ( typical 155 nC)
• Low Crss ( typical 95 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
= 0.11Ω @VGS = 10 V
DS(on)
suited for high efficiency switch mode power supply, power factor correction, motor drive and welding machine.
D
!
!
"
"
"
"
!
!
"
" "
"
!
!
S
G
SD
Absolute Maximum Ratings T
TO-264
FQL Series
= 25°C unless otherwise noted
C
!
!
G
Symbol Parameter FQL40N50 Units
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt P
D
Drain-Source Voltage 500 V Drain Current
- Continuous (T
- Continuous (T
Drain Current - Pulsed
= 25°C)
C
= 100°C)
C
(Note 1)
40 A 25 A
160 A Gate-Source Voltage ± 30 V Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Power Dissipation (TC = 25°C)
(Note 2) (Note 1) (Note 1) (Note 3)
1780 mJ
40 A 46 mJ
4.5 V/ns
460 W
- Derate above 25°C 3.7 W/°C
T
, T
J
STG
T
L
Operating and Storage Temperature Range -55 to +150 °C Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds
300 °C
Thermal Characteristics
Symbol Parameter Typ Max Units
R
θJC
R
θCS
R
θJA
©2001 Fairchild Semiconductor Corporation Rev. A1. May 2001
Thermal Resistance, Junction-to-Case -- 0.27 °C/W Thermal Resistance, Case-to-Sink 0.1 -- °C/W Thermal Resistance, Junction-to-Ambient -- 30 °C/W
Page 2
FQL40N50
Electrical Characteristics T
= 25°C unless otherwise noted
C
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV ∆BV / ∆T I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage
DSS
Breakdown Voltage Temperature
DSS
Coefficient
J
Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
= 0 V, ID = 250 µA
V
GS
I
= 250 µA, Referenced to 25°C
D
V
= 500 V, VGS = 0 V
DS
V
= 400 V, TC = 125°C
DS
V
= 30 V, VDS = 0 V
GS
= -30 V, VDS = 0 V
V
GS
500 -- -- V
-- 0.48 -- V/°C
-- -- 1 µA
-- -- 10 µA
-- -- 100 nA
-- -- -100 nA
On Characteristics
V R
g
FS
GS(th)
DS(on)
Gate Threshold Voltage Static Drain-Source
On-Resistance Forward Transconductance
V
= VGS, ID = 250 µA
DS
= 10 V, ID = 20 A
V
GS
= 50 V, ID = 20 A
V
DS
(Note 4)
3.0 -- 5.0 V
-- 0.085 0.11 Ω
-- 29 -- S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance Output Capacitance -- 880 1150 pF Reverse Transfer Capacitance -- 95 120 pF
= 25 V, VGS = 0 V,
V
DS
f = 1.0 MHz
-- 5800 7500 pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q Q Q
g gs gd
Turn-On Delay Time Turn-On Rise Time -- 440 890 ns Turn-Off Delay Time -- 350 700 n s Turn-Off Fall Time -- 250 50 0 n s Total Gate Charge Gate-Source Charge -- 37 -- nC Gate-Drain Charge -- 78 -- nC
= 250 V, ID = 40 A,
V
DD
= 25 Ω
R
G
V
= 400 V, ID = 40 A,
DS
V
GS
= 10 V
(Note 4, 5)
(Note 4, 5)
-- 140 290 ns
-- 155 200 nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 2.0mH, IAS = 40A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 40A, di/dt ≤ 200A/µs, VDD ≤ BV
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
Maximum Continuous Drain-Source Diode Forward Current -- -- 40 A Maximum Pulsed Drain-Source Diode Forward Current -- -- 160 A
= 0 V, IS = 40 A
Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 8.0 -- µC
Starting TJ = 25°C
DSS,
V
GS
= 0 V, IS = 40 A,
V
GS
/ dt = 100 A/µs
dI
F
-- -- 1.4 V
-- 520 -- ns
(Note 4)
Rev. A1. May 2001©2001 Fairchild Semiconductor Corporation
Page 3
Typical Characteristics
FQL40N50
V Top : 15 V 10 V
8.0 V
7.0 V
6.5 V
6.0 V Botto m : 5.5 V
-1
GS
※
Notes :
1. 250μs Pulse Test
2. T
0
10
10
2
10
1
10
, Drain Current [A]
D
I
0
10
10
VDS , Drain-Source Voltage [V]
0.4
0.3
],
Ω
[
0.2
DS(on)
R
0.1
Drain-Source On-Resistance
0 30 60 90 120 150 180
VGS = 10V
VGS = 20V
※
ID , Drain Curren t [A]
= 25
C
1
Note : T
2
10
℃
1
10
0
, Dra in Current [A ]
10
D
I
℃
-1
10
246810
150
℃
25
℃
-55
※
Note s :
= 50V
1. V
DS
2. 250μs Pulse Test
VGS , Gate -S o u rc e Vo lta g e [V ]
Figure 2. Transfer CharacteristicsFigure 1. On-Region Char act er i stic s
2
10
1
10
0
10
, Reverse Drain Current [A]
DR
I
℃
= 25
J
10
℃
150
℃
25
-1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
※
Note s :
= 0 V
1. V
GS
2. 250μs Pulse Test
VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12000
10000
Capacitance [pF]
8000
6000
4000
2000
C
= Cgs + Cgd (Cds = shorted)
iss
C
= Cds + C
oss
gd
C
= C
rss
gd
C
iss
C
oss
※
10
1
Note s :
1. V
= 0 V
GS
2. f = 1 MHz
C
rss
0
-1
10
0
10
VDS, Drain-Source Voltage [V]
12
10
8
6
4
, Gate-Source Voltage [V]
2
GS
V
0
0 30 60 90 120 150 180
QG, Tota l Gate Charge [n C]
VDS = 100V
VDS = 250V
VDS = 400V
※
Note : I
= 40 A
D
Figure 5. Capacitance C haracteristics Figure 6. Gate Charge Characteristics
©2001 Fairchild Semiconductor Corporation Rev. A1. May 2001
Page 4
Typical Characteristics (Continued)
FQL40N50
1.2
1.1
1.0
, (N o r malize d )
DSS
BV
0.9
Drain-Source Breakdown V oltage
0.8
-100 -50 0 50 100 150 200
※
1. V
2. I
No tes :
GS
= 250 μA
D
TJ, Junction Tem perature [oC]
Figure 7. Breakdown Voltage Variation
vs. Temperature
※
Notes :
1. T
= 25 oC
C
= 150 oC
2. T
J
3. Single Pulse
1
10
DS(on)
100 µs
1 ms
10 ms
DC
2
10
3
10
2
10
1
10
, Drain Current [A]
D
0
I
10
-1
10
0
10
Operation in T his Area is Limited by R
VDS, Drain-Source Voltage [V]
= 0 V
10 µs
3.0
2.5
2.0
1.5
, (Normalized)
1.0
DS(ON)
R
Drain-Source On-Resistance
0.5
0.0
-100 -50 0 50 100 150 200
※
Notes :
= 10 V
1. V
GS
= 20 A
2. I
D
TJ, Junction Temperature [oC]
Figure 8. On-Resistance Variation
vs. Temperature
40
30
3
10
20
, Drain Current [A]
D
I
10
0
25 50 75 100 125 150
TC, Case Temperature [℃]
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
D=0.5
-1
10
0.2
0.1
※
No te s :
(t) = 0.27 ℃/W M a x .
1. Z
θ
JC
2. D u ty F a c to r, D = t
3. TJM - TC = PDM * Z
1/t2
(t)
θ
JC
0.05
P
10
(t), Therm al Response
JC
θ
Z
-2
0.02
0.01
-5
10
single pulse
-4
10
-3
10
-2
10
DM
t
1
t
2
-1
10
0
10
1
10
t1, Square W ave Pulse Duration [sec]
Figure 11. Transient Thermal Response Cur ve
©2001 Fairchild Semiconductor Corporation Rev. A1. May 2001
Page 5
12V
12V
200nF
200nF
3mA
3mA
50KΩ
50KΩ
V
V
Gate Charge Test Circuit & Waveform
V
V
GS
GS
GS
300nF
300nF
Same Type
Same Type
as DUT
as DUT
DUT
DUT
V
V
DS
DS
GS
10V
10V
Resistive Switching Test Circuit & Waveforms
FQL40N50
Q
Q
g
g
Q
Q
gs
gs
Q
Q
gd
gd
Charge
Charge
10V
10V
10V
10V
R
R
L
DUT
DUT
L
V
V
DD
DD
V
V
DS
DS
V
V
GS
GS
R
R
G
G
V
V
DS
DS
90%
90%
10%
10%
V
V
GS
GS
t
t
d(on)tr
d(on)tr
t
t
on
on
t
t
d(off)
d(off)
t
t
f
f
t
t
off
off
Unclamped Inductive Switching Test Circuit & Waveforms
BV
BV
DSS
L
LL
V
V
DS
DS
BV
BV
DSS
V
V
DSS
I
I
AS
AS
DD
DD
I
IDI
D
D
R
R
G
G
DUT
DUT
t
t
p
p
V
V
DD
DD
1
1
1
1
----
----
----
----
E
E
=LI
E
=LI
=LI
AS
AS
AS
2
2
2
2
AS
AS
AS
ID (t)
ID (t)
t
t
2
2
2
p
p
DSS
--------------------
-------------------­BV
BV
DSS-VDD
DSS-VDD
Time
Time
V
(t)
V
(t)
DS
DS
©2001 Fairchild Semiconductor Corporation Rev. A1. May 2001
Page 6
Peak Diode Recovery dv /d t Test Circuit & Waveforms
+
DUT
DUT
I
I
SD
SD
Driver
Driver
R
R
G
G
V
V
GS
GS
+
V
V
DS
DS
_
_
L
LL
Same Type
Same Type
as DUT
as DUT
• dv/dt controlled by R
• dv/dt controlled by R
•ISDcontroll ed by pulse peri od
•ISDcontroll ed by pulse peri od
G
G
FQL40N50
V
V
DD
DD
V
V
GS
GS
( Driver )
( Driver )
I
I
SD
SD
( DUT )
( DUT )
V
V
DS
DS
( DUT )
( DUT )
Gate Pulse Width
Gate Pulse Width
Gate Pulse Width
--------------------------
--------------------------
--------------------------
D =
D =
D =
Gate Pulse Period
Gate Pulse Period
Gate Pulse Period
IFM, Body Diode Forward Current
IFM, Body Diode Forward Current
I
I
RM
RM
Body Diode Reverse Current
Body Diode Reverse Current
Body Diode Recoverydv/dt
Body Diode Recoverydv/dt
V
V
SD
SD
Body Diode
Body Diode
Forward Voltage Drop
Forward Voltage Drop
di/dt
di/dt
10V
10V
V
V
DD
DD
©2001 Fairchild Semiconductor Corporation Rev. A1. May 2001
Page 7
Package Dimensions
(8.30) (8.30)
(9.00)
20.00
±0.20
TO-264
(1.00)
(4.00)
±0.20
6.00
FQL40N50
(2.00)
(R2.00)
ø3.30
(9.00)
(11.00)
±0.20
(R1.00)
±0.20
1.50
4.90
(7.00)
±0.20
(7.00)
(1.50) (1.50)
±0.20
2.50
3.00
1.00
5.45TYP
±0.30
[5.45
]
5.45TYP
[5.45
±0.20
+0.25 –0.10
±0.30
(0.50)
(2.00)
]
±0.10
2.50
±0.20
20.00
±0.50
20.00
0.60
+0.25 –0.10
(1.50)
2.80
±0.30
±0.20
±0.20
(0.15)
5.00
3.50
(1.50)
©2001 Fairchild Semiconductor Corporation Rev. A1. May 2001
(2.80)
Page 8
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™
2
E
CMOS™ EnSigna™ FACT™ FACT Quiet Series™
®
FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MICROWIRE™ OPTOLOGIC™
OPTOPLANAR™ PACMAN
™
POP™ PowerTrench
®
QFET™ QS™ QT Optoelectronics™ Quiet Series™ SLIENT SWITCHER SMART START™ Stealth™
SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ UltraFET VCX™
®
®
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design
Preliminary First Producti on This datasheet contains preliminary data, and
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Obsolete Not In Production This datasheet contains specifications on a product
©2001 Fairchild Semiconductor Corporation Rev. H2
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Semiconductor reserves the right to make changes at any time without notice in order to improve design.
that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Loading...