Datasheet FQI4N90, FQB4N90 Datasheet (Fairchild Semiconductor)

Page 1
FQB4N90 / FQI4N90
900V N-Channel MOSFET
FQB4N90 / FQI4N90
October 2001
TM
QFET
These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well
Features
• 4.2A, 900V, R
• Low gate charge ( typically 24 nC)
• Low Crss ( typically 9.5 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
= 3.3 @ VGS = 10 V
DS(on)
suited for high efficiency switch mode power supplies.
!
!
D
!
!
"
"
"
"
"
" "
"
!
!
S
D
GS
2
-PAK
D
FQB Series
GSD
Absolute Maximum Ratings T
I2-PAK
FQI Series
= 25°C unless otherwise noted
C
!
!
G
Symbol Parameter FQB4N90 / FQI4N90 Units
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt P
D
Drain-Source Voltage 900 V Drain Current
- Continuous (T
- Continuous (T
Drain Current - Pulsed
= 25°C)
C
= 100°C)
C
(Note 1)
4.2 A
2.65 A
16.8 A Gate-Source Voltage ± 30 V Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Power Dissipation (TA = 25°C) * Power Dissipation (T
= 25°C)
C
(Note 2) (Note 1) (Note 1) (Note 3)
570 mJ
4.2 A 14 mJ
4.0 V
3.13 W 140 W
- Derate above 25°C 1.12 W/°C
, T
T
J
stg
T
L
Operating and Storage Temperature Range -55 to +150 °C Maximum lead temperature for soldering purposes,
1/8” from case for 5 seconds
300 °C
Thermal Characteristics
Symbol Parameter Typ Max Units
R
θJC
R
θJA
R
θJA
* When mounted on the minimum pad size recommended (PCB Mount)
©2001 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Case -- 0.89 °C/W Thermal Resistance, Junction-to-Ambient * -- 40 °C/W Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W
Rev. B, October 2001
Page 2
FQB4N90 / FQI4N90
Electrical Characteristics T
= 25°C unless otherwise noted
C
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV BV / ∆T I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage
DSS
Breakdown Voltage Temperature
DSS
Coefficient
J
Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
= 0 V, ID = 250 µA
V
GS
I
= 250 µA, Referenced to 25°C
D
V
= 900 V, VGS = 0 V
DS
V
= 720 V, TC = 125°C
DS
V
= 30 V, VDS = 0 V
GS
= -30 V, VDS = 0 V
V
GS
900 -- -- V
-- 0.9 -- V/°C
-- -- 10 µA
-- -- 100 µA
-- -- 100 nA
-- -- -100 nA
On Characteristics
V R
g
FS
GS(th)
DS(on)
Gate Threshold Voltage Static Drain-Source
On-Resistance Forward Transconductance
V
= VGS, ID = 250 µA
DS
V
= 10 V, ID = 2.1 A
GS
= 50 V, ID = 2.1 A
V
DS
(Note 4)
3.0 -- 5.0 V
-- 2.7 3.3
-- 3.5 -- S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance Output Capacitance -- 90 120 pF Reverse Transfer Capacitance -- 9.5 12.5 pF
= 25 V, VGS = 0 V,
V
DS
f = 1.0 MHz
-- 860 1100 pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q Q Q
g gs gd
Turn-On Delay Time Turn-On Rise Time -- 70 150 ns Turn-Off Delay Time -- 45 10 0 ns Turn-Off Fall Time -- 40 90 ns Total Gate Charge Gate-Source Charge -- 5.8 -- nC Gate-Drain Charge -- 11.5 -- nC
= 450 V, ID = 4.2 A,
V
DD
= 25
R
G
V
= 720 V, ID = 4.2 A,
DS
V
GS
= 10 V
(Note 4, 5)
(Note 4, 5)
-- 25 60 ns
-- 24 30 nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 61mH, IAS = 4.2A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD 4.2A, di/dt 200A/µs, VDD≤ BV
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2001 Fairchild Semiconductor Corporation
Maximum Continuous Drain-Source Diode Forward Current -- -- 4.2 A Maximum Pulsed Drain-Source Diode Forward Current -- -- 16.8 A
= 0 V, IS = 4.2 A
Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 3.3 -- µC
Starting TJ = 25°C
DSS,
V
GS
= 0 V, IS = 4.2 A,
V
GS
/ dt = 100 A/µs
dI
F
-- -- 1.4 V
-- 440 -- ns
(Note 4)
Rev. B, October 2001
Page 3
Typical Characteristics
FQB4N90 / FQI4N90
V
GS
1
Top : 1 5 .0 V
10
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V Bottom : 5.5 V
0
10
, Dra in Curre n t [A ]
D
I
-1
10
-1
10
0
10
Note s :
1. 250μs Pulse Tes t
2. T
= 25
C
1
10
VDS, Drain-Source Voltage [V]
10
8
6
[],
DS(on)
R
4
Drain-Source On-Resistance
2
0
036912
VGS = 20V
VGS = 10V
Note : T
= 25
J
ID , Drai n Curren t [A ]
1
10
150
0
10
, Dra in C u rre n t [A]
D
I
-1
10
246810
25
-55
Note s :
= 50V
1. V
DS
2. 250μs Pulse Test
VGS , Gate-Source Voltage [V]
Figure 2. Transfer CharacteristicsFigure 1. On-Region Char act er i stic s
1
10
0
10
, Reverse Drain Current [A]
150
DR
I
-1
10
0.2 0.4 0.6 0.8 1.0 1.2 1.4
25
Note s :
1. V
= 0V
GS
2. 250μs Pulse Test
VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variati on vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current and
Temperature
VDS = 180V
VDS = 450V
VDS = 720V
Note : I
1500
1200
900
600
Capacitance [pF]
300
0
-1
10
VDS, Drain-Source Voltage [V]
C
= Cgs + Cgd (Cds = shorted)
iss
C
= Cds + C
oss
gd
C
= C
rss
10
gd
1
Note s :
1. V
= 0 V
GS
2. f = 1 MHz
C
iss
C
oss
C
rss
0
10
12
10
8
6
4
, Gate-Source Voltage [V]
2
GS
V
0
0 5 10 15 20 25 30
QG, Tota l Gate Charge [n C]
Figure 5. Capacitance C haracteristics Figure 6. Gate Charge Characteristics
= 4.2 A
D
Rev. B, October 2001©2001 Fairchild Semiconductor Corporation
Page 4
Typical Characteristics (Continued)
FQB4N90 / FQI4N90
1.2
1.1
1.0
, (N o r ma lize d )
DSS
BV
0.9
Drain-Source Breakdown V oltage
0.8
-100 -50 0 50 100 150 200
1. V
2. I
No tes :
D
GS
= 250
= 0 V
TJ, Junction Tem perature [oC]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Operation in This Area is Limited by R
Notes :
1. T
= 25 oC
C
= 150 oC
2. T
J
3. Single Pulse
1
10
DS(on)
100 µs
1 ms
10 ms
DC
2
10
2
10
1
10
0
10
, Drain Current [A]
D
-1
I
10
-2
10
0
10
VDS, Drain-Source Voltage [V]
3.0
2.5
2.0
μ
A
1.5
, (Normalized)
1.0
DS(ON)
R
Drain-Source On-Resistance
0.5
0.0
-100 -50 0 50 100 150 200
1. V
2. I
Note s :
D
= 10 V
GS
= 2.1 A
TJ, Junction Temperature [oC]
Figure 8. On-Resistance Variation
vs. Temperature
5
4
3
2
, Drain Current [A]
D
I
1
3
10
0
25 50 75 100 125 150
TC, Case Temperature [℃]
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
0
10
D=0.5
0.2
-1
0.1
10
0.05
0.02
(t), Therm al Response
JC
0.01
θ
Z
-2
10
-5
10
single pulse
-4
10
-3
10
-2
10
N o te s :
(t) = 0.8 9 ℃/W M a x.
1. Z
θ
JC
2. D u ty F a c to r , D = t
3. TJM - TC = PDM * Z
P
DM
t
1
t
2
-1
10
10
1/t2
(t)
θ
JC
0
1
10
t1, S q u a re W av e P u lse D u ra tion [s e c]
Figure 11. Transient Thermal Response Cur ve
©2001 Fairchild Semiconductor Corporation Rev. B, October 2001
Page 5
12V
12V
200nF
200nF
3mA
3mA
50KΩ
50KΩ
Gate Charge Test Circuit & Waveform
V
V
GS
GS
Same Type
Same Type
as DUT
as DUT
300nF
300nF
V
V
GS
GS
DUT
DUT
10V
10V
V
V
DS
DS
Resistive Switching Test Circuit & Waveforms
FQB4N90 / FQI4N90
Q
Q
g
g
Q
Q
gs
gs
Q
Q
gd
gd
Charge
Charge
10V
10V
10V
10V
R
R
L
DUT
DUT
L
( 0.5 rated V
( 0.5 rated V
V
V
DD
DD
V
V
DS
DS
R
R
G
G
DS
DS
V
V
DS
DS
90%
90%
)
)
10%
10%
V
V
in
in
t
t
d(on)tr
d(on)tr
t
t
on
on
t
t
d(off)
d(off)
t
t
f
f
t
t
off
off
Unclamped Inductive Switching Test Circuit & Waveforms
BV
L
V
LL
V
DS
DS
V
V
DD
DD
BV
BV
DSS
V
V
DSS
I
I
AS
AS
DD
DD
I
IDI
D
D
R
R
G
G
DUT
DUT
E
E
E
AS
AS
AS
1
1
1
1
----
----
----
----
=LL I
=LL I
=LL I
2
2
2
2
AS
AS
AS
I
I
D
D
BV
DSS
DSS
--------------------
-------------------­BV
BV
DSS
DSS
(t)
(t)
2
2
2
-- V
-- V
DD
DD
V
(t)
V
(t)
DS
DS
t
t
p
p
Time
Time
Rev. B, October 2001©2001 Fairchild Semiconductor Corporation
Page 6
Peak Diode Recovery dv / dt Test Circuit & Waveforms
DUT
DUT
I
ISI
S
S
Driver
Driver
R
R
G
G
V
V
GS
GS
+
+
V
V
DS
DS
_
_
L
LL
Same Type
Same Type
as DUT
as DUT
• dv/dt controlled by R
• dv/dt controlled by R
•IScontrolled by pulse period
•IScontrolled by pulse period
G
G
FQB4N90 / FQI4N90
V
V
DD
DD
V
V
GS
GS
( Driver )
( Driver )
I
I
S
S
( DUT )
( DUT )
V
V
DS
DS
( DUT )
( DUT )
Gate Pulse Width
Gate Pulse Width
Gate Pulse Width
--------------------------
--------------------------
--------------------------
D =
D =
D =
Gate Pulse Period
Gate Pulse Period
Gate Pulse Period
IFM, Body Diode Forward Current
IFM, Body Diode Forward Current
I
I
RM
RM
Body Diode Reverse Current
Body Diode Reverse Current
Body Diode Recoverydv/dt
Body Diode Recoverydv/dt
V
V
f
f
Body Diode
Body Diode
Forward Voltage Drop
Forward Voltage Drop
di/dt
di/dt
10V
10V
V
V
DD
DD
©2001 Fairchild Semiconductor Corporation Rev. B, October 2001
Page 7
Package Dimensions
FQB4N90 / FQI4N90
D2-PAK
9.90
±0.20
(0.40)
1.40 ±0.20
1.27
±0.10
0.80 ±0.10
2.54 TYP 2.54 TYP
1.20 ±0.20
9.20 ±0.20
4.90 ±0.20
15.30 ±0.30
2.00 ±0.10
(0.75)
4.50 ±0.20
10.00 ±0.20 (8.00) (4.40)
+0.10
1.30
–0.05
0.10 ±0.15
2.40 ±0.20
0°~3°
+0.10
0.50
–0.05
2.54 ±0.30
10.00 ±0.20
15.30 ±0.30
(1.75)
(2XR0.45)
(7.20)
9.20 ±0.20
4.90 ±0.20
0.80 ±0.10
Dimensions in Millimeters
Rev. B, October 2001©2001 Fairchild Semiconductor Corporation
Page 8
Package Dimensions
FQB4N90 / FQI4N90
(Continued)
I2-PAK
9.90 ±0.20
(0.40)
(1.46)
(0.94)
1.27 ±0.10 1.47 ±0.10
13.08 ±0.20
(45°)
0.80 ±0.10
2.54 TYP2.54 TYP
1.20 ±0.20
9.20 ±0.20
MAX 3.00
10.08 ±0.20 MAX13.40
0.50
4.50 ±0.20
+0.10 –0.05
+0.10
1.30
–0.05
2.40 ±0.20
10.00 ±0.20
Dimensions in Millimeters
Rev. B, October 2001©2001 Fairchild Semiconductor Corporation
Page 9
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™
2
CMOS™
E EnSigna™ FACT™ FACT Quiet Series™
STAR*POWER is used under license
®
FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™
OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench
®
QFET™ QS™ QT Optoelectronics™ Quiet Series™ SLIENT SWITCHER
SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TruTranslation™ TinyLogic™ UHC™
®
UltraFET
VCX™
®
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design
Preliminary First Production This datasheet contains preliminary data, and
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Obsolete Not In Production This datasheet contains specifications on a product
©2001 Fairchild Semiconductor Corporation
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Semiconductor reserves the right to make changes at any time without notice in order to improve design.
that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4
Loading...