Datasheet FQI44N08, FQB44N08 Datasheet (Fairchild Semiconductor)

Page 1
FQB44N08 / FQI44N08
August 2000
QFET
QFET
QFETQFET
TM
General Description
These N-Channel enhancement mode power field effect
FQB44N08 / FQI44N08
transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for low voltage applications such as automotive, high efficiency switching for DC/DC converters, and DC mo tor control.
D
G
S
D2-PAK
FQB Series
Absolute Maximum Ratings T
Symbol Parameter FQB44N08 / FQI44N08 Units
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt P
D
, T
T
J
STG
T
L
Drain-Source Voltage 80 V Drain Current
Drain Current - Pulsed Gate-Source Voltage ± 25 V Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Power Dissipation (TA = 25°C) * Power Dissipation (T
Operating and Storage Temperature Range -55 to +175 °C Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds
G
D
S
= 25°C unless otherwise noted
C
- Continuous (T
- Continuous (T
= 25°C)
C
- Derate above 25°C 0.85 W/°C
= 25°C)
C
= 100°C)
C
Features
• 44A, 80V, R
• Low gate charge ( typical 38 nC)
• Low Crss ( typical 90 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• 175°C maximum junction temperature rating
I2-PAK
FQI Series
(Note 1)
(Note 2) (Note 1) (Note 1) (Note 3)
= 0.034 @VGS = 10 V
DS(on)
G
44 A
31.1 A 176 A
450 mJ
44 A
12.7 mJ
6.5 V/ns
3.75 W 127 W
300 °C
!
!
!
!
D
!
!
"
"
"
"
"
" "
"
!
!
S
Thermal Characteristics
Symbol Parameter Typ Max Units
R
θJC
R
θJA
R
θJA
* When mounted on the minimum pad size recommended (PCB Mount)
©2000 Fairchild Semiconductor International
Thermal Resistance, Junction-to-Case -- 1.18 °C/W Thermal Resistance, Junction-to-Ambient * -- 40 °C/W Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W
Rev. A, August 2000
Page 2
FQB44N08 / FQI44N08
Electrical Characteristics T
= 25°C unless otherwise noted
C
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
BV
DSS
/ ∆T I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage Breakdown Voltage Temperature
Coefficient
J
Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
= 0 V, ID = 250 µA
V
GS
I
= 250 µA, Referenced to 25°C
D
V
= 80 V, VGS = 0 V
DS
V
= 64 V, TC = 150°C
DS
V
= 25 V, VDS = 0 V
GS
= -25 V, VDS = 0 V
V
GS
80 -- -- V
-- 0.07 -- V/°C
-- -- 1 µA
-- -- 10 µA
-- -- 100 nA
-- -- -100 nA
On Characteristics
V R
g
FS
GS(th)
DS(on)
Gate Threshold Voltage Static Drain-Source
On-Resistance Forward Transconductance
V
= VGS, ID = 250 µA
DS
= 10 V, ID = 22 A
V
GS
= 30 V, ID = 22 A
V
DS
(Note 4)
2.0 -- 4.0 V
-- 0.026 0.034
-- 23 -- S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance Output Capacitance -- 400 520 pF Reverse Transfer Capacitance -- 90 120 pF
= 25 V, VGS = 0 V,
V
DS
f = 1.0 MHz
-- 1100 1430 pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q Q Q
g gs gd
Turn-On Delay Time Turn-On Rise Time -- 170 350 ns Turn-Off Delay Time -- 40 90 ns Turn-Off Fall Time -- 75 160 ns Total Gate Charge Gate-Source Charge -- 7.5 -- nC Gate-Drain Charge -- 18 -- nC
= 40 V, ID = 44 A,
V
DD
= 25
R
G
V
= 64 V, ID = 44 A,
DS
V
GS
= 10 V
(Note 4, 5)
(Note 4, 5)
-- 15 40 ns
-- 38 50 nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.32mH, IAS = 44A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C
3. ISD 44A, di/dt 300A/µs, VDD BV
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Maximum Continuous Drain-Source Diode Forward Current -- -- 44 A Maximum Pulsed Drain-Source Diode Forward Current -- -- 176 A
= 0 V, IS = 44 A
Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 160 -- nC
Starting TJ = 25°C
DSS,
V
GS
= 0 V, IS = 44 A,
V
GS
/ dt = 100 A/µs
dI
F
-- -- 1.5 V
-- 67 -- ns
(Note 4)
Rev. A, August 2000
Page 3
Typical Characteristics
V
GS
2
Top : 15.0 V
10
10.0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V Bottom : 4.5 V
1
10
FQB44N08 / FQI44N08
, Drain Current [A]
D
I
0
10
-1
10
0
10
Notes :
1. 250μs Pulse Test
2. T
= 25
C
1
10
VDS, Drain-Source Voltage [V]
2
10
1
10
175
25
0
10
, Drain Current [A]
D
I
-1
10
246810
VGS, Gate-Source Voltage [V]
-55
Notes :
1. V
= 30V
DS
2. 250μs Pulse Tes t
Figure 2. Transfer CharacteristicsFigure 1. On-Region Char act er i stic s
0.12
0.10
0.08
],
[
0.06
DS(on)
R
VGS = 10V
VGS = 20V
0.04
Drain-Source On-Resistance
0.02
0.00 0 306090120150180
Note : T
ID , Drain Curren t [A]
2
10
1
10
0
10
175
, Reverse Drain Current [A]
DR
= 25
J
I
-1
10
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
25
VSD, Sou r c e - Drain voltage [V ]
Notes :
1. V
= 0V
GS
2. 250μs Pulse Tes t
Figure 3. On-Resistance Variati on vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
3000
2500
2000
1500
1000
Capacitance [pF]
500
0
-1
10
VDS, Drain-Source Voltage [V]
C
= Cgs + Cgd (Cds = shorted)
iss
= Cds + C
C
oss
gd
C
= C
rss
gd
Notes :
= 0 V
1. V
10
1
GS
2. f = 1 MHz
C
iss
C
oss
C
rss
0
10
12
10
8
6
4
, Gate-Source Voltage [V]
2
GS
V
0
0 10203040
QG, Tota l Gate Charge [n C]
VDS = 40V
VDS = 64V
Note : I
Figure 5. Capacitance C haracteristics Figure 6. Gate Charge Characteristics
D
= 44A
Rev. A, August 2000©2000 Fairchild Semiconductor International
Page 4
Typical Characteristics (Continued)
FQB44N08 / FQI44N08
1.2
1.1
1.0
, (Normalized)
DSS
BV
0.9
Drain-Source Breakdown Voltage
0.8
-100 -50 0 50 100 150 200
1. V
2. I
Notes :
TJ, Junction Temperature [oC]
Figure 7. Breakdown Voltage Variation
vs. Temperature
3
10
2
10
1
10
, Drain Current [A]
D
I
0
10
-1
10
0
10
Operation in This Area is Limited by R
DS(on)
1 ms
10 ms
DC
Notes :
1. TC = 25 oC
2. T
= 175 oC
J
3. Single Pulse
1
10
VDS, Drain-Source Voltage [V]
100 µs
= 0 V
GS
= 250 μA
D
3.0
2.5
2.0
1.5
, (No rmaliz ed)
1.0
DS(ON)
R
Drain-Source On-Resistance
0.5
0.0
-100 -50 0 50 100 150 200
Notes :
1. V
= 10 V
GS
2. I
= 22 A
D
TJ, Junction Temperature [oC]
Figure 8. On-Resistance Variation
vs. Temperature
50
40
30
20
, Drain Current [A]
D
I
10
2
10
0
25 50 75 100 125 150 175
TC, Case Temperature [℃]
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
(t), Thermal R esponse
JC
θ
Z
©2000 Fairchild Semiconductor International
vs. Case Temperature
0
10
D=0.5
0.2
0.1
-1
10
0.05
0.02
0.01
-2
10
-5
10
single pulse
-4
10
-3
10
-2
10
Notes :
1. Z
(t) = 1 .18 ℃/W M a x .
θ
JC
2. D u t y F a c t o r , D = t
3. TJM - TC = PDM * Z
P
DM
t
1
t
2
-1
10
10
1/t2
(t)
θ
JC
0
1
10
t1, S q u a re W a v e P u ls e D u ra tio n [s ec ]
Figure 11. Transient Thermal Response Cur ve
Rev. A, August 2000
Page 5
Gate Charge Test Circuit & Waveform
V
V
GS
DS
DS
GS
10V
10V
Q
Q
g
g
Q
Q
gs
gs
Q
Q
gd
gd
Charge
Charge
Same Type
50KΩ
50KΩ
200nF
12V
12V
FQB44N08 / FQI44N08
200nF
3mA
3mA
300nF
300nF
V
V
GS
GS
Same Type
as DUT
as DUT
DUT
DUT
V
V
Resistive Switching Test Circuit & Waveforms
R
R
L
10V
10V
DUT
DUT
L
V
V
DD
DD
V
V
DS
DS
V
V
GS
GS
R
R
G
G
V
V
DS
DS
90%
90%
10%
10%
V
V
GS
GS
t
t
d(on)tr
d(on)tr
t
t
on
on
t
t
d(off)
d(off)
t
t
f
f
t
t
off
off
10V
10V
Unclamped Inductive Switching Test Circuit & Waveforms
BV
BV
DSS
L
LL
V
V
DS
DS
BV
BV
DSS
V
V
DSS
I
I
AS
AS
DD
DD
I
IDI
D
D
R
R
G
G
DUT
DUT
t
t
p
p
V
V
DD
DD
1
1
1
1
----
----
----
----
E
E
=LI
E
=LI
=LI
AS
AS
AS
2
2
2
2
2
2
2
AS
AS
AS
ID (t)
ID (t)
t
t
p
p
DSS
--------------------
-------------------­BV
BV
DSS-VDD
DSS-VDD
Time
Time
V
(t)
V
(t)
DS
DS
Rev. A, August 2000©2000 Fairchild Semiconductor International
Page 6
Peak Diode Recovery dv /d t Test Circuit & Waveforms
+
DUT
DUT
I
I
SD
SD
Driver
Driver
R
R
G
G
V
V
GS
GS
+
V
V
DS
DS
_
_
L
LL
Same Type
Same Type
as DUT
as DUT
• dv/dt controlled by R
• dv/dt controlled by R
•ISDcontroll ed by pulse peri od
•ISDcontroll ed by pulse peri od
G
G
FQB44N08 / FQI44N08
V
V
DD
DD
V
V
GS
GS
( Driver )
( Driver )
I
I
SD
SD
( DUT )
( DUT )
V
V
DS
DS
( DUT )
( DUT )
Gate Pulse Width
Gate Pulse Width
Gate Pulse Width
--------------------------
--------------------------
--------------------------
D =
D =
D =
Gate Pulse Period
Gate Pulse Period
Gate Pulse Period
IFM, Body Diode Forward Current
IFM, Body Diode Forward Current
I
I
RM
RM
Body Diode Reverse Current
Body Diode Reverse Current
Body Diode Recoverydv/dt
Body Diode Recoverydv/dt
V
V
SD
SD
Body Diode
Body Diode
Forward Voltage Drop
Forward Voltage Drop
di/dt
di/dt
10V
10V
V
V
DD
DD
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Page 7
Package Dimensions
D2PAK
4.50 ±0.20
1.30
+0.10 –0.05
(0.40)
9.90
±0.20
FQB44N08 / FQI44N08
1.20 ±0.20
0.10 ±0.15
2.40 ±0.20
0°~3°
+0.10
0.50
–0.05
2.54 ±0.30
1.40 ±0.20
1.27
±0.10
0.80 ±0.10
2.54 TYP 2.54 TYP
9.20 ±0.20
2.00 ±0.10
15.30 ±0.30
4.90 ±0.20
(0.75)
10.00 ±0.20 (8.00) (4.40)
10.00 ±0.20
15.30 ±0.30
(1.75)
(2XR0.45)
(7.20)
9.20 ±0.20
4.90 ±0.20
0.80 ±0.10
Rev. A, August 2000©2000 Fairchild Semiconductor International
Page 8
FQB44N08 / FQI44N08
Package Dimensions
(0.40)
(1.46)
(Continued)
9.90 ±0.20
(45°)
I2PAK
1.20 ±0.20
9.20 ±0.20
4.50 ±0.20
1.30
+0.10 –0.05
(0.94)
1.27 ±0.10 1.47 ±0.10
13.08 ±0.20
10.00 ±0.20
0.80 ±0.10
2.54 TYP2.54 TYP
MAX 3.00
10.08 ±0.20 MAX13.40
0.50
+0.10 –0.05
2.40 ±0.20
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Page 9
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™
2
E
CMOS™ EnSigna™ FACT™ FACT Quiet Series™
®
FAST
FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ POP™ PowerTrench
®
QFET™ QS™ QT Optoelectronics™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design
Preliminary First Production This datasheet contains preliminary data, and
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Obsolete Not In Production This datasheet contains specifications on a product
©2000 Fairchild Semiconductor International
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Semiconductor reserves the right to make changes at any time without notice in order to improve design.
that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. F1
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