Page 1
©2000 Fairchild Semiconductor International
November 2000
Rev. A, November 2000
FQB3N25 / FQI3N25
QFET
QFETQFET
QFET
TM
FQB3N25 / FQI3N25
250V N-Channel M OSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters,
switch mode power supply.
Features
• 2.8A, 250V, R
DS(on)
= 2.2Ω @VGS = 10 V
• Low gate charge ( typical 4.0 nC)
• Low Crss ( typical 4.7 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
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Absolute Maximum Ratings T
C
= 25°C unless otherwise noted
Thermal Characteristics
Symbol Parameter FQB3N25 / FQI3N25 Units
V
DSS
Drain-Source Voltage 250 V
I
D
Drain Current
- Continuous (T
C
= 25°C)
2.8 A
- Continuous (T
C
= 100°C)
1.77 A
I
DM
Drain Current - Pulsed
(Note 1)
11.2 A
V
GSS
Gate-Source Voltage ± 30 V
E
AS
Single Pulsed Avalanche Energy
(Note 2)
40 mJ
I
AR
Avalanche Current
(Note 1)
2.8 A
E
AR
Repetitive Avalanche Energy
(Note 1)
4.5 mJ
dv/dt Peak Diode Recovery dv/dt
(Note 3)
5.5 V/ns
P
D
Power Dissipation (TA = 25°C) *
3.13 W
Power Dissipation (T
C
= 25°C)
45 W
- Derate above 25°C 0.36 W/°C
T
J
, T
STG
Operating and Storage Temperature Range -55 to +150 °C
T
L
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
300 °C
Symbol Parameter Typ Max Units
R
θJC
Thermal Resistance, Junction-to-Case -- 2.78 °C/W
R
θJA
Thermal Resistance, Junction-to-Ambient * -- 40 °C/W
R
θJA
Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W
* When mounted on the minimum pad size recommended (PCB Mount)
S
D
G
D2-PAK
FQB Series
I2-PAK
FQI Series
G
S
D
G
S
D
Page 2
Rev. A, November 2000
FQB3N25 / FQI3N25
(Note 4)
(Note 4, 5)
(Note 4, 5)
(Note 4)
©2000 Fairchild Semiconductor International
Electrical Characteristics T
C
= 25°C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 8.2mH, IAS = 2.8A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 2.8A, di/dt ≤ 300A/µs, VDD ≤ BV
DSS,
Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
Symbol Parameter Te st Conditions Min Typ Max Units
Off Characteristics
BV
DSS
Drain-Source Breakdown Voltage
V
GS
= 0 V, ID = 250 µA
250 -- -- V
∆BV
DSS
/ ∆T
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250 µA, Referenced to 25°C
-- 0.24 -- V/°C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 250 V, VGS = 0 V
-- -- 1 µA
V
DS
= 200 V, TC = 125°C
-- -- 10 µA
I
GSSF
Gate-Body Leakage Current, Forward
V
GS
= 30 V, VDS = 0 V
-- -- 100 nA
I
GSSR
Gate-Body Leakage Current, Reverse
V
GS
= -30 V, VDS = 0 V
-- -- -100 nA
On Characteristics
V
GS(th)
Gate Threshold Voltage
V
DS
= VGS, ID = 250 µA
3.0 -- 5.0 V
R
DS(on)
Static Drain-Source
On-Resistance
V
GS
= 10 V, ID = 1.4 A
-- 1.75 2.2 Ω
g
FS
Forward Transconductance
V
DS
= 50 V, ID = 1.4 A
-- 1.53 -- S
Dynamic Characteristics
C
iss
Input Capacitance
V
DS
= 25 V, VGS = 0 V,
f = 1.0 MHz
-- 130 170 pF
C
oss
Output Capacitance -- 30 40 pF
C
rss
Reverse Transfer Capacitance -- 4.7 6.1 pF
Switching Characteristics
t
d(on)
Turn-On Delay Time
V
DD
= 125 V, ID = 2.8 A,
R
G
= 25 Ω
-- 6.6 23 ns
t
r
Turn-On Rise Time -- 25 60 ns
t
d(off)
Turn-Off Delay Time -- 5.5 21 ns
t
f
Turn-Off Fall Time -- 20 50 ns
Q
g
Total Gate Charge
V
DS
= 200 V, ID = 2.8 A,
V
GS
= 10 V
-- 4.0 5.2 nC
Q
gs
Gate-Source Charge -- 1.1 -- nC
Q
gd
Gate-Drain Charge -- 2.2 -- nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain-Source Diode Forward Current -- -- 2.8 A
I
SM
Maximum Pulsed Drain-Source Diode Forward Current -- -- 11.2 A
V
SD
Drain-Source Diode Forward Voltage
V
GS
= 0 V, IS = 2.8 A
-- -- 1.5 V
t
rr
Reverse Recovery Time
V
GS
= 0 V, IS = 2.8 A,
dI
F
/ dt = 100 A/µs
-- 100 -- ns
Q
rr
Reverse Recovery Charge -- 0.3 - - µC
Page 3
FQB3N25 / FQI3N25
Rev. A, November 2000©2000 Fairchild Semiconductor International
10
-1
10
0
10
1
10
-1
10
0
10
1
V
GS
Top : 15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
Bottom : 5.5 V
※
Notes :
1. 250μs Pulse Test
2. T
C
= 25
℃
I
D
, Drain Current [A]
VDS, Drain-Source Voltage [V]
0123456
0
2
4
6
8
10
VGS = 20V
VGS = 10V
R
DS(on)
[
Ω
],
Drain-Source On-Resistance
ID , Drain Current [A]
012345
0
2
4
6
8
10
12
VDS = 125V
VDS = 50V
VDS = 200V
※
Note : I
D
= 2.8 A
V
GS
, Gate-Source Voltage [V]
QG, Tota l Gate Charge [n C]
10
-1
10
0
10
1
0
50
100
150
200
250
300
C
iss
= Cgs + Cgd (Cds = shorted)
C
oss
= Cds + C
gd
C
rss
= C
gd
※
Note s :
1. V
GS
= 0 V
2. f = 1 MH z
C
rss
C
oss
C
iss
Capacitance [pF]
VDS, Drain-Source Voltage [V]
0.2 0.4 0.6 0.8 1.0 1.2 1.4
10
-1
10
0
10
1
150
℃
※
Notes :
1. V
GS
= 0V
2. 250μs Pulse Test
25
℃
I
DR
, Reverse Drain Current [A]
VSD, Source-Drain voltage [V]
246810
10
-2
10
-1
10
0
10
1
※
Notes :
1. V
DS
= 50V
2. 250μs Pulse Test
-55
℃
25
℃
150
℃
I
D
, Drain Current [A]
VGS , Gate-Source Voltage [V]
Typical Characteristics
Figure 5. Capacitance C haracteristics Figure 6. Gate Charg e C haracteristics
Figure 3. On-Resistance Variati on vs .
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
Figure 2. Transfer CharacteristicsFigure 1. On-Region Charact eristics
Page 4
©2000 Fairchild Semiconductor International
FQB3N25 / FQI3N25
Rev. A, November 2000
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
-2
10
-1
10
0
※
N o te s :
1. Z
θ
JC
(t) = 2.78 ℃/W M ax .
2. D u ty F a c t o r, D = t
1/t2
3. TJM - TC = PDM * Z
θ
JC
(t)
single pulse
D=0.5
0.02
0.2
0.05
0.1
0.01
Z
θ
JC
(t), Therm al Response
t
1
, S q u a re W av e P u ls e D u ra tio n [se c ]
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
※
Notes :
1. V
GS
= 10 V
2. I
D
= 1.4 A
R
DS(ON)
, (No rmaliz e d )
Drain-Source On-Resistance
TJ, Junction Temperature [oC]
25 50 75 100 125 150
0.0
0.5
1.0
1.5
2.0
2.5
3.0
I
D
, Drain Current [A]
TC, Case Temperature [℃]
10
0
10
1
10
2
10
-1
10
0
10
1
DC
10 ms
1 ms
100 µs
Operation in T his Area
is Limited by R
DS(on)
※
Notes :
1. T
C
= 25 oC
2. T
J
= 150 oC
3. Single Pulse
I
D
, Drain Current [A]
VDS, Drain-Source Voltage [V]
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
※
Notes :
1. V
GS
= 0 V
2. I
D
= 250 μA
BV
DSS
, (Normalized)
Drain-Source Breakdown Voltage
TJ, Junction Temperature [oC]
Typical Characteristics (Continued)
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
Figure 7. Breakdo w n Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
Figure 11. Transient Thermal Response Cur ve
t
1
P
DM
t
2
Page 5
FQB3N25 / FQI3N25
Rev. A, November 2000©2000 Fairchild Semiconductor International
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50KΩ
200nF
12V
Same Type
as DUT
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50KΩ
200nF
12V
Same Type
as DUT
V
GS
V
DS
10%
90%
t
d(on)tr
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
V
GS
V
DS
10%
90%
t
d(on)tr
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
E
AS
=LI
AS
2
---2
1
-------------------BV
DSS-VDD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
ID (t)
Time
10V
DUT
R
G
L
I
D
t
p
E
AS
=LI
AS
2
---2
1
E
AS
=LI
AS
2
---2
1
---2
1
-------------------BV
DSS-VDD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
I
AS
V
DS
(t)
ID (t)
Time
10V
DUT
R
G
LL
IDI
D
t
p
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
Page 6
©2000 Fairchild Semiconductor International
FQB3N25 / FQI3N25
Rev. A, November 2000
Peak Diode Recovery dv/d t Test Circuit & Waveforms
DUT
V
DS
+
_
Driver
R
G
Same Type
as DUT
V
GS
• dv/dt controlled by R
G
•ISDcontroll e d by pulse period
V
DD
L
I
SD
10V
V
GS
( Driver )
I
SD
( DUT )
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
V
SD
IFM, Body Diode Forward Current
Body Diode Reverse Current
I
RM
Body Diode Recoverydv/dt
di/dt
D =
Gate Pulse Width
Gate Pulse Period
--------------------------
DUT
V
DS
+
_
Driver
R
G
Same Type
as DUT
V
GS
• dv/dt controlled by R
G
•ISDcontroll e d by pulse period
V
DD
LL
I
SD
10V
V
GS
( Driver )
I
SD
( DUT )
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
V
SD
IFM, Body Diode Forward Current
Body Diode Reverse Current
I
RM
Body Diode Recoverydv/dt
di/dt
D =
Gate Pulse Width
Gate Pulse Period
--------------------------
D =
Gate Pulse Width
Gate Pulse Period
--------------------------
Page 7
FQB3N25 / FQI3N25
Rev. A, November 2000©2000 Fairchild Semiconductor International
Package Dimensions
10.00 ±0.20
10.00 ±0.20
(8.00)
(4.40)
1.27
±0.10
0.80 ±0.10
0.80 ±0.10
(2XR0.45)
9.90
±0.20
4.50 ±0.20
0.10 ±0.15
2.40 ±0.20
2.54 ±0.30
15.30 ±0.30
9.20 ±0.20
4.90 ±0.20
1.40 ±0.20
2.00 ±0.10
(0.75)
(1.75)
(7.20)
0°~3°
1.20 ±0.20
9.20 ±0.20
15.30 ±0.30
4.90 ±0.20
(0.40)
2.54 TYP 2.54 TYP
1.30
+0.10
–0.05
0.50
+0.10
–0.05
D2PAK
Page 8
©2000 Fairchild Semiconductor International
FQB3N25 / FQI3N25
Rev. A, November 2000
Package Dimensions
(Continued)
9.90 ±0.20
2.40 ±0.20
4.50 ±0.20
1.27 ±0.10 1.47 ±0.10
(45°)
0.80 ±0.10
10.00 ±0.20
2.54 TYP2.54 TYP
13.08 ±0.20
9.20 ±0.20
1.20 ±0.20
10.08 ±0.20 MAX13.40
MAX 3.00
(0.40)
(1.46)
(0.94)
1.30
+0.10
–0.05
0.50
+0.10
–0.05
I2PAK
Page 9
©2000 Fairchild Semiconductor International
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DOME™
E
2
CMOS™
EnSigna™
FACT™
FACT Quiet Series™
FAST
®
FASTr™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
POP™
PowerTrench
®
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
INTERNATIONAL.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary First Production This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete Not In Production This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. F1
VCX™
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