Datasheet FQI2P40, FQB2P40 Datasheet (Fairchild Semiconductor)

FQB2P40 / FQI2P40

400V P-Channel MOSFET

December 2000

QFET

QFETQFET

FQB2P40 / FQI2P40

TM

General Description

These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand a high energy pulse in the avalanche and commutation modes. These devices are

Features

• -2.0A, -400V, R

• Low gate charge ( typical 10 nC)

• Low Crss ( typical 6.5 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

= 6.5Ω @VGS = -10 V

DS(on)

well suited for electronic lamp ballasts based on the complementary half bridge topology.

D

G

S

D2-PAK

FQB Series

G

D

Absolute Maximum Ratings T

S

= 25°C unless otherwise noted

C

I2-PAK

FQI Series

G

!!!!

S

!!!!

●●●●

▶▶▶▶

▲▲▲▲

●●●●

!!!!

D

Symbol Parameter FQB2P40 / FQI2P40 Units

V

DSS

I

D

I

DM

V

GSS

E

AS

I

AR

E

AR

dv/dt Peak Diode Recovery dv/dt P

D

Drain-Source Voltage -400 V Drain Current

- Continuous (T

Drain Current - Pulsed

= 25°C)

C

= 100°C)

C

(Note 1)

-2.0 A

-1.27 A

-8.0 A Gate-Source Voltage ± 30 V Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy

Power Dissipation (TA = 25°C) * Power Dissipation (T

= 25°C)

C

(Note 2) (Note 1) (Note 1) (Note 3)

120 mJ

-2.0 A

6.3 mJ

-4.5 V/ns

3.13 W 63 W

- Derate above 25°C 0.51 W/°C

, T

T

J

STG

T

L

Operating and Storage Temperature Range -55 to +150 °C Maximum lead temperature for soldering purposes,

1/8” from case for 5 seconds

300 °C

Thermal Characteristics

Symbol Parameter Typ Max Units

R

θJC

R

θJA

R

θJA

* When mounted on the minimum pad size recommended (PCB Mount)

Thermal Resistance, Junction-to-Case -- 1.98 °C/W Thermal Resistance, Junction-to-Ambient * -- 40 °C/W Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W

Rev. A2, December 2000

FQB2P40 / FQI2P40

Elerical Characteristics T

= 25°C unless otherwise noted

C

Symbol Parameter Te st Conditions Min Typ Max Units

Off Characteristics

BV ∆BV / ∆T I

DSS

I

GSSF

I

GSSR

Drain-Source Breakdown Voltage

DSS

Breakdown Voltage Temperature

DSS

Coefficient

J

Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

= 0 V, ID = -250 µA

V

GS

I

= -250 µA, Referenced to 25°C

D

V

= -400 V, VGS = 0 V

DS

V

= -320 V, TC = 125°C

DS

V

= -30 V, VDS = 0 V

GS

= 30 V, VDS = 0 V

V

GS

-400 -- -- V

-- - -- V/°C

-- -- -1 µA

-- -- -10 µA

-- -- -100 nA

-- -- 100 nA

On Characteristics

V R

g

FS

GS(th)

DS(on)

Gate Threshold Voltage Static Drain-Source

On-Resistance Forward Transconductance

V

= VGS, ID = -250 µA

DS

= -10 V, ID = -1.0 A

V

GS

= -50 V, ID = -1.0 A

V

DS

(Note 4)

-3.0 -- -5.0 V

-- 5.0 6.5 Ω

-- 1.42 -- S

Dynamic Characteristics

C

iss

C

oss

C

rss

Input Capacitance Output Capacitance -- 45 60 pF Reverse Transfer Capacitance -- 6.5 8.5 pF

= -25 V, VGS = 0 V,

V

DS

f = 1.0 MHz

-- 270 350 pF

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q Q Q

g gs gd

Turn-On Delay Time Turn-On Rise Time -- 33 75 ns Turn-Off Delay Time -- 22 55 ns Turn-Off Fall Time -- 25 60 ns Total Gate Charge Gate-Source Charge -- 2.1 -- nC Gate-Drain Charge -- 5.5 -- nC

= -200 V, ID = -2.0 A,

V

DD

= 25 Ω

R

G

V

= -320 V, ID = -2.0 A,

DS

V

GS

= -10 V

(Note 4, 5)

-- 9 30 ns

-- 10 13 nC

Drain-Source Diode Characteristics and Maximum Ratings

I

S

I

SM

V

SD

t

rr

Q

rr

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 52.5mH, IAS = -2.0A, VDD = -50V, RG = 25 Ω, Starting TJ = 25°C

3. ISD ≤ -2.0A, di/dt ≤ 200A/µs, VDD ≤ BV

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Maximum Continuous Drain-Source Diode Forward Current -- -- -2.0 A Maximum Pulsed Drain-Source Diode Forward Current -- -- -8.0 A

= 0 V, IS = -2.0 A

Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 0.85 -- µC

Starting TJ = 25°C

DSS,

V

GS

= 0 V, IS = -2.0 A,

V

GS

/ dt = 100 A/µs

dI

F

-- -- -5.0 V

-- 250 -- ns

(Note 4)

Rev. A2, December 2000

Typical Characteristics

FQB2P40 / FQI2P40

V

GS

Top : -15. 0 V

-10.0 V

-8.0 V

-7.0 V

-6.5 V

0

10

-6.0 V Botto m : -5. 5 V

-1

10

, Drain Current [A]

D

-I

-2

10

-1

10

0

10

※

Notes :

1. 250μs Pulse Tes t

℃

2. T

= 25

C

1

10

-VDS, Drain-Source Voltage [V]

VGS = - 10V

VGS = - 20V

※

Note : T

= 25

J

12

10

[Ω],

8

DS(on)

R

6

Drain-Source On-Resistance

4

0123456

-ID , Drai n Curren t [A]

0

10

, Drain Current [A]

D

-I

-1

10

246810

℃

150

℃

25

-55

℃

※

Notes :

1. V

= -50V

DS

2. 250μs Pulse Tes t

-VGS , Gate-Source Voltage [V]

Figure 2. Transfer CharacteristicsFigure 1. On-Region Char act er i stic s

0

℃

10

℃

25

℃

, Reverse Drain Current [A]

DR

-I

-1

10

150

0.0 0.5 1.0 1.5 2.0 2.5 3.0

※

Notes :

1. V

= 0V

GS

2. 250μs Pulse Tes t

-VSD , Sou r c e-Drain Voltag e [V]

Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

600

500

400

300

200

Capacitance [pF]

100

0

-1

10

Figure 5. Capacitance Characteristics Figure 6. Gate Charge Ch a ra ct eristics

C

iss

C

oss

C

rss

C

iss

C

oss

C

rss

0

10

-VDS, Drain-Source Voltage [V]

= Cgs + Cgd (Cds = shorted) = Cds + C

gd

= C

gd

※

Notes :

= 0 V

1. V

GS

2. f = 1 MHz

1

10

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

VDS = -80V

VDS = -200V

VDS = -320V

※

Note : I

= -2.0 A

D

Rev. A2, December 2000

12

10

8

6

4

, Gate-Source Voltage [V]

GS

2

-V

0

024681012

QG, Tota l Gate Charge [n C]

Typical Characteristics (Continued)

FQB2P40 / FQI2P40

1.2

1.1

1.0

, (Normalized)

DSS

※

-BV

0.9

Drain-Source Breakdown Voltage

0.8

-100 -50 0 50 100 150 200

1. V

2. I

Notes :

TJ, Junction Temperature [oC]

Figure 7. Breakdown Voltage Variation

vs. Temperature

Operation in This Area is Limited by R

※

Notes :

1. T

= 25 oC

C

2. T

= 150 oC

J

3. Single Pulse

1

10

DS(on)

1 ms

10 ms

DC

2

10

1

10

0

10

, Dra i n Current [A]

-1

D

10

-I

-2

10

0

10

-VDS, Drain-Source Voltage [V]

= 0 V

GS

= -250 μA

D

100 µs

2.5

2.0

1.5

, (No rmaliz ed)

1.0

DS(ON)

R

0.5

Drain-Source On-Resistance

0.0

-100 -50 0 50 100 150 200

※

Notes :

1. V

= -10 V

GS

2. I

= -1.0 A

D

TJ, Junction Temperature [oC]

Figure 8. On-Resistance Variation

vs. Temperature

2.0

1.6

1.2

0.8

, Drain Current [A]

D

-I

0.4

3

10

0.0 25 50 75 100 125 150

TC, Case Temperature [℃]

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current

vs. Case Temperature

0

D=0.5

10

※

0.2

0.1

0.05

-1

10

0.02

0.01

(t), Th erm al R e sp o ns e

JC

θ

Z

-2

10

-5

10

sin g le p u ls e

-4

10

-3

10

-2

10

N o te s :

(t) = 1 .98 ℃/W M a x .

1. Z

θ

JC

2. D u ty F a c t o r, D = t

3. TJM - TC = PDM * Z

P

DM

t

1

t

2

-1

10

1/t2

(t)

θ

JC

0

1

10

t1, S q u a re W a v e P u ls e D u ra tio n [s e c ]

Figure 11. Transient Thermal Response Cur ve

Rev. A2, December 2000

12V

200nF

-3mA

50K

FQB2P40 / FQI2P40

Gate Charge Test Circuit & Waveform

V

GS

DS

GS

-10V

Q

g

Q

gs

Q

gd

Charge

Same Type

Ω

300nF

V

GS

Same Type

as DUT

DUT

V

Resistive Switching Test Circuit & Waveforms

-10V

R

L

DUT

L

V

DD

V

GS

10%

V

DS

V

DS

V

GS

R

G

t

d(on)tr

90%

t

on

t

d(off)

t

off

t

f

Unclamped Inductive Switching Test Circuit & Waveforms

BV

DSS

L

LL

V

DS

I

IDI

D

V

DD

BV

DD

I

AS

DSS

R

G

DUT

t

p

V

DD

1

----

E

=LI

E

=LI

AS

2

AS

t

p

I

(t)

D

DSS

--------------------

-------------------BV

BV

DSS-VDD

Time

V

(t)

V

(t)

DS

Rev. A2, December 2000

Peak Diode Recovery dv /d t Test Circuit & Waveforms

+

V

DS

DUT

I

SD

Driver

R

G

V

GS

_

L

LL

Compliment of DUT

(N-Channel)

• dv/dt controlled by R

•ISDcontroll ed by pulse peri od

G

FQB2P40 / FQI2P40

V

DD

V

GS

( Driver )

I

SD

( DUT )

V

DS

( DUT )

Gate Pulse Width

--------------------------

D =

Gate Pulse Period

Body Diode Reverse Current

I

RM

IFM, Body Diode Forward Current

V

SD

Body Diode

Forward Voltage Drop

Body Diode Recoverydv/dt

di/dt

10V

V

DD

Rev. A2, December 2000

Package Dimensions

FQB2P40 / FQI2P40

D2PAK

9.90

±0.20

(0.40)

1.40 ±0.20

1.27

±0.10

0.80 ±0.10

2.54 TYP 2.54 TYP

1.20 ±0.20

9.20 ±0.20

4.90 ±0.20

15.30 ±0.30

2.00 ±0.10

(0.75)

4.50 ±0.20

10.00 ±0.20 (8.00) (4.40)

+0.10

1.30

–0.05

0.10 ±0.15

2.40 ±0.20

0°~3°

+0.10

0.50

–0.05

2.54 ±0.30

10.00 ±0.20

15.30 ±0.30

(1.75)

(2XR0.45)

(7.20)

9.20 ±0.20

4.90 ±0.20

0.80 ±0.10

Rev. A2, December 2000

FQB2P40 / FQI2P40

Package Dimensions

(0.40)

(1.46)

(Continued)

9.90 ±0.20

(45°)

I2PAK

1.20 ±0.20

9.20 ±0.20

4.50 ±0.20

1.30

+0.10 –0.05

(0.94)

1.27 ±0.10 1.47 ±0.10

13.08 ±0.20

10.00 ±0.20

0.80 ±0.10

2.54 TYP2.54 TYP

MAX 3.00

10.08 ±0.20 MAX13.40

0.50

+0.10 –0.05

2.40 ±0.20

Rev. A2, December 2000

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ Bottomless™ CoolFET™ CROSSVOLT™

2

E

CMOS™ FACT™ FACT Quiet Series™

®

FAST FASTr™ GTO™

HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench

®

QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6

SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Production This datasheet contains specifications on a product

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Semiconductor reserves the right to make changes at any time without notice in order to improve design.

that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. A, January 2000