Datasheet FQI17N08L, FQB17N08L Datasheet (Fairchild Semiconductor)

FQB17N08L / FQI17N08L

80V LOGIC N-Channel MOSFET

December 2000

QFET

QFETQFET

FQB17N08L / FQI17N08L

TM

General Description

These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand a high energy pulse in the avalanche and commutation modes. These devices are well suited for low voltage applications such as automotive, high efficiency switching for DC/DC converters, and DC motor control.

D

G

S

D2-PAK

FQB Series

Absolute Maximum Ratings T

Symbol Parameter FQB17N08L / FQI17N08L Units

V

DSS

I

D

I

DM

V

GSS

E

AS

I

AR

E

AR

dv/dt Peak Diode Recovery dv/dt P

D

, T

T

J

STG

T

L

Drain-Source Voltage 80 V Drain Current

Drain Current - Pulsed Gate-Source Voltage ± 20 V Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy

Power Dissipation (TA = 25°C) * Power Dissipation (T

Operating and Storage Temperature Range -55 to +175 °C Maximum lead temperature for soldering purposes,

1/8” from case for 5 seconds

G

D

S

= 25°C unless otherwise noted

C

- Continuous (T

= 25°C)

C

- Derate above 25°C 0.43 W/°C

= 25°C)

C

= 100°C)

C

Features

• 16.5A, 80V, R

• Low gate charge ( typical 8.8 nC)

• Low Crss ( typical 29 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

• 175°C maximum junction temperature rating

• Low level gate drive requirements allowing direct operation from logic drives

I2-PAK

FQI Series

(Note 1)

(Note 2) (Note 1) (Note 1) (Note 3)

= 0.1Ω @VGS = 10 V

DS(on)

!

G

16.5 A

11.6 A 66 A

100 mJ

16.5 A

6.5 mJ

6.5 V/ns

3.75 W 65 W

300 °C

!

D

!

"

" "

"

!

S

Thermal Characteristics

Symbol Parameter Typ Max Units

R

θJC

R

θJA

R

θJA

* When mounted on the minimum pad size recommended (PCB Mount)

Thermal Resistance, Junction-to-Case -- 2.31 °C/W Thermal Resistance, Junction-to-Ambient * -- 40 °C/W Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W

Rev. A2, December 2000

FQB17N08L / FQI17N08L

Electrical Characteristics T

= 25°C unless otherwise noted

C

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

BV ∆BV / ∆T I

DSS

I

GSSF

I

GSSR

Drain-Source Breakdown Voltage

DSS

Breakdown Voltage Temperature

DSS

Coefficient

J

Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

= 0 V, ID = 250 µA

V

GS

I

= 250 µA, Referenced to 25°C

D

V

= 80 V, VGS = 0 V

DS

V

= 64 V, TC = 150°C

DS

V

= 20 V, VDS = 0 V

GS

= -20 V, VDS = 0 V

V

GS

80 -- -- V

-- 0.08 -- V/°C

-- -- 1 µA

-- -- 10 µA

-- -- 100 nA

-- -- -100 nA

On Characteristics

V R

g

FS

GS(th)

DS(on)

Gate Threshold Voltage Static Drain-Source

On-Resistance Forward Transconductance

V

= VGS, ID = 250 µA

DS

V

= 10 V, ID = 8.25 A

GS

= 5 V, ID = 8.25 A

V

GS

V

= 25 V, ID = 8.25 A

DS

(Note 4)

1.0 -- 2.0 V

0.076

--

0.090

0.100

0.115

-- 12.4 -- S

Dynamic Characteristics

C

iss

C

oss

C

rss

Input Capacitance Output Capacitance -- 120 155 pF Reverse Transfer Capacitance -- 29 37 pF

= 25 V, VGS = 0 V,

V

DS

f = 1.0 MHz

-- 400 520 pF

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q Q Q

g gs gd

Turn-On Delay Time Turn-On Rise Time -- 290 590 ns Turn-Off Delay Time -- 20 50 ns Turn-Off Fall Time -- 75 160 ns Total Gate Charge Gate-Source Charge -- 2.0 -- nC Gate-Drain Charge -- 5.4 -- nC

= 40 V, ID = 16.5 A,

V

DD

= 25 Ω

R

G

= 64 V, ID = 16.5 A,

V

DS

V

GS

= 5 V

(Note 4, 5)

-- 7 25 ns

-- 8.8 11.5 nC

Ω

Drain-Source Diode Characteristics and Maximum Ratings

I

S

I

SM

V

SD

t

rr

Q

rr

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 0.5mH, IAS = 16.5A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C

3. ISD ≤ 16.5A, di/dt ≤ 300A/µs, VDD ≤ BV

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Maximum Continuous Drain-Source Diode Forward Current -- -- 16.5 A Maximum Pulsed Drain-Source Diode Forward Current -- -- 66 A

= 0 V, IS = 16.5 A

Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 85 -- nC

Starting TJ = 25°C

DSS,

V

GS

= 0 V, IS = 16.5 A,

V

GS

/ dt = 100 A/µs

dI

F

(Note 4)

-- -- 1.5 V

-- 55 -- ns

Rev. A2, December 2000

Typical Characteristics

FQB17N08L / FQI17N08L

V

GS

Top : 10.0 V

8.0 V

6.0 V

5.0 V

4.5 V

4.0 V

1

3.5 V

10

Bottom : 3.0 V

, Drain Current [A]

D

I

0

10

-1

10

0

10

※

Notes :

1. 250μs Pulse Te st

℃

= 25

2. T

C

1

10

VDS, Drain-Source Voltage [V]

VGS = 10V

VGS = 5V

※

Note : T

= 25

J

0.4

0.3

],

Ω

[

0.2

DS(on)

R

0.1

Drain-Source On-Resistance

0.0 0 1020304050

ID , Drain Curren t [A]

1

10

, Dra in Cu rrent [A]

D

I

℃

175

0

10

℃

25

-1

10

0246810

℃

-55

※

Notes :

1. V

= 25V

DS

2. 250μs Pulse Test

VGS , Gate - Source Voltage [V]

Figure 2. Transfer CharacteristicsFigure 1. On-Region Char act er i stic s

1

10

0

10

, Rever s e Drain Curre n t [A]

DR

℃

I

-1

10

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

℃

175

℃

25

※

Notes :

1. V

= 0V

GS

2. 250μs Pulse Test

VSD , So u rce-Dra in Volta g e [V]

Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

1100 1000

900 800 700 600 500 400

Capacitance [pF]

300 200 100

0

-1

10

C

= Cgs + Cgd (Cds = shorted)

iss

= Cds + C

C

oss

gd

C

= C

rss

gd

※

10

1

Notes :

= 0 V

1. V

GS

2. f = 1 MHz

C

iss

C

oss

C

rss

0

10

VDS, Drain-Source Voltage [V]

12

10

8

6

4

, Gate-Source Voltage [V]

2

GS

V

0

0 2 4 6 8 10121416

QG, Tota l Gate Charge [n C]

VDS = 40V

VDS = 64V

※

Figure 5. Capacitance Characteristics Figure 6. Gate Charge Ch a ra ct eristics

Note : I

= 16.5A

D

Typical Characteristics (Continued)

FQB17N08L / FQI17N08L

1.2

1.1

1.0

, (Norm a liz e d )

DSS

BV

0.9

Drain-Source Breakdown Voltage

0.8

-100 -50 0 50 100 150 200

※

1. V

2. I

Notes :

TJ, Junction Temperature [oC]

Figure 7. Breakdown Voltage Variation

vs. Temperature

Operation in This Area is Limited by R

2

10

1

10

, Drain Current [A]

0

D

10

I

-1

10

0

10

VDS, Drain-Source Voltage [V]

DS(on)

DC

※

Notes :

1. T

= 25 oC

C

= 175 oC

2. T

J

3. Single Pulse

1

10

100 µs

1 ms

10 ms

GS

= 250

D

= 0 V

3.0

2.5

2.0

μ

A

1.5

, (Normalized)

1.0

DS(ON)

R

Drain-Source On-Resistance

0.5

0.0

-100 -50 0 50 100 150 200

※

Notes :

= 10 V

1. V

GS

2. I

= 8.25 A

D

TJ, Junction Temperature [oC]

Figure 8. On-Resistance Variation

vs. Temperature

18

15

12

2

10

9

6

, Drain Current [A]

D

I

3

0

25 50 75 100 125 150 175

TC, Case Temperature [℃]

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current

(t), Therm al Response

JC

θ

Z

vs. Case Temperature

D=0.5

0

10

※

0.2

0.1

0.05

-1

10

0.02

0.01 single pulse

-2

10

-5

10

-4

10

-3

10

-2

10

No te s :

(t) = 2.31 ℃/W M a x .

1. Z

θ

JC

2. D u ty F a c to r, D = t

3. TJM - TC = PDM * Z

P

DM

t

1

t

2

-1

10

1/t2

(t)

θ

JC

0

1

10

t1, Square W ave Pulse Duration [sec]

Figure 11. Transient Thermal Response Cur ve

Rev. A2, December 2000

12V

200nF

3mA

50K

Gate Charge Test Circuit & Waveform

Same Type

Ω

300nF

V

GS

Same Type

as DUT

DUT

V

DS

Resistive Switching Test Circuit & Waveforms

V

5V

GS

FQB17N08L / FQI17N08L

Q

g

Q

gs

Q

gd

Charge

5V

10V

R

L

DUT

L

V

DD

V

DS

V

GS

R

G

V

DS

90%

10%

V

GS

t

d(on)tr

t

on

t

d(off)

t

f

t

off

Unclamped Inductive Switching Test Circuit & Waveforms

BV

DSS

L

LL

V

DS

BV

DSS

V

DSS

I

AS

DD

I

IDI

D

R

G

DUT

t

p

V

DD

1

----

E

=LI

E

=LI

AS

2

AS

(t)

I

D

t

p

DSS

--------------------

-------------------BV

BV

DSS-VDD

Time

V

(t)

V

(t)

DS

Peak Diode Recovery dv /d t Test Circuit & Waveforms

+

DUT

I

SD

Driver

R

G

V

GS

+

V

DS

_

L

LL

Same Type

as DUT

• dv/dt controlled by R

•ISDcontroll ed by pulse peri od

G

FQB17N08L / FQI17N08L

V

DD

V

GS

( Driver )

I

SD

( DUT )

V

DS

( DUT )

Gate Pulse Width

--------------------------

D =

Gate Pulse Period

IFM, Body Diode Forward Current

I

RM

Body Diode Reverse Current

Body Diode Recoverydv/dt

V

SD

Body Diode

Forward Voltage Drop

di/dt

10V

V

DD

Rev. A2, December 2000

Package Dimensions

FQB17N08L / FQI17N08L

D2PAK

9.90

±0.20

(0.40)

1.40 ±0.20

1.27

±0.10

0.80 ±0.10

2.54 TYP 2.54 TYP

1.20 ±0.20

9.20 ±0.20

4.90 ±0.20

15.30 ±0.30

2.00 ±0.10

(0.75)

4.50 ±0.20

10.00 ±0.20 (8.00) (4.40)

+0.10

1.30

–0.05

0.10 ±0.15

2.40 ±0.20

0°~3°

+0.10

0.50

–0.05

2.54 ±0.30

10.00 ±0.20

15.30 ±0.30

(1.75)

(2XR0.45)

(7.20)

9.20 ±0.20

4.90 ±0.20

0.80 ±0.10

FQB17N08L / FQI17N08L

Package Dimensions

(0.40)

(1.46)

(Continued)

9.90 ±0.20

(45°)

I2PAK

1.20 ±0.20

9.20 ±0.20

4.50 ±0.20

1.30

+0.10 –0.05

(0.94)

1.27 ±0.10 1.47 ±0.10

13.08 ±0.20

10.00 ±0.20

0.80 ±0.10

2.54 TYP2.54 TYP

MAX 3.00

10.08 ±0.20 MAX13.40

0.50

+0.10 –0.05

2.40 ±0.20

Rev. A2, December 2000

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™

2

E

CMOS™ EnSigna™ FACT™ FACT Quiet Series™

®

FAST

FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ POP™ PowerTrench

®

QFET™ QS™ QT Optoelectronics™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™

VCX™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Production This datasheet contains specifications on a product

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Semiconductor reserves the right to make changes at any time without notice in order to improve design.

that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. F1