Datasheet FQA34N20L Datasheet (Fairchild Semiconductor)

Page 1
FQA34N20L
FQA34N20L
June 2000
QFET
QFET
QFETQFET
TM
General Description
These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switching DC/DC converters, switch mode power supply, motor control.
G
S
D
Absolute Maximum Ratings T
Symbol Parameter FQA34N20L Units
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt P
D
T
, T
J
STG
T
L
Drain-Source Voltage 200 V Drain Current
Drain Current - Pulsed Gate-Source Voltage ± 20 V Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Power Dissipation (TC = 25°C)
Operating and Storage Temperature Range -55 to +150 °C Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds
- Continuous (T
- Continuous (T
- Derate above 25°C 1.67 W/°C
TO-3P
FQA Series
= 25°C unless otherwise noted
C
= 25°C)
C
= 100°C)
C
Features
• 34A, 200V, R
• Low gate charge ( typical 55 nC)
• Low Crss ( typical 52 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• Low level gate drive requirement allowing direct opration from logic drivers
G
(Note 1)
(Note 2) (Note 1) (Note 1) (Note 3)
= 0.075Ω @VGS = 10 V
DS(on)
D
!
!
"
"
"
"
!
!
"
!
!
" "
"
!
!
S
34 A 21 A
136 A
640 mJ
34 A 21 mJ
5.5 V/ns
210 W
300 °C
Thermal Characteristics
Symbol Parameter Typ Max Units
R
θJC
R
θCS
R
θJA
©2000 Fairchild Semiconductor International
Thermal Resistance, Junction-to-Case -- 0.6 °C/W Thermal Resistance, Case-to-Sink 0.24 -- °C/W Thermal Resistance, Junction-to-Ambient -- 40 °C/W
Rev. A, June 2000
Page 2
FQA34N20L
Electrical Characteristics T
= 25°C unless otherwise noted
C
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV ∆BV / ∆T I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage
DSS
Breakdown Voltage Temperature
DSS
Coefficient
J
Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
= 0 V, ID = 250 µA
V
GS
I
= 250 µA, Referenced to 25°C
D
V
= 200 V, VGS = 0 V
DS
V
= 160 V, TC = 125°C
DS
V
= 20 V, VDS = 0 V
GS
= -20 V, VDS = 0 V
V
GS
200 -- -- V
-- 0.16 -- V/°C
-- -- 1 µA
-- -- 10 µA
-- -- 100 nA
-- -- -100 nA
On Characteristics
V R
g
FS
GS(th)
DS(on)
Gate Threshold Voltage Static Drain-Source
On-Resistance Forward Transconductance
V
= VGS, ID = 250 µA
DS
V
= 10 V, ID = 17 A
GS
= 5 V, ID = 17 A
V
GS
V
= 30 V, ID = 17 A
DS
(Note 4)
1.0 -- 2.0 V
0.057
--
0.060
0.075
0.080
-- 42 -- S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance Output Capacitance -- 400 520 pF Reverse Transfer Capacitance -- 52 67 pF
= 25 V, VGS = 0 V,
V
DS
f = 1.0 MHz
-- 3000 3900 pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q Q Q
g gs gd
Turn-On Delay Time Turn-On Rise Time -- 520 1050 ns Turn-Off Delay Time -- 170 350 n s Turn-Off Fall Time -- 370 75 0 n s Total Gate Charge Gate-Source Charge -- 9.9 -- nC Gate-Drain Charge -- 27 -- nC
= 100 V, ID = 34 A,
V
DD
= 25 Ω
R
G
= 160 V, ID = 34 A,
V
DS
V
GS
= 5 V
(Note 4, 5)
(Note 4, 5)
-- 45 100 ns
-- 55 72 nC
Ω
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.83mH, IAS = 34A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 34A, di/dt ≤ 300A/µs, VDD ≤ BV
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Maximum Continuous Drain-Source Diode Forward Current -- -- 34 A Maximum Pulsed Drain-Source Diode Forward Current -- -- 136 A
= 0 V, IS = 34 A
Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 1.1 -- µC
Starting TJ = 25°C
DSS,
V
GS
= 0 V, IS = 34 A,
V
GS
/ dt = 100 A/µs
dI
F
-- -- 1.5 V
-- 205 -- ns
(Note 4)
Rev. A, June 2000
Page 3
Typical Characteristics
FQA34N20L
V
2
Top : 10.0 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V Bottom : 3.0 V
1
0
-1
10
GS
※
Notes :
1. 250μs Pulse Test
℃
2. T
= 25
C
0
10
1
10
10
10
, Drain Current [A]
D
I
10
VDS, Drai n -Source Voltag e [V]
0.25
0.20
0.15
],
Ω
[
0.10
DS(ON)
R
0.05
Drain-Source On-Resistance
0.00 0306090120
VGS = 5V
VGS = 10V
※
Note : T
℃
= 25
J
ID, Dra i n Current [A]
2
10
1
10
℃
150
0
10
, Dra in Curre n t [A ]
℃
25
D
I
-1
10
0246810
℃
-55
※
Note s :
1. V
= 30V
DS
2. 250μs Pulse Test
VGS , Gate-Source Voltage [V]
Figure 2. Transfer CharacteristicsFigure 1. On-Region Char act er i stic s
2
10
1
10
0
10
, Reverse Drain Current [A]
DR
I
10
℃
150
℃
25
-1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
※
Notes :
= 0V
1. V
GS
2. 250μs Pulse Test
VSD, Sou r c e-Drain voltage [V]
Figure 3. On-Resistance Variati on vs.
Drain Current and Gate Voltage
7000
6300
5600
4900
4200
3500
2800
2100
Capacitance [pF]
1400
700
0
-1
10
Figure 5. Capacitance C haracteristics Figure 6. Gate Charge Characteristics
©2000 Fairchild Semiconductor International
C C C
C
iss
C
oss
C
rss
0
10
VDS, Drain-Source Voltage [V]
= Cgs + Cgd (Cds = shorted)
iss
= Cds + C
oss
gd
= C
rss
gd
※
Notes :
= 0 V
1. V
GS
2. f = 1 MHz
1
10
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
VDS = 40V
※
Note : I
= 34 A
D
Rev. A, June 2000
12
10
8
VDS = 100V
VDS = 160V
6
4
, Gate-Source Voltage [V]
2
GS
V
0
0 20406080100120
QG, Tota l Gate Charge [n C]
Page 4
Typical Characteristics (Continued)
FQA34N20L
1.2
1.1
1.0
, (Norm a liz e d )
DSS
BV
0.9
Drain-Source Breakdown Voltage
0.8
-100 -50 0 50 100 150 200
※
1. V
2. I
Notes :
TJ, Junction Temperature [oC]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Operation in This Area is Limited by R
2
10
1
10
, Dra in Cur re nt [A]
D
0
I
10
-1
10
0
10
DS(on)
1 ms
10 ms
DC
※
Notes :
1. TC = 25 oC
2. T
= 150 oC
J
3. Single Pulse
1
10
VDS, Drain-Source Voltage [V]
100 µs
10
2
= 0 V
GS
= 250 μA
D
2.5
2.0
1.5
, (Normalized)
1.0
DS(ON)
R
0.5
Drain-Source On-Resistance
0.0
-100 -50 0 50 100 150 200
※
Notes :
1. V
= 10 V
GS
2. I
= 17 A
D
TJ, Junction Temperature [oC]
Figure 8. On-Resistance Variation
vs. Temperature
40
30
20
, Drain Current [A]
D
I
10
0
25 50 75 100 125 150
TC, Case Temperature [℃]
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
©2000 Fairchild Semiconductor International
vs. Case Temperature
0
10
D=0.5
0.2
-1
10
0.1
0.05
(t), Th erm al R es p on s e Z
0.02
JC
0.01
θ
-2
10
-5
10
sin g le p u ls e
-4
10
-3
10
t1, S q u a re W a v e P uls e D u ra tio n [se c ]
※
N o te s :
(t) = 0 .6 ℃/W Ma x .
1. Z
θ
JC
2. D u ty F a c t o r, D = t
3. TJM - TC = PDM * Z
P
DM
-2
10
-1
10
1/t2
(t)
θ
JC
t
1
t
2
0
10
1
10
Figure 11. Transient Thermal Response Cur ve
Rev. A, June 2000
Page 5
Gate Charge Test Circuit & Waveform
FQA34N20L
12V
12V
5V
5V
200nF
200nF
3mA
3mA
V
V
GS
DS
DS
5V
5V
GS
Q
Q
g
g
Q
Q
gs
gs
Q
Q
gd
gd
Charge
Charge
50K
50K
Same Type
Ω
Ω
300nF
300nF
V
V
GS
GS
Same Type
as DUT
as DUT
DUT
DUT
V
V
Resistive Switching Test Circuit & Waveforms
R
R
L
DUT
DUT
L
V
V
DD
DD
V
V
DS
DS
V
V
GS
GS
R
R
G
G
V
V
DS
DS
90%
90%
10%
10%
V
V
GS
GS
t
t
d(on)tr
d(on)tr
t
t
on
on
t
t
d(off)
d(off)
t
t
f
f
t
t
off
off
R
R
G
G
10V
10V
t
t
p
p
©2000 Fairchild Semiconductor International
Unclamped Inductive Switching Test Circuit & Waveforms
L
LL
V
V
DS
DS
BV
BV
DSS
V
V
DSS
I
I
AS
AS
DD
DD
I
IDI
D
D
V
V
DD
DD
DUT
DUT
1
1
1
1
----
----
----
----
E
E
=LI
E
=LI
=LI
AS
AS
AS
2
2
2
2
2
2
2
AS
AS
AS
(t)
(t)
I
I
D
D
t
t
p
p
BV
BV
DSS
DSS
--------------------
-------------------­BV
BV
DSS-VDD
DSS-VDD
Time
Time
V
(t)
V
(t)
DS
DS
Rev. A, June 2000
Page 6
Peak Diode Recovery dv /d t Test Circuit & Waveforms
+
DUT
DUT
I
I
SD
SD
Driver
Driver
R
R
G
G
V
V
GS
GS
+
V
V
DS
DS
_
_
L
LL
Same Type
Same Type
as DUT
as DUT
• dv/dt controlled by R
• dv/dt controlled by R
•ISDcontroll ed by pulse peri od
•ISDcontroll ed by pulse peri od
G
G
FQA34N20L
V
V
DD
DD
V
V
GS
GS
( Driver )
( Driver )
I
I
SD
SD
( DUT )
( DUT )
V
V
DS
DS
( DUT )
( DUT )
Gate Pulse Width
Gate Pulse Width
Gate Pulse Width
--------------------------
--------------------------
--------------------------
D =
D =
D =
Gate Pulse Period
Gate Pulse Period
Gate Pulse Period
IFM, Body Diode Forward Current
IFM, Body Diode Forward Current
I
I
RM
RM
Body Diode Reverse Current
Body Diode Reverse Current
Body Diode Recoverydv/dt
Body Diode Recoverydv/dt
V
V
SD
SD
Body Diode
Body Diode
Forward Voltage Drop
Forward Voltage Drop
di/dt
di/dt
10V
10V
V
V
DD
DD
©2000 Fairchild Semiconductor International
Rev. A, June 2000
Page 7
Package Dimensions
FQA34N20L
ø3.20 ±0.10
15.60 ±0.20
13.60 ±0.20
9.60 ±0.20
TO-3P
3.80 ±0.20
4.80 ±0.20
+0.15
1.50
–0.05
13.90 ±0.20
2.00 ±0.20
3.00 ±0.20
1.00 ±0.20
5.45TYP
±0.30]
[5.45
5.45TYP
±0.30]
[5.45
12.76 ±0.20
19.90 ±0.20
3.50 ±0.20
23.40 ±0.20
16.50 ±0.30
18.70 ±0.20
1.40 ±0.20
+0.15
0.60
–0.05
©2000 Fairchild Semiconductor International
Rev. A, June 2000
Page 8
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™ E2CMOS EnSigna
TM
TM
FACT™ FACT Quiet Series™
®
FAST
FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ POP™ PowerTrench
®
QFET™ QS™ QT Optoelectronics™
Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. F1
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