Datasheet FQA160N08 Datasheet (Fairchild Semiconductor)

Page 1
FQA160N08
FQA160N08
September 2000
QFET
QFET
QFETQFET
TM
General Description
These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for low voltage applications such as automotive, high efficiency switching for DC/DC converters, and DC motor control.
G
SD
Absolute Maximum Ratings T
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt P
D
T
, T
J
STG
T
L
Drain-Source Voltage 80 V Drain Current
Drain Current - Pulsed Gate-Source Voltage ± 25 V Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Power Dissipation (TC = 25°C)
Operating and Storage Temperature Range -55 to +175 °C Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds
Parameter FQA160N08 Units
- Continuous (T
- Continuous (T
- Derate above 25°C 2.5 W/°C
TO-3P
FQA Series
= 25°C unless otherwise noted
C
= 25°C)
C
= 100°C)
C
Features
• 160A, 80V, R
• Low gate charge ( typical 220 nC)
• Low Crss ( typical 530 pF)
•Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• 175°C maximum junction temperature rating
G
(Note 1)
(Note 2) (Note 1) (Note 1) (Note 3)
= 0.007Ω @VGS = 10 V
DS(on)
D
!
!
"
"
"
"
!
!
"
!
!
" "
"
!
!
S
160 A 113 A 640 A
1600 mJ
160 A
37.5 mJ
6.5 V/ns
375 W
300 °C
Thermal Characteristics
Symbol Parameter Typ Max Units
R
θJC
R
θCS
R
θJA
©2000 Fairchild Semiconductor International
Thermal Resistance, Junction-to-Case -- 0.4 °C/W Thermal Resistance, Case-to-Sink 0.24 -- °C/W Thermal Resistance, Junction-to-Ambient -- 40 °C/W
Rev. A, September 2000
Page 2
FQA160N08
Electrical Characteristics
T
= 25°C unless otherwise noted
C
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
∆BV
DSS
/ ∆T I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage Breakdown Voltage Temperature
Coefficient
J
Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
= 0 V, ID = 250 µA
V
GS
I
= 250 µA, Referenced to 25°C
D
V
= 80 V, VGS = 0 V
DS
V
= 64 V, TC = 150°C
DS
= 25 V, VDS = 0 V
V
GS
= -25 V, VDS = 0 V
V
GS
80 -- -- V
-- 0.08 -- V/°C
-- -- 1 µA
-- -- 10 µA
-- -- 100 nA
-- -- -100 nA
On Characteristics
V
GS(th)
R
DS(on)
g
FS
Gate Threshold Voltage Static Drain-Source
On-Resistance Forward Transconductance
= VGS, ID = 250 µA
V
DS
V
= 10 V, ID = 80 A
GS
= 30 V, ID = 80 A
V
DS
(Note 4)
2.0 -- 4.0 V
-- 0.0056 0.007 Ω
-- 92 -- S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance Output Capacitance -- 2400 3100 pF Reverse Transfer Capacitance -- 530 690 pF
V
= 25 V, VGS = 0 V,
DS
f = 1.0 MHz
-- 6100 7900 pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q Q Q
g gs gd
Turn-On Delay Time Turn-On Rise Time -- 970 2000 ns Turn-Off Delay Time -- 260 530 ns Turn-Off Fall Time -- 410 830 ns Total Gate Charge Gate-Source Charge -- 43 -- nC Gate-Drain Charge -- 120 -- nC
= 40 V, ID = 160 A,
V
DD
R
= 25 Ω
G
V
= 64 V, ID = 160 A,
DS
= 10 V
V
GS
(Note 4, 5)
(Note 4, 5)
-- 85 180 ns
-- 225 290 nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.086mH, IAS = 160A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 160A, di/dt ≤ 300A/µs, VDD ≤ BV
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temp er at ur e
6. Continuous Drain Current Calculated by Maximum Junction Temperature : Limited by Package
©2000 Fairchild Semiconductor International
Maximum Continuous Drain-Source Diode Forward Current -- -- 160 A Maximum Pulsed Drain-Source Diode Forward Current -- -- 640 A
= 0 V, IS = 160 A
Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 510 -- nC
Starting TJ = 25°C
DSS,
V
GS
V
= 0 V, IS = 160 A,
GS
/ dt = 100 A/µs
dI
F
(Note 6)
-- -- 1.5 V
-- 125 -- ns
(Note 4)
Rev. A, September 2000
Page 3
Typical Characteristics
V Top : 1 5 .0 V
10
, Drain Current [A]
D
I
10
10.0 V
8.0 V
7.0 V
6.0 V
5.5 V
2
5.0 V Bottom : 4 .5 V
1
-1
10
FQA160N08
20
15
],
Ω
[m
10
DS(ON)
R
5
Drain-Source On-Resistance
0
0 200 400 600 800 1000
GS
0
10
VDS, Drain-Source Voltage [V]
VGS = 10V
VGS = 20V
ID , Drain Current [A]
2
10
℃
175
1
10
℃
25
0
, Dra in Current [A]
D
10
I
-1
10
246810
※
Notes :
1. 250μs Pulse Test
℃
2. T
= 25
C
1
10
℃
-55
※
Notes :
1. V
= 30V
DS
2. 250μs Pulse Test
VGS, Gate-Source Voltage [V]
Figure 2. Transfer CharacteristicsFigure 1. On-Region Characteristics
2
10
1
10
0
10
, Reverse Drain Curre n t [A]
175
DR
I
-1
10
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
℃
℃
25
※
Note : T
℃
= 25
J
VSD, Source-Drain voltage [V]
※
Notes :
1. V
= 0V
GS
2. 250μs Pulse Test
Figure 3. On-Resistance Variation vs.
Drain Current and Gate V oltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
20000 18000
16000
14000 12000
10000
8000
6000
Capacitance [pF]
4000 2000
0
-1
10
C
= Cgs + Cgd (Cds = shorted)
iss
C
= Cds + C
oss
gd
C
= C
rss
gd
※
Notes :
1. V
= 0 V
C
iss
C
oss
C
rss
0
10
10
1
GS
2. f = 1 MHz
VDS, Drain-Source Voltage [V]
12
10
8
6
4
, Gate-Source Voltage [V]
2
GS
V
0
0 40 80 120 160 200 240
QG, Tota l Gate Char g e [ n C]
VDS = 40V
VDS = 64V
※
Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics
Note : I
= 160A
D
Rev. A, September 2000©2000 Fairchild Semiconductor International
Page 4
Typical Characteristics (Continued)
FQA160N08
1.2
1.1
1.0
, (Normalized)
DSS
BV
0.9
Drain-Source Breakdown Voltage
0.8
-100 -50 0 50 100 150 200
※
1. V
2. I
Note s :
TJ, Junction Temperature [oC]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Operation in This Area is Limited by R
3
10
2
10
1
10
, Drain Current [A]
D
I
0
10
-1
10
0
10
VDS, Drain-Source Voltage [V]
DS(on)
DC
※
Notes :
1. T
= 25 oC
C
2. T
= 175 oC
J
3. Sing le Pulse
1
10
10 ms
1 ms
100 µs
= 0 V
GS
= 250 μA
D
10 µs
3.0
2.5
2.0
1.5
, (Normalized)
1.0
DS(ON)
R
Drain-Source On-Resistance
0.5
0.0
-100 -50 0 50 100 150 200
※
Notes :
= 10 V
1. V
GS
2. I
= 80 A
D
TJ, Junction Temperature [oC]
Figure 8. On-Resistance Variation
vs. Temperature
180
150
120
2
10
90
60
, Drain Current [A]
D
I
30
0
Limited by Package
25 50 75 100 125 150 175
TC, Case Temperature [℃]
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
©2000 Fairchild Semiconductor International
vs. Case Temperature
D=0.5
※
-1
10
0.2
0.1
Notes :
1. Z
(t) = 0.4 ℃/W M a x.
θ
JC
2. D u ty F a c to r , D = t
3. TJM - TC = PDM * Z
1/t2
(t)
θ
JC
0.05
P
0.02
(t), Thermal Response
JC
-2
0.01
10
θ
Z
-5
10
single pulse
-4
10
-3
10
-2
10
DM
t
1
t
2
-1
10
0
10
1
10
t1, S q u ar e W a v e P uls e D u ra tion [s e c ]
Figure 11. Transient Thermal Response Curve
Rev. A, September 2000
Page 5
Gate Charge Test Circuit & Waveform
FQA160N08
12V
12V
10V
10V
200nF
200nF
3mA
3mA
V
V
GS
DS
DS
GS
10V
10V
Q
Q
g
g
Q
Q
gs
gs
Q
Q
gd
gd
Charge
Charge
50K
50K
Same Type
Ω
Ω
300nF
300nF
V
V
GS
GS
Same Type
as DUT
as DUT
DUT
DUT
V
V
Resistive Switching Test Circuit & Waveforms
R
R
L
DUT
DUT
L
V
V
DD
DD
V
V
DS
DS
V
V
GS
GS
R
R
G
G
V
V
DS
DS
90%
90%
10%
10%
V
V
GS
GS
t
t
d(on)tr
d(on)tr
t
t
on
on
t
t
d(off )
d(off )
t
t
f
f
t
t
off
off
10V
10V
Unclamped Inductive Switching Test Circuit & Waveforms
BV
BV
DSS
L
LL
V
V
DS
DS
BV
BV
DSS
V
V
DSS
I
I
AS
AS
DD
DD
I
IDI
D
D
R
R
G
G
DUT
DUT
t
t
p
p
V
V
DD
DD
1
1
1
1
----
----
----
----
E
E
=LI
E
=LI
=LI
AS
AS
AS
2
2
2
2
2
2
2
AS
AS
AS
I
I
(t)
(t)
D
D
t
t
p
p
DSS
--------------------
-------------------­BV
BV
DSS-VDD
DSS-VDD
Time
Time
V
(t)
V
(t)
DS
DS
Rev. A, September 2000©2000 Fairchild Semiconductor International
Page 6
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
DUT
DUT
I
I
SD
SD
Driver
Driver
R
R
G
G
V
V
GS
GS
+
V
V
DS
DS
_
_
L
LL
Same Type
Same Type
as DUT
as DUT
• dv /dt controlled by R
• dv /dt controlled by R
•ISDcontrolled by pulse period
•ISDcontrolled by pulse period
G
G
FQA160N08
V
V
DD
DD
V
V
GS
GS
( Driver )
( Driver )
I
I
SD
SD
( DUT )
( DUT )
V
V
DS
DS
( DUT )
( DUT )
Gate Pulse Width
Gate Pulse Width
Gate Pulse Width
--------------------------
--------------------------
--------------------------
D =
D =
D =
Gate Pulse Period
Gate Pulse Period
Gate Pulse Period
IFM, Body Diode Forward Current
IFM, Body Diode Forward Current
I
I
RM
RM
Body Diode Reverse Current
Body Diode Reverse Current
Body Diode Recoverydv/dt
Body Diode Recoverydv/dt
V
V
SD
SD
Body Diode
Body Diode
Forward Voltage Drop
Forward Voltage Drop
di/dt
di/dt
10V
10V
V
V
DD
DD
©2000 Fairchild Semiconductor International
Rev. A, September 2000
Page 7
Package Dimensions
FQA160N08
ø3.20 ±0.10
15.60 ±0.20
13.60 ±0.20
9.60 ±0.20
TO-3P
3.80 ±0.20
4.80 ±0.20
+0.15
1.50
–0.05
13.90 ±0.20
2.00 ±0.20
3.00 ±0.20
1.00 ±0.20
5.45TYP
±0.30]
[5.45
5.45TYP
±0.30]
[5.45
12.76 ±0.20
19.90 ±0.20
3.50 ±0.20
23.40 ±0.20
16.50 ±0.30
18.70 ±0.20
1.40 ±0.20
+0.15
0.60
–0.05
Rev. A, September 2000©2000 Fairchild Semiconductor International
Page 8
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™
2
E
CMOS™ EnSigna™ FACT™ FACT Quiet Series™
®
FAST
FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ POP™ PowerTrench
®
QFET™ QS™ QT Optoelectronics™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design
Preliminary First Production This datasheet contains preliminary data, and
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Obsolete Not In Production This datasheet contains specifications on a product
©2000 Fairchild Semiconductor International
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Semiconductor reserves the right to make changes at any time without notice in order to improve design.
that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. F1
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