Datasheet FQA12P20 Datasheet (Fairchild Semiconductor)

Page 1
FQA12P20
FQA12P20
May 2000
QFET
QFET
QFETQFET
TM
General Description
These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well
Features
• -12.6A, -200V, R
• Low gate charge ( typical 31 nC)
• Low Crss ( typical 30 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
= 0.47Ω @VGS = -10 V
DS(on)
suited for high efficiency switching DC/DC converters.
S
!!!!
!!!!
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▶▶▶▶
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▲▲▲▲
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!!!!
!!!!
D
G
S
D
Absolute Maximum Ratings T
TO-3P
FQA Series
= 25°C unless otherwise noted
C
G
!!!!
!!!!
Symbol Parameter FQA12P20 Units
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt P
D
Drain-Source Voltage -200 V Drain Current
- Continuous (T
- Continuous (T
Drain Current - Pulsed
= 25°C)
C
= 100°C)
C
(Note 1)
-12.6 A
-7.9 A
-50.4 A Gate-Source Voltage ± 30 V Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Power Dissipation (TC = 25°C)
(Note 2) (Note 1) (Note 1) (Note 3)
810 mJ
-12.6 A
15 mJ
-5.5 V/ns 150 W
- Derate above 25°C 1.2 W/°C
T
, T
J
STG
T
L
Operating and Storage Temperature Range -55 to +150 °C Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds
300 °C
Thermal Characteristics
Symbol Parameter Typ Max Units
R
θJC
R
θCS
R
θJA
©2000 Fairchild Semiconductor International
Thermal Resistance, Junction-to-Case -- 0.83 °C/W Thermal Resistance, Case-to-Sink 0.24 -- °C/W Thermal Resistance, Junction-to-Ambient -- 40 °C/W
Rev. B, May 2000
Page 2
FQA12P20
Elerical Characteristics T
= 25°C unless otherwise noted
C
Symbol Parameter Te st Conditions Min Typ Max Units
Off Characteristics
BV
DSS
∆BV
DSS
/ ∆T I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage Breakdown Voltage Temperature
Coefficient
J
Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
= 0 V, ID = -250 µA
V
GS
I
= -250 µA, Referenced to 25°C
D
V
= -200 V, VGS = 0 V
DS
V
= -160 V, TC = 125°C
DS
V
= -30 V, VDS = 0 V
GS
= 30 V, VDS = 0 V
V
GS
-200 -- -- V
-- - -- V/°C
-- -- -1 µA
-- -- -10 µA
-- -- -100 nA
-- -- 100 nA
On Characteristics
V R
g
FS
GS(th)
DS(on)
Gate Threshold Voltage Static Drain-Source
On-Resistance Forward Transconductance
V
= VGS, ID = -250 µA
DS
= -10 V, ID = -6.3 A
V
GS
= -40 V, ID = -6.3 A
V
DS
(Note 4)
-3.0 -- -5.0 V
-- 0.36 0.47 Ω
-- 6.6 -- S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance Output Capacitance -- 190 250 pF Reverse Transfer Capacitance -- 3 0 40 pF
= -25 V, VGS = 0 V,
V
DS
f = 1.0 MHz
-- 920 1200 pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q Q Q
g gs gd
Turn-On Delay Time Turn-On Rise Time -- 195 400 ns Turn-Off Delay Time -- 40 90 ns Turn-Off Fall Time -- 60 13 0 ns Total Gate Charge Gate-Source Charge -- 8.1 -- nC Gate-Drain Charge -- 16 -- nC
= -100 V, ID = -11.5 A,
V
DD
= 25 Ω
R
G
V
= -160 V, ID = -11.5 A,
DS
V
GS
= -10 V
(Note 4, 5)
(Note 4, 5)
-- 20 50 ns
-- 31 40 nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 7.65mH, IAS = -12.6A, VDD = -50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ -11.5A, di/dt ≤ 300A/µs, VDD ≤ BV
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Maximum Continuous Drain-Source Diode Forward Current -- -- -12.6 A Maximum Pulsed Drain-Source Diode Forward Current -- -- -50.4 A
= 0 V, IS = -12.6 A
Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge -- 1.44 -- µC
Starting TJ = 25°C
DSS,
V
GS
= 0 V, IS = -11.5 A,
V
GS
/ dt = 100 A/µs
dI
F
-- -- -5.0 V
-- 180 -- ns
(Note 4)
Rev. B, May 2000
Page 3
Typical Characteristics
V
FQA12P20
10
10
, Drain Current [A]
D
-I
10
Top : -15.0 V
-10.0 V
-8.0 V
-7.0 V
1
-6.5 V
-6.0 V Bottom : -5.5 V
0
-1
-1
10
GS
0
10
-VDS, Drain-Source Voltage [V]
※
Notes :
1. 250μs Pulse Test
℃
2. T
= 25
C
1
10
1
10
0
10
, Drain Current [A]
D
-I
-1
10
246810
℃
150
℃
25
-VGS , Gate-Source Voltage [V]
※
℃
-55
Notes :
1. V
= -40V
DS
2. 250μs Pulse Test
Figure 2. Transfer CharacteristicsFigure 1. On-Region Char act er i stic s
2.0
1.5
],
Ω
[
1.0
DS(on)
R
0.5
Drain-Source On-Resistance
0.0 0 10203040
VGS = - 10V
VGS = - 20V
※
Note : T
℃
= 25
J
-ID , Drai n Curren t [A]
1
10
0
10
, Reve rs e D ra in Current [A ]
DR
-I
-1
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0
℃
150
-VSD , Source-Drain Voltage [V]
※
℃
25
Notes :
= 0V
1. V
GS
2. 250μs Pulse Test
Figure 3. On-Resistance Variati on vs.
Drain Current and Gate Voltage
2400
2000
1600
1200
800
Capacitance [pF]
400
0
-1
10
Figure 5. Capacitance C haracteristics Figure 6. Gate Charge Characteristics
©2000 Fairchild Semiconductor International
C
iss
C
oss
C
rss
C
iss
C
oss
C
rss
0
10
-VDS, Drain-Source Voltage [V]
= Cgs + Cgd (Cds = shorted)
= Cds + C
gd
= C
gd
※
Notes :
= 0 V
1. V
GS
2. f = 1 MHz
1
10
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
12
10
8
6
4
, Gate-Source Voltage [V]
GS
2
-V
0
0 5 10 15 20 25 30 35
QG, Tota l Gate Charge [n C]
VDS = -40V
VDS = -100V
VDS = -160V
※
Note : I
= -11.5 A
D
Rev. B, May 2000
Page 4
Typical Characteristics (Continued)
FQA12P20
1.2
1.1
1.0
, (Norm a liz e d )
DSS
※
-BV
0.9
Drain-Source Breakdown Voltage
0.8
-100 -50 0 50 100 150 200
1. V
2. I
Notes :
TJ, Junction Temperature [oC]
Figure 7. Breakdown Voltage Variation
vs. Temperature
2
10
1
10
0
, Dra i n Curre nt [A]
10
D
-I
-1
10
0
10
Operation in This Area is Limited by R
DS(on)
1 ms
10 ms
DC
※
Notes :
1. T
= 25 oC
C
2. T
= 150 oC
J
3. Single Pulse
1
10
-VDS, Drain-Source Voltage [V]
10
100 µs
2
GS
= -250
D
= 0 V
2.5
2.0
1.5
, (No rmaliz e d )
1.0
DS(ON)
R
0.5
μ
A
Drain-Source On-Resistance
0.0
-100 -50 0 50 100 150 200
※
Notes :
= -10 V
1. V
GS
2. I
= -5.75 A
D
TJ, Junction Temperature [oC]
Figure 8. On-Resistance Variation
vs. Temperature
15
12
9
6
, Drain Current [A]
D
-I
3
0
25 50 75 100 125 150
TC, Case Temperature [℃]
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
©2000 Fairchild Semiconductor International
vs. Case Temperature
0
10
D=0.5
※
0.2
-1
0.1
10
N o te s :
1. Z
(t) = 0.83 ℃/W M ax.
θ
JC
2. D u ty F a c t o r, D = t
3. TJM - TC = PDM * Z
1/t2
(t)
θ
JC
0.05
P
0.02
(t), Therm al Response
0.01
JC
θ
Z
-2
10
-5
10
single pulse
-4
10
-3
10
-2
10
DM
t
1
t
2
-1
10
0
10
1
10
t1, S q u a re W a v e P u lse D ura tio n [s e c ]
Figure 11. Transient Thermal Response Cur ve
Rev. B, May 2000
Page 5
Gate Charge Test Circuit & Waveform
FQA12P20
V
V
GS
DS
DS
GS
-10V
-10V
V
V
GS
GS
10%
10%
Q
Q
gs
gs
t
t
d(on)tr
d(on)tr
Q
Q
g
g
Q
Q
gd
gd
Charge
Charge
t
t
on
on
t
t
d(off)
d(off)
t
t
off
off
t
t
f
f
12V
12V
200nF
200nF
-3mA
-3mA
Same Type
50K
50K
Ω
Ω
300nF
300nF
V
V
GS
GS
Same Type
as DUT
as DUT
DUT
DUT
V
V
Resistive Switching Test Circuit & Waveforms
R
R
L
V
V
DS
DS
V
V
GS
GS
R
R
G
G
L
V
V
DD
DD
-10V
-10V
-10V
-10V
DUT
DUT
90%
90%
V
V
DS
DS
Unclamped Inductive Switching Test Circuit & Waveforms
BV
BV
DSS
L
LL
V
V
DS
DS
I
IDI
D
D
V
V
DD
BV
BV
DD
I
I
AS
AS
DSS
DSS
R
R
G
G
DUT
DUT
t
t
p
p
V
V
DD
DD
1
1
1
1
----
----
----
----
E
E
=LI
E
=LI
=LI
AS
AS
AS
2
2
2
2
2
2
2
AS
AS
AS
t
t
p
p
I
I
(t)
(t)
D
D
DSS
--------------------
-------------------­BV
BV
DSS-VDD
DSS-VDD
Time
Time
V
(t)
V
(t)
DS
DS
©2000 Fairchild Semiconductor International
Rev. B, May 2000
Page 6
Peak Diode Recovery dv /d t Test Circuit & Waveforms
+
+
V
V
DS
DS
DUT
DUT
I
I
SD
SD
Driver
Driver
R
R
G
G
V
V
GS
GS
_
_
L
LL
Compliment of DUT
Compliment of DUT
(N-Channel)
(N-Channel)
• dv/dt controlled by R
• dv/dt controlled by R
•ISDcontroll ed by pulse peri od
•ISDcontroll ed by pulse peri od
G
G
FQA12P20
V
V
DD
DD
V
V
GS
GS
( Driver )
( Driver )
I
I
SD
SD
( DUT )
( DUT )
V
V
DS
DS
( DUT )
( DUT )
Gate Pulse Width
Gate Pulse Width
Gate Pulse Width
--------------------------
--------------------------
--------------------------
D =
D =
D =
Gate Pulse Period
Gate Pulse Period
Gate Pulse Period
Body Diode Reverse Current
Body Diode Reverse Current
I
I
RM
RM
IFM, Body Diode Forward Current
IFM, Body Diode Forward Current
V
V
SD
SD
Body Diode
Body Diode
Forward Voltage Drop
Forward Voltage Drop
Body Diode Recoverydv/dt
Body Diode Recoverydv/dt
di/dt
di/dt
10V
10V
V
V
DD
DD
©2000 Fairchild Semiconductor International
Rev. B, May 2000
Page 7
Package Dimensions
FQA12P20
ø3.20 ±0.10
15.60 ±0.20
13.60 ±0.20
9.60 ±0.20
TO-3P
3.80 ±0.20
4.80 ±0.20
+0.15
1.50
–0.05
13.90 ±0.20
2.00 ±0.20
3.00 ±0.20
1.00 ±0.20
5.45TYP
±0.30]
[5.45
5.45TYP
±0.30]
[5.45
12.76 ±0.20
19.90 ±0.20
3.50 ±0.20
23.40 ±0.20
16.50 ±0.30
18.70 ±0.20
1.40 ±0.20
+0.15
0.60
–0.05
©2000 Fairchild Semiconductor International
Rev. B, May 2000
Page 8
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™ E2CMOS EnSigna
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FACT™ FACT Quiet Series™
FAST
FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ P ACMAN™ POP™
PowerTrench
QFET™ QS™ QT Optoelectronics™
Quiet Series™ SILENT SWITCHER SMART ST ART™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8
SyncFET™ TinyLogic™ UHC™ VCX™
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN T O IMPROVE RELIABILITY , FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS P ATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORA TION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
PRODUCT STA TUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. G
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