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FM25160
16Kb FRAM Serial Memory
Features
16K bit Ferroelectric Nonvolatile RAM
• Organized as 2,048 x 8 bits
• High endurance 10 Billion (1010) read/writes
• 10 year data retention at 85° C
• NoDelay™ write
• Advanced high-reliability ferroelectric process
Fast Serial Peripheral Interface - SPI
• Up to 2.1 MHz maximum bus frequency
• Direct hardware replacement for EEPROM
• Supports SPI Mode 0 (CPOL=0, CPHA=0)
Description
The FM25160 is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile but operates in other respects as a RAM.
It provides reliable data retention for 10 years while
eliminating the complexities, overhead, and system
level reliability problems caused by EEPROM and
other nonvolatile memories.
Unlike serial EEPROMs, the FM25160 performs
write operations at bus speed. No write delays are
incurred. Data is written to the memory array mere
hundreds of nanoseconds after it has been
successfully transferred to the device. The next bus
cycle may c7ommence immediately. In addition, the
product offers substantial write endurance compared
with other nonvolatile memories. The FM25160 is
capable of supporting up to 1E10 read/write cycles -far more than most systems will require from a serial
memory.
These capabilities make the FM25160 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.
The FM25160 provides substantial benefits to users
of serial EEPROM, in a hardware drop-in
replacement. The FM25160 uses the high-speed SPI
bus, which enhances the high-speed write capability
of FRAM technology. It is guaranteed over an
industrial temperature range of -40°C to +85°C.
Sophisticated Write Protection Scheme
• Hardware protection
• Software protection
Low Power Consumption
• 10 µA standby current
Industry Standard Configuration
• Industrial temperature -40° C to +85° C
• 8-pin SOP or DIP
Pin Configuration
CS
SO
WP
VSS
Pin Names Function
/CS Chip Select
SO Serial Data Output
/WP Write Protect
VSS Ground
SI Serial Data Input
SCK Serial Clock
/HOLD Hold
VCC Supply Voltage 5V
VCC
HOLD
SCK
SI
Ordering Information
FM25160-P 8-pin plastic DIP
FM25160-S 8-pin SOP
This data sheet contains design specifications for product development. Ramtron International Corporation
These specifications may change in any manner without notice 1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058
www.ramtron.com
12 May 2000 1/14
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Ramtron FM25160
Figure 1. Block Diagram
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Ramtron FM25160
Pin Description
Pin Name Pin Number I/O Pin Description
/CS 1 I Chip Select. Activates the device. When high, all outputs are tri-state and
the device ignores other inputs. The part remains in a low power standby
mode. When low, the part recognizes activity on the SCK signal. A
falling edge on /CS must occur prior to every op-code.
SO 2 O Serial Output. SO is the data output pin. It is driven actively during a read
and remains tri-state at all other times including when HOLD\ is low.
Data transitions are driven on the falling edge of the serial clock.
* SO can be connected to SI for a single pin data interface since the part
communicates in half-duplex.
/WP 3 I Write Protect. This pin prevents write operations to the status register.
This is critical since many other write protection features are controlled
through the status register. A complete explanation of write protection is
provided below. *Note that the function of /WP is different from the
FM25040 where it prevent all writes to the part.
VSS 4 I Ground
SI 5 I Serial Input. All data is input to the device on this pin. The pin is sampled
on the rising edge of SCK and is ignored at other times. It should always
be driven to a valid logic level to meet ICC specifications.
* SI may be connected to SO for a single pin data interface.
SCK 6 I Serial Clock. All I/O activity is synchronized to the serial clock. Inputs
are latched on the rising edge and outputs occur on the falling edge. The
part is static so the clock frequency may be any value between 0 and 2.1
MHz and may be interrupted at any time.
/HOLD 7 I Hold. The /HOLD signal is used when the host CPU must interrupt a
memory operation for another task. Taking the /HOLD signal to a low
state pauses the current operation. The part ignores any transition on SCK
or /CS. All transitions on /HOLD must occur while SCK is low.
VCC 8 I Supply Voltage. 5V
Overview
The FM25160 is a serial FRAM memory. The
memory array is logically organized as 2,048 x 8 and
is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the FRAM is similar to serial EEPROMs. The
major difference between the FM25160 and a serial
EEPROM with the same pin-out relates to its superior
write performance.
Memory Architecture
When accessing the FM25160, the user addresses
2,048 locations each with 8 data bits. These data bits
are shifted serially. The addresses are accessed using
the SPI protocol, which includes a chip select (to
permit multiple devices on the bus), an op-code
including a page address, and a word address. The
word address consists of 8-bits that specify one of
256 addresses. The page address is 3-bits and so there
are 8 pages each of 256 locations. The complete
address of 11-bits specifies each byte address
uniquely.
12 May 2000 3/14
Most functions of the FM25160 are either controlled
by the SPI interface or are handled automatically by
on-board circuitry. The access time for memory
operation essentially is zero, beyond the time needed
for the serial protocol. That is, the memory is read or
written at the speed of the SPI bus. Unlike an
EEPROM, it is not necessary to poll the device for a
ready condition since writes occur at bus speed. That
is, by the time a new bus transaction can be shifted
into the part, a write operation will be complete. This
is explained in more detail in the interface section
below.
Users expect several obvious system benefits from
the FM25160 due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example in
a high noise environment, the fast-write operation is
less susceptible to corruption than an EEPROM since
it is completed quickly. By contrast an EEPROM
requiring milliseconds to write is vulnerable to noise
during much of the cycle.
Note that the FM25160 contains no power
management circuits other than a simple internal
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Ramtron FM25160
power-on reset. It is the user’s responsibility to ensure
that VCC is within data sheet tolerances to prevent
incorrect operation.
Serial Peripheral Interface – SPI Bus
The FM25160 employs a Serial Peripheral Interface
(SPI) bus. This high-speed serial bus is provides high
performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface. It
is quite simple to emulate the port using ordinary port
pins for microcontrollers that do not. Note that the
FM25160 operates in SPI Mode 0 only.
The SPI interface uses a total of four pins, clock,
data-in, data-out, and chip select. It is possible to
connect the two data lines together. Figure 2
illustrates a typical system configuration using the
FM25160 with a microcontroller that offers an SPI
port. Figure 3 shows a similar configuration for a
microcontroller that has no hardware support for the
SPI bus.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data lines. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25160 will begin monitoring
the clock and data lines. The relationship between the
falling edge of \CS, the clock and data is dictated by
the SPI mode. There are four such modes however
the FM25160 supports only mode 0. This mode
dictates that the SCK signal must be low when \CS is
activated.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the part. After \CS
is activated, the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred.
Certain op-codes are commands with no subsequent
data transfer. The /CS must go inactive after an
operation is complete and before a new op-code can
be issued.
Figure 2. System Configuration with SPI port
Figure 3. System Configuration without SPI port
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Ramtron FM25160
Data Transfer
All data transfers to and from the FM25160 occur in
8-bit groups. They are synchronized to the clock
signal (SCK) and occur most significant bit (MSB)
first. Serial inputs are clocked in on the rising edge
of SCK. Outputs are driven on the falling edge of
SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25160. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, are commands
that have no subsequent operations. They perform a
single function such as to enable a write operation.
Second are commands followed by one byte, either in
or out. They operate on the status register Last are
commands for memory transactions followed by
address and one or more bytes of data.
Table 1. Op-code Commands
Name Description Op-code value
WREN Set Write Enable Latch
WRDI Write Disable
RDSR Read Status Register
WRSR Write Status Register
READ Read Memory Data
WRITE Write Memory Data
Figure 4. WREN Bus Configuration
00000110
00000100
00000101
00000001
00AAA011
00AAA010
WREN - Set Write Enable Latch
The FM25160 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the status register
and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no affect. Completing any write
operation will automatically clear the write enable
latch and prevent further writes without another
WREN command. Figure 4 below illustrates the
WREN command bus configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
5 below illustrates the WRDI command bus
configuration.
Figure 5. WRDI Bus Configuration
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Ramtron FM25160
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR opcode, the FM25160 will return one bye with the
contents of the Status register. The Status register is
described in detail in a later section.
Figure 6. RDSR Bus Configuration
Figure 7. WRSR Bus Configuration
WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive.
Note that on the FM25160, /WP only prevents
writing to the Status register, not the memory array.
Also prior to sending the WRSR command, the user
must send a WREN command to enable writes. Note
that executing a WRSR command is a write
operation and therefore clears the Write Enable
Latch. The bus configuration of RDSR and WRSR
are shown below.
unnecessary as the FRAM writes in real-time and is
Status Register & Write Protection
The write protection features of the FM25160 are
multi-tiered. First, a WREN op-code must be issued
prior to any write operation. Assuming that writes are
enabled using WREN, writes to memory are
controlled by the Status register. As described above,
writes to the status register are performed using the
WRSR command and subject to the /WP pin. The
Status register is organized as follows.
never busy. The WPEN, BP1 and BP0 control write
protection features. They are nonvolatile! The WEL
flag indicates the state of the Write Enable Latch.
Writing the WEL bit in the status register has no
affect.
BP1 and BP0 are memory block write protection
bits. They specify portions of memory that are write
protected as shown in the following table.
Table 2. Status Register
Bit 7 6 5 4 3 2 1 0
Name WPEN 0 0 0 BP1 BP0 WEL 0
Bits 0 and 4-6 are fixed at 0 and can not be modified.
Note that the Ready bit in many EEPROMs is
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Ramtron FM25160
Table 3. Block Memory Write Protection
BP1 BP0 Protected Address Range
0 0 None
0 1 600h to 7FFh (upper ¼)
1 0 400h to 7FFH (upper ½)
1 1 000h to 7FFh (all)
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
The WPEN bit controls the affect of the hardware
/WP pin. When WPEN is low, the /WP pin is
ignored. When WPEN is high, the /WP pin controls
Table 4. Write Protection
WEL WPEN /WP Protected Blocks Unprotected Blocks Status Register
0 X X Protected Protected Protected
1 0 0 Protected Unprotected Unprotected
1 0 1 Protected Unprotected Unprotected
1 1 0 Protected Unprotected Protected
1 1 1 Protected Unprotected Unprotected
write access to the status register. Thus the Status
register is write protected if WPEN=1 and /WP=0.
This scheme provides a write protection mechanism,
which can prevent software from writing the
memory under any circumstances. This occurs if the
BP1 and BP0 are set to 1, then the WPEN bit is set
to 1 and /WP is set to 0. This occurs because the
block protect bits prevent writing memory and the
/WP signal in hardware prevents altering the block
protect bits (if WPEN is high). Therefore in this
condition, hardware must be involved in allowing a
write operation. The following table summarizes the
write protection conditions.
Memory Operation
The SPI interface, with its relatively high maximum
clock frequency, highlights the fast write capability of
the FRAM technology. Unlike SPI bus EEPROMs
the FM25160 can perform sequential writes at bus
speed. No page register is needed and any number of
sequential writes may be performed.
Write Operation
All writes to the memory array begin with a WREN
op-code. The bus master then issues a WRITE opcode. Part of this op-code includes the upper 3-bits of
the memory address. Bits 5, 4, and 3 in the op-code
correspond to A10, A9, A8 respectively. The next
byte is the lower 8-bits of the address. In total, the 11bits specify the address of the first byte of the write
operation. Subsequent bytes are data and they are
written sequentially. Addresses are incremented
internally as long as the bus master continues to issue
clocks. If the last address of 7FFh is reached, the
counter will roll over to 000h. Data is written MSB
first.
Unlike EEPROMs, any number of bytes can be
written sequentially and each byte is written to
memory immediately after it is clocked in (after the
8th clock). The rising edge of /CS terminates a
WRITE op-code operation.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Part of this op-code includes the
upper 3-bits of the memory address. The next byte is
the lower 8-bits of the address. In total, the 11-bits
specify the address of the first byte of the read
operation. After the op-code is complete, the SI line
is ignored. The bus master then issues 8 clocks, with
one bit read out for each. Addresses are incremented
internally as long as the bus master continues to issue
clocks. If the last address of 7FFh is reached, the
counter will roll over to 000h. Data is read MSB first.
The rising edge of /CS terminates a READ op-code
operation.. The bus configuration for read and write
operations is shown below.
Hold
The /HOLD pin can be used to interrupt a serial
operation without aborting it. If the bus master takes
the /HOLD pin low while SCK is low, the current
operation will pause. Taking the /HOLD pin high
while SCK is low will resume an operation. The
transitions of /HOLD must occur while SCK is low,
but the SCK pin can toggle during a hold state.
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Ramtron FM25160
Figure 8 Memory Write
Figure 9 Memory Read
Data Retention and Endurance
Data retention is specified in the electrical
specifications below. For purposes of clarity, this
section contrasts the retention and endurance of
FRAM with EEPROM. The retention performance of
FRAM is very comparable to EEPROM in its
characteristics. However, the effect of endurance
cycles on retention is different.
A typical EEPROM has a write endurance
specification that is fixed. Surpassing the specified
level of cycles on an EEPROM usually leads to a
hard memory failure. By contrast, the effect of
increasing cycles on FRAM produces an increase in
the soft error rate. That is, there is a higher likelihood
of data loss but the memory continues to function
properly. A hard failure would not occur by simply
exceeding the endurance specification; simply a
reduction in data retention reliability. While enough
cycles would cause an apparent hard error, this is
simply a very high soft error rate. This characteristic
makes it problematic to assign a fixed endurance
specification.
Endurance is a soft specification. Therefore, the user
may operate the device with different levels of
endurance cycling for different portions of the
memory. For example, critical data needing the
highest reliability level could be stored in memory
locations that receive comparatively few cycles. Data
with shorter-term use could be located in an area
receiving many more cycles. A scratchpad area,
needing little if any retention can be cycled until there
is virtually no retention capability remaining. This
would occur several orders of magnitude above the
endurance spec.
Internally, a FRAM operates with a read and restore
mechanism similar to a DRAM. Therefore, endurance
cycles are applied for each access: read or write. The
FRAM architecture is based on an array of rows and
columns. Each access causes a cycle for an entire
row. Therefore, data locations targeted for
substantially differing numbers of cycles should not
be located within the same row. In the FM25160,
there are 256 rows each 64 bits wide. Each 8 bytes in
the address mark the beginning of a new row.
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Ramtron FM25160
Applications
The versatility of FRAM technology fits into many
diverse applications. Clearly the strength of higher
write endurance and faster writes make FRAM
superior to EEPROM in all but one-time
programmable applications. The advantage is most
obvious in data collection environments where writes
are frequent and data must be nonvolatile.
The attributes of fast writes and high write endurance
combine in many innovative ways. A short list of
ideas is provided here.
1. Data collection. In applications where data is
collected and saved, FRAM provides a superior
alternative to other solutions. It is more cost effective
than battery backup for SRAM and provides better
write attributes than EEPROM.
2. Configuration. Any nonvolatile memory can
retain a configuration. However if the configuration
changes and power failure is a possibility, the higher
write endurance of FRAM allows changes to be
recorded without restriction. Any time the system
state is altered, the change can be written. This avoids
writing to memory on power down when the available
time is short and power scarce.
3. High noise environments. Writing to EEPROM
in a noisy environment can be challenging. When
severe noise or power fluctuations are present, the
long write time of EEPROM creates a window of
vulnerability during which the write can be corrupted.
The fast write of FRAM is complete within a
microsecond. This time is typically too short for noise
or power fluctuation to disturb it.
4. Time to market. In a complex system, multiple
software routines may need to access the nonvolatile
memory. In this environment the time delay
associated with programming EEPROM adds undue
complexity to the software development. Each
software routine must wait for complete programming
before allowing access to the next routine. When time
to market is critical, FRAM can eliminate this simple
obstacle. As soon as a write is issued to the
FM25160, it is effectively done -- no waiting.
5. RF/ID. In the area of contactless memory, FRAM
provides an ideal solution. Since RF/ID memory is
powered by an RF field, the long programming time
and high current consumption needed to write
EEPROM is unattractive. FRAM provides a superior
solution. The FM25160 is suitable for multi-chip
RF/ID products.
6. Maintenance tracking. In sophisticated systems,
the operating history and system state during a failure
is important knowledge. Maintenance can be
expedited when this information has been recorded.
Due to the high write endurance, FRAM makes an
ideal system log. In addition, the convenient 2-wire
interface of the FM25160 allows memory to be
distributed throughout the system using minimal
additional resources.
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Ramtron FM25160
Electrical Specifications
Absolute Maximum Ratings
Description Ratings
Ambient storage or operating temperature
Voltage on any pin with respect to ground -1.0V to +7.0V
D.C. output current on any pin 5 mA
Lead temperature (Soldering, 10 seconds)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only, and the functional operation of the device at these or any other conditions above those listed in the
operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability
DC Operating Conditions TA = -40° C to + 85° C, VCC = 4.5V to 5.5V unless otherwise specified
Symbol Parameter Min Typ Max Units Notes
VCC Main Power Supply 4.5 5.0 5.5 V 1
ICC VCC Supply Current
@ SCK = 1.0 MHz
ICC VCC Supply Current
@ SCK = 2.1 MHz
ISB Standby Current 1 10
ILI Input Leakage Current 10
ILO Output Leakage Current 10
VIL Input Low Voltage -0.3 VCC x 0.3 V 1
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V 1
VOL Output Low Voltage
@ IOL = 2 mA
VOH Output High Voltage
@ IOH = -1 mA
VHYS Input Hysteresis VCC x .05 V 1, 5
Notes
1. Referenced to VSS.
2. SCK toggling between VCC-0.3V and VSS, other inputs VSS or VCC-0.3V
3. SCK = SI = /CS=VCC. All inputs VSS or VCC.
4. VIN or VOUT = VSS to VCC
5. This parameter is periodically sampled and not 100% tested.
-40°C to + 85°C
300° C
0.9 1.2 mA 2
1.6 2.5 mA 2
µA
µA
µA
0.4 V 1
VCC-0.8 V 1
3
4
4
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Ramtron FM25160
AC Parameters TA = -40° C to + 85° C, VCC = 4.5V to 5.5V unless otherwise specified
Symbol Parameter
Min Max
Units
fCK SCK Clock Frequency 0 2.1 MHz
tCH Clock High Time 200 ns
tCL Clock Low Time 200 ns
tCSU Chip Select Setup 240 ns
tCSH Chip Select Hold 240 ns
tOD Output Disable 240 ns
tODV Output Data Valid 200 ns
tOH Output Hold 0 ns
tD Deselect Time 240 ns
tR Data Rise Time 2.0
tF Data Fall Time 2.0
µS
µS
tH Data Hold Time 100 ns
tSU Data Setup Time 100 ns
tHS /Hold Setup Time 90 ns
tHH /Hold Hold Time 90 ns
tHZ /Hold Low to Hi-Z 100 ns
tLZ /Hold High to Data Active 100 ns
Notes
1. Rise and fall times measured between 10% and 90% of waveform.
Capacitance TA = 25° C , f=1.0 MHz, VCC = 5V
Symbol Parameter Max Units Notes
CO Output capacitance (SDA) 8 pF 1
CI Input capacitance 6 pF 1
Notes
1. This parameter is periodically sampled and not 100% tested.
AC Test Conditions
Input Pulse Levels VCC * 0.1 to VCC * 0.9
Input rise and fall times 10 ns
Input and output timing levels VCC*0.5
Equivalent AC Load Circuit
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Ramtron FM25160
Serial Data Bus Timing
/Hold Timing
Data Retention TA = -40° C to + 85° C, VCC = 4.5V to 5.5V unless otherwise specified
Parameter Min Units Notes
Data Retention 10 Years 1
Notes
1. Data retention is specified at 85° C. The relationship between retention, temperature, and the associated
reliability level is characterized separately.
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Ramtron FM25160
α
8-pin SOP JEDEC MS-012
Index
Area
E H
Pin 1
D
A
B
e
Selected Dimensions
Refer to JEDEC MS-012 for complete dimensions and
notes.
Controlling dimensions is in millimeters. Conversions to
inches are not exact.
Symbol Dim Min Nom. Max
A mm
in.
A1 mm
in.
B mm
in.
C mm
in.
D mm
in.
E mm
in.
e mm
in.
H mm
in.
h mm
in.
L mm
in.
α
A1
1.35
.053
.10
.004
.33
.013
.19
.007
4.80
.189
3.80
.150
1.27 BSC
5.80
.228
.25
.010
.40
.016
0°
1.75
.25
.51
.25
5.00
4.00
.050 BSC
6.20
.50
1.27
.10 mm
.004 in.
.069
.010
.020
.010
.197
.157
.244
.197
.050
8°
h
45
L
C
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Ramtron FM25160
8-pin DIP JEDEC MS-001
Index
E1
Area
D
A2
A
A1
e
b
D1
Selected Dimensions
12 May 2000 14/14
Refer to JEDEC MS-001 for complete dimensions and notes.
Controlling dimensions is in inches. Conversions to millimeters are
not exact.
Symbol Dim Min Nom. Max
A in.
mm
A1 in.
mm
A2 in.
mm
b in.
mm
D in.
mm
D1 in.
mm
E in.
mm
E1 in.
mm
e in.
mm
eA in.
mm
eB in.
mm
L in.
mm
.210
0.015
.381
0.115
2.92
0.014
.356
0.355
9.02
0.005
.127
0.300
7.62
0.240
6.10
.100 BSC
.300 BSC
0.430
0.115
2.92
0.130
3.30
0.018
.457
0.365
9.27
0.310
7.87
0.250
6.35
2.54 BSC
7.62 BSC
0.130
3.30
5.33
0.195
4.95
0.022
.508
0.400
10.2
0.325
8.26
0.280
7.11
10.92
0.150
3.81
E
eA
eB
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