Datasheet FM24C256-SE Datasheet (RAMTRON)

Preliminary Data Sheet

FM24C256

256Kb FRAM Serial Memory

Features

256Kbit Ferroelectric Nonvolatile RAM

• Organized as 32,768 x 8 bits

• High Endurance 100 Billion (10

• 10 year Data Retention

• NoDelay™ Writes

• Advanced High-Reliability Ferroelectric Process

Fast Two-wire Serial Interface

• Up to 1 MHz M aximum Bus Frequency

• Supports Legacy Timing for 100 kHz & 400 kHz

Description

The FM24C256 is a 256-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.

The FM24C256 performs write operations at bus
speed. No write delays are incurred. The next bus
cycle may commence immediately without the need
for data polling. In addition, the product offers
virtually unlimited write endurance, orders of
magnitude more endurance than EEPROM. Also,
FRAM exhibits much lower power during writes than
EEPROM since write operations do not require an
internally elevated power supply voltage for write
circuits.

These capabilities make the FM24C256 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with less overhead for the system.

The FM24C256 is provided in a 8-pin EIAJ SOP
package using a familiar two-wire protocol. It is
guaranteed over an industrial temperature range of

-40°C to +85°C.

11

) Read/Writes

Low Power Operation

• True 5V Operation

• 200 µA Active Current (100 kHz)

• 100 µA Standby Current

Industry Standard Configurat ion

• Industrial Temperature -40° C to +85° C

• 8-pin EIAJ SOP

Pin Configuration

A0
A1
A2

VSS

1
2
3
4

Pin Names Function

A0-A2 Device Select Address
SDA Serial Data/Address
SCL Serial Clock
WP Write Protect
VSS Ground
VDD Supply Voltage 5V

8
7
6
5

VDD
WP
SCL
SDA

Ordering Information

FM24C256-SE 8-pin SOP EIAJ

This is a product in sampling or pre-produ ction phase of develop-
ment. Characteristic data and other specifications are subject to 1850 Ramtron Drive, Colorado Springs, CO 80921
change without notice. (800) 545-FRAM, [phone], Fax [phone]

Ramtron International Corporation

www.ramtron.com

Rev 1.1
Sept 2001 Page 1of 13

FM24C256

A0-A2

SDA

SCL

WP

Counter

Address

Latch

4,096 x 64

FRAM Array

8

`

Serial to Parallel

Converter

Data Latch

Control Logic

Figure 1. Block Diagram

Pin Description

Pin Name Type Pin Description

A0-A2 Input Address 0-2. These pins are used to select one of up to 8 devices of the same type on

the same two-wire bus. To select the device, the address value on the three pins must
match the corresponding bits contained in the device address. The address pins are
pulled down internally.

WP Input Write Protect. When tied to VDD, the entire array will be write-protected. When WP is

connected to ground, all addresses may be written. This pin is pulled down internally.

SDA I/O Serial Data Address. This is a bi-directional line for the two-wire interface. It is open-

drain and is intended to be wire-ORed with other devices on the two-wire bus. The
input buffer incorporates a schmitt trigger for noise immunity and the output driver
includes slope control for falling edges. A pull-up resistor is required.

SCL Input Serial Clock. The serial clock line for the two-wire interface. Data is clocked out of the

part on the falling edge, and in on the rising edge. The SCL input also incorporates a

schmit trigger input for noise immunity.
VDD Supply Supply Voltage. 5V
VSS Supply Ground

Rev 1.1
Sept 2001 Page 2 of 13

FM24C256

Overview

The FM24C256 is a serial FRAM memory. The
memory array is logically organized as 32,768 x 8 bit
memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the FRAM is similar to serial EEPROMs. The major
difference between the FM24C256 and a serial
EEPROM relates to its superior write performance.

Two-wire Interface

The FM24C256 employs a bi-directional two-wire
bus protocol using few. Figure 2 illustrates a typical
system configuration using the FM24C256 in a
microcontroller-based system. The industry standard
two-wire bus is familiar to many users but is
described in this section.

By convention, any device that is se nding data onto

Memory Architecture

When accessing the FM24C256, the user addresses
32,768 locations each with 8 data bits. These data bits
are shifted serially. The 32,768 addresses are
accessed using the two-wire protocol, which includes
a slave address (to distinguish other non-memory
devices), and an extended 16-bit address. Only the
lower 15 bits are used by the decoder for accessing
the memory. The upper address bit should be set to 0
for compatibility with larger devices in the future.

The memory is read or written at the speed of the
two-wire bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. That is, by the time a

the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24C256 always is a slave device.

The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including Start, Stop, Data bit, and Acknowledge.
Figure 3 illustrates the signal conditions that specify
the four states. Detailed timing diagrams are shown
in the electrical specifications.

VDD

new bus transaction can be shifted into the part, a
write operation is complete. This is explained in more
detail in the interface section below.

Microcontroller

Rmin = 1.8 K

Rmax = tR/Cbus

Ω

Users expect several obvious system benefits from
the FM24C256 due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM

SDA SCL

FM24C256

A0 A1 A2

SDA SCL

FM24C64

A0 A1 A2

since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.

Note that the FM24C256 contains no power
management circuits other than a simple internal

Figure 2. Typical System Configuration

power-on reset. It is the user’s responsibility to
ensure that V

is maintained within data sheet

DD

tolerances to prevent incorrect operation.

Rev 1.1
Sept 2001 Page 3 of 13

FM24C256

7

Stop

(Master)

Start

(Master)

Data bits

(Transmitter)

Figure 3. Data Transfer Protocol

Stop Condition

A Stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24C256 must end
with a Stop condition. If an operation is pending
when a Stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a Stop condition.

Start Condition

A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
ready the FM24C256 for a new operation.

If during operation the power supply drops below the
specified VDD minimum, the system should issue a
Start condition prior to performing another operation.

Data/Address Transfer

All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.

Acknowledge

The Acknowledge takes place after the 8

th

data bit
has been transferred in any transaction. During this
state the transmitter should release the SDA bus to
allow the receiver to drive it. The receiver drives the
SDA signal low to acknowledge receipt of the byte.
If the receiver does not drive SDA low, the condition
is a No-Acknowledge and the operation is aborted.

The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the No-Acknowledge ends the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.

6

0

Data bit

(Transmitter)

Acknowledge

(Receiver)

Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24C256
will continue to place data onto the bus as long as
the receiver sends Acknowledges (and clocks).
When a read operation is complete and no more data
is needed, the receiver must not acknowledge the
last byte. If the receiver acknowledges the last byte,
this will cause the FM24C256 to attempt to drive
the bus on the next clock while the master is sending
a new command such as Stop.

Slave Address

The first byte that the FM24C256 expects after a
Start condition is the slave address. As shown in
Figure 4, the slave address contains the Slave ID
(device type), the device select address bits, and a
bit that specifies if the transaction is a read or a
write.

Bits 7-4 are the device type and should be set to
1010b for the FM24C256. These bits allow other
types of function types to reside on the 2-wire bus
within an identical address range. Bits 3-1 are the
address select bits. They must match the
corresponding value on the external address pins to
select the device. Up to eight FM24C256 devices
can reside on the same two-wire bus by assigning a
different address to each. Bit 0 is the read/write bit.
A 0 indicates a write operation.

Slave

ID

1010A2A1A0R/W

7654321 0

Device

Select

Figure 4. Slave Address

Rev 1.1
Sept 2001 Page 4 of 13

FM24C256

Addressing Overview

After the FM24C256 (as receiver) acknowledges the
device address, the master can place the memory
address on the bus for a write operation. The address
requires two bytes. The first is the MSB (upper byte).
Since the device uses only 15 address bits, the value
of the upper bits is a “don’t care”. Following the
MSB is the LSB (lower byte) with the remaining
eight address bits. The address value is latched
internally. Each access causes the latched address
value to be incremented automatically. The current
address is the value that is held in the latch, either a
newly written value or the address following the last
access. The current address will be held as long as
power remains or until a new value is written. Reads
always use the current address. A random read
address can be loaded by beginning a write operation
as explained below.

After transmission of each data byte, just prior to the
acknowledge, the FM24C256 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing externally.
After the last address (7FFFh) is reached, the address
latch will roll over to 0000h. There is no limit to the
number of bytes that can be accessed with a single
read or write operation.

Data Transfer

After the address information has been transmitted,
data transfer between the bus master and the
FM24C256 can begin. For a read operation the
FM24C256 will place 8 data bits on the bus then wait
for an Acknowledge from the master. If the
Acknowledge occurs, the FM24C256 will transfer the
next sequential byte. If the Acknowledge is not sent,
the FM24C256 will end the read operation. For a
write operation, the FM24C256 will accept 8 data
bits from the master then send an acknowledge. All
data transfer occurs MSB (most significant bit) first.

Memory Operation

The FM24C256 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24C256 and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained

Write Operation

All writes begin with a device address, then a
memory address. The bus master indicates a write
operation by setting the LSB of the device address
to a 0. After addressing, the bus master sends each
byte of data to the memory and the memory
generates an acknowledge condition. Any number of
sequential bytes may be written. If the end of the
address range is reached internally, the address
counter will wrap from 7FFFh to 0000h.

Unlike other nonvolatile memory technologies,
there is essentially no write delay with FRAM.
Since the read and write access times of the
underlying memory are the same, the user
experiences no delay on the bus. The entire memory
cycle occurs in less time than a single bus clock.
Therefore, any operation including read or write can
occur immediately following a write. Acknowledge
polling, a technique used with EEPROMs to
determine if a write has completed is unnecessary
and will always return a ready condition.

Internally, an actual memory write occurs after the

th

8

data bit is transferred. It will be complete before
the Acknowledge is sent. Therefore, if the user
desires to abort a write without altering the memory
contents, this should be done using Start or Stop
condition prior to the 8

th

data bit. The FM24C256

uses no page buffering.

The memory array can be write protected using the
WP pin. Pulling the WP pin high will write-protect
all addresses. The FM24C256 will not acknowledge
data bytes that are written when WP is active. In
addition, the address counter will not increment if
writes are attempted to these addresses. Setting WP
low will deactivate this feature. WP is internally
pulled down. The state of WP should remain stable
from the Start command until the address is
complete.

Figure 5 and 6 below illustrate both a single-byte
and multiple-write.

below.

Rev 1.1
Sept 2001 Page 5 of 13

FM24C256

By Master

Start Address & Data

Stop

S ASlave Address 0 Address MSB A Data Byte A P

By FM24C256

X

Figure 5. Single Byte Write

Start

By Master

S ASlave Address 0 Address MSB A Data Byte A P

By FM24C256

Address & Data

X

Acknowledge

Figure 6. Multiple Byte Write

Read Operation

There are two types of read operations. They are
current address read and selective address read. In a
current address read, the FM24C256 uses the internal
address latch to supply the address. In a selective
read, the user performs a procedure to set the address
to a specific value.

Current Address & Sequential Read
As mentioned above the FM24C256 uses an internal

latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.

To perform a current address read, the bus master
supplies a device address with the lsb set to 1. T his
indicates that a read operation is requested. After
receiving the complete device address, the
FM24C256 will begin shifting out data from the
current address on the next clock. The current address
is the value held in the internal address latch.

Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte, the internal address
counter will be incremented.

Each time the bus master acknowledges a byte, this
indicates that the FM24C256 should read out the next
sequential byte.

There are four ways to properly terminate a read
operation. Failing to properly terminate the read will

Address LSB A

Acknowledge

Address LSB A

Data Byte A

most likely create a bus contention as the FM24C256
attempts to read out additional data onto the bus. The
four valid methods are as follows.

1. The bus master issues a no-acknowledge in the

th

9

clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
preferred.

2. The bus master issues a no-acknowledge in the

th

9

clock cycle and a start in the 10th.

3. The bus master issues a stop in the 9
cycle.

4. The bus master issues a start in the 9
cycle.

If the internal address reaches 7FFFh, it will wrap
around to 0000h on the next read cycle. Figures 7 and
8 show the proper operation for current address reads.

Selective (Random) Read
There is a simple technique that allows a user to

select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.

To perform a selective read, the bus master sends out
the device address with the lsb set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
loaded into the internal address latch. After the
FM24C256 acknowledges the address, the bus master
issues a Start condition. This simultaneously aborts
the write operation and allows the read command to
be issued with the device address LSB set to a 1. The
operation is now a current address read.

Stop

th

clock

th

clock

Rev 1.1
Sept 2001 Page 6 of 13

FM24C256

No

Acknowledge

Stop

By Master

Start Address

S ASlave Address 1 Data Byte 1 P

By Master

By FM24C256

Start

By Master

By FM24C256

By FM24C256

Figure 7. Current Address Read

Start Address

S ASlave Address 1 Data Byte 1 P

Acknowledge

Figure 8. Sequential Read

Address

S ASlave Address 0 Address MSB A

Figure 9. Selective (Random) Read

Acknowledge

Address LSB A

Acknowledge

Data

No

Acknowledge

Acknowledge

Data ByteA

Data

Start Address

S ASlave Address 1 Data Byte 1 P

Data

No

Acknowledge

Stop

Stop

Rev 1.1
Sept 2001 Page 7 of 13

FM24C256

Endurance

A FRAM internally operates with a read and restore
mechanism similar to a DRAM. Therefore,
endurance cycles are applied for each access: read or
write. The FRAM architecture is based on an array of
rows and columns. Each access causes a cycle for an
entire row. In the FM24C256, a row is 64 bits wide.
Every 8 bytes in the address marks the beginning of a
new row. Endurance can be optimized by ensuring
frequently accessed data are loacted in different rows.
Regardless, FRAM read and write endurance is
effectively unlimited at the 1MHz two-wire speed.
The rated endurance limit of 10

11

cycles will allow
300 accesses per second to the same row for over 10
years.

Applications

The versatility of FRAM technology fits into many
diverse applications. Clearly the strength of higher
write endurance and faster writes make FRAM
superior to EEPROM in all but one-time
programmable applications. The advantage is most
obvious in data collection environments where writes
are frequent and data must be nonvolatile.

The attributes of fast writes and high write endurance
combine in many innovative ways. A short list of
ideas is provided here.

1. Data collection
collected and saved, FRAM provides a superior
alternative to other solutions. It is more cost effective
than battery backup for SRAM and provides better
write attributes than EEPROM.

2. Configuration
retain a configuration. However, if the configuration
changes and power failure is a possibility, the higher
write endurance of FRAM allows changes to be
recorded without restriction. Any time the system

. In applications where data is

. Any nonvolatile memory can

state is altered, the change can be written. This avoids
writing to memory on power down when the
available time is short and power scarce.

3. High noise environments

. Writing to EEPROM
in a noisy environment can be challenging. When
severe noise or power fluctuations are present, the
long write time of EEPROM creates a window of
vulnerability during which the write can be
corrupted. The fast write of FRAM is complete
within a microsecond. This time is typically fast
enough to avoid noise or power supply disturbances.

4. Time to market

. In a complex system, multiple
software routines may need to access the nonvolatile
memory. In this environment the time delay
associated with programming EEPROM adds undue
complexity to the software development. Each
software routine must wait for complete
programming before allowing access to the next
routine. When time to market is critical, FRAM can
eliminate this obstacle. As soon as a write is issued to
the FM24C256, it is effectively done -- no waiting.

5. RF/ID

. In the area of contactless memory,
FRAM provides an ideal solution. Since RF/ID
memory is powered by an RF field, the long
programming time and high current consumption
needed to write EEPROM is unattractive. FRAM
provides a superior solution. The FM24C256 is
suitable for multi-chip RF/ID products.

6. Maintenance tracking

. In sophisticated systems,
the operating history and system state must be
captured prior to a failure. Maintenance can be
expedited when this information has been recorded
frequently. Due to the high write endurance, FRAM
makes an ideal system log. In addition, the
convenient 2-wire interface of the FM24C256 allows
memory to be distributed throughout the system
using minimal additional resources.

Rev 1.1
Sept 2001 Page 8 of 13

FM24C256

Electrical Specifications

Absolute Maximum Ratings

Symbol Description Ratings

VDD Voltage on VDD with respect to VSS -1.0V to +7.0V

VIN Voltage on any signal pin with respect to VSS -1.0V to +7.0V

and V

T

Storage Temperature

STG

T

Lead temperature (Soldering, 10 seconds)

LEAD

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only, and the functional operation of the device at these or any other conditions above
those listed in the operational section of this specification is not implied. Exposure to absolute maximum
ratings conditions for extended periods may affect device reliability

DC Operating Conditions

(TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified)

Symbol Parameter Min Typ Max Units Notes

VDD Main Power Supply 4.5 5.0 5.5 V
IDD VDD Supply Current

@ SCL = 100 kHz
@ SCL = 400 kHz

@ SCL = 1 MHz
ISB Standby Current 100
ILI Input Leakage Current 10
ILO Output Leakage Current 10
VIH Input High Voltage 0.7 VDD V

VIL Input Low Voltage -0.3 0.3 VDD V 4
VOL Output Low Voltage

@ I

= 3 mA

OL

RIN Address Input Resistance (WP, A2-A0)

For V

For V
V

Input Hysteresis 0.05 VDD V 4

HYS

= VIL

IN

= VIH

IN

(max)

(min)

0.4 V

20

1

Notes

1.

SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V

2.

SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.

3.

VIN or V

4.

This parameter is characterized but no t tested.

5.

The input pull-down circuit is strong (20KΩ) when the input voltage is below VIL and weak (1MΩ) when the input voltage
is above V

= VSS to VDD. Does not apply to pins with internal pull down resistors.

OUT

. This resistance is characterized and not tested.

IH

< VDD+1.0V

IN

-40°C to + 85°C
300° C

200
500

1.2

+ 0.5 V 4

DD

µA
µA

mA

µA
µA
µA

KΩ

MΩ

1

2
3
3

5

Rev 1.1
Sept 2001 Page 9 of 13

FM24C256

AC Parameters

(TA = -40° C to + 85° C, VDD = 4.5V to 5.5V, CL = 100 pF unless otherwise specified)

Symbol Parameter Min Max Min Max Min Max Units Notes

f

SCL Clock Frequency 0 100 0 400 0 1000 kHz

SCL

t

Clock Low Period 4.7 1.3 0.6

LOW

t

Clock High Period 4.0 0.6 0.4

HIGH

tAA SCL Low to SDA Data Out Valid 3 0.9 0.55
t

Bus Free Before New

BUF

4.7 1.3 0.5

µs
µs
µs

µs

Transmission

t

Start Condition Hold Time 4.0 0.6 0.25

HD:STA

t

Start Condition Setup for Repeated

SU:STA

4.7 0.6 0.25

µs
µs

Start

t

Data In Hold 0 0 0 ns

HD:DAT

t

Data In Setup 250 100 100 ns

SU:DAT

tR Input Rise Time 1000 300 300 ns 1
tF Input Fall Time 300 300 100 ns 1
t

Stop Condition Setup 4.0 0.6 0.25

SU:STO

tDH Data Output Hold

0 0 0 ns

µs

(from SCL @ VIL)

tSP Noise Suppression Time Constant

50 50 50 ns

on SCL, SDA

Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations.

1 This parameter is periodically sampled and not 100% tested.

Data Retention

(VDD = 4.5V to 5.5V unless otherwise specified)

Parameter Min Units Notes

Data Retention 10 Years 1

Notes

1.

The relationship between retention, temperature, and the associated reliability level is
characterized separately.

Capacitance

(TA = 25° C, f=1.0 MHz, VDD = 5V)

Symbol Parameter Max Units Notes

C

Input/output capacitance (SDA) 8 pF 1

I/O

CIN Input capacitance 6 pF 1

Notes

1 This parameter is periodically sampled and not 100% tested.

AC Test Conditions Equivalent AC Load Circuit

Input Pulse Levels 0.1 V

to 0.9 VDD

DD

5.5V

Input rise and fall times 10 ns
Input and output timing levels 0.5 V

DD

Ω

1700

Output

100 pF

Rev 1.1
Sept 2001 Page 10 of 13

FM24C256

Diagram Notes

All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read
and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional
relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only.

Read Bus Timing

t

t

R

HIGH

t

F

`

t

LOW

t

SP

t

SP

SCL

t

AA

1/fSCL

t

HD:DAT

t

SU:D AT

t

DH

Acknowledge

SDA

t

SU:SDA

Start

t

BUF

Stop Start

Write Bus Timing

t

HD:DAT

SCL

t

SU:STO

t

HD:STA

t

SU:DAT

t

AA

SDA

Start

Stop Start Acknowledge

Rev 1.1
Sept 2001 Page 11 of 13

FM24C256

8-pin EIAJ SOP

Index

Area

E H

Pin 1

D

A

h

°

45

α

L

C

.10 mm
.004 in.

0.080

0.013

0.020

0.010

0.212

0.213

0.330

0.035

8°

B

e

Controlling dimensions in millimeters.
Conversions to inches are not necessarily exact.

Symbol Dim Min Nom. Max

A mm

in.

A1 mm

in.

B mm

in.

C mm

in.

D mm

in.

E mm

in.

e mm

in.

H mm

in.

L mm

in.

α

1.78

0.070

0.102

0.004

0.305

0.012

0.178

0.070

5.16

0.203

5.21

0.205

7.62

0.300

0.508

0.020

0°

A1

2.03

0.330

0.508

0.254

0.538

5.41

1.27 BSC

0.050 BSC

8.38

0.889

Rev 1.1
Sept 2001 Page 12 of 13

FM24C256

Revision History

Revision

Date

Summary

1.0 4/10/01 Initial Release

1.1 9/28/01 Changed Idd and Isb specifications. Changed test load to 1700 ohms to reflect
3mA V

test condition.

OL

Rev 1.1
Sept 2001 Page 13 of 13