Datasheet FM24C256-S Datasheet (RAMTRON)

Preliminary

This data sheet contains design specifications for product development. Ramtron International Corporation
This product is still under development, these specifications may 1850 Ramtron Drive, Colorado Springs, CO 80921
change in any manner without notice (800) 545-FRAM, [phone], Fax [phone]

www.ramtron.com

10 April 2001 1/12

FM24C256

256Kb FRAM Serial Memory

Features

256K bit Ferroelectric Nonvolatile RAM

• Organized as 32,768 x 8 bits

• High endurance 10 Billion (1010) read/writes

• 10 year data retention at 85° C

• NoDelay™ write

• Advanced high-reliability ferroelectric process

Fast Two-wire Serial Interface

• Up to 1 MHz maximum bus frequency

• Supports legacy timing for 100 kHz & 400 kHz

Low Power Operation

• True 5V operation

• 150 µA Active current (100 kHz)

• 10 µA standby current

Industry Standard Configuration

• Industrial temperature -40° C to +85° C

• 20-pin SOP

Description

The FM24C256 is a 256-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile but operates in other res pects as a RAM.
It provides reliable data retention for 10 years while
eliminating the complexities, overhead, and system
level reliability problems caused by EEPROM and
other nonvolatile memories.

The FM24C256 performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array mere hundreds of nanoseconds
after it has been successfully transferred to the
device. The next bus cycle may commence
immediately. In addition, the product offers
substantial write endurance compared with other
nonvolatile memories. The FM24C256 is capable of
supporting up to 1E10-read/write cycles -- far more
than most systems will require from a serial memory.

These capabilities make the FM24C256 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with less overhead for the system.

The FM24C256 is provided in a 20-pin SOP package
using a familiar two-wire protocol. It is guaranteed
over an industrial temperature range of -40°C to
+85°C.

Pin Configuration

NC

NC

NC

A0

WP

VDD

A1

A2

NC

NC

NC

NC

NC

NC
NC
NC

VSS

SDA

SCL

NC

Pin Names Function

A0-A2 Device Select Address
SDA Serial Data/address
SCL Serial Clock
WP Write Protect
VSS Ground
VDD Supply Voltage 5V

Ordering Information

FM24C256-S 20-pin SOP

Ramtron FM24C256

10 April 2001 2/12

Figure 1. Block Diagram

Address

Latch

`

4,096 x 64

FRAM Array

Data Latch

8

SDA

Counter

Serial to Parallel

Converter

Control Logic

SCL

WP

A0-A2

Pin Description

Pin Name Pin Number I/O Pin Description

A0-A2 1-2, 9 I Address 0-2. These pins are used to select one of up to 8 devices of

the same type on the same two -wire bus. To select the device, the
address value on the three pins must match the corresponding bits
contained in the device address. The address pins are pulled down

internally.
VSS 10 I Ground
SDA 11 I/O Serial Data Address. This is a bi-directional line for the two-wire

interface. It is open-drain and is intended to be wire -ORed with other

devices on the two -wire bus. The input buffer incorporates a schmitt

trigger for noise immunity and the output driver includes slope

control for falling edges. A pull-up resistor is required.
SCL 12 I Serial Clock. The serial clock line for the two -wire interface. Data is

clocked out of the part on the falling edge, and in on the rising edge.

The SCL input also incorporates a schmit trigger input for noise

immunity.
WP 19 I Write Protect. When tied to VDD, the entire array will be write-

protected. When WP is connected to ground, all addresses may be

written. This pin is pulled down internally.
VDD 20 I Supply Voltage. 5V

Ramtron FM24C256

10 April 2001 3/12

Overview

The FM24C256 is a serial FRAM memory. The
memory array is logically organized as 32,768 x 8 bit
memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the FRAM is similar to serial EEPROMs. The major
difference between the FM24C256 and a serial
EEPROM relates to its superior write performance.

Memory Architecture

When accessing the FM24C256, the user addresses
32,768 locations each with 8 data bits. These data bits
are shifted serially. The 32,768 addresses are
accessed using the two -wire protocol, which includes
a slave address (to distinguish other non-memory
devices), and an extended 16-bit address. Only the
lower 15 bits are used by the decoder for accessing
the memory. The upper address bit should be set to 0
for compatibility with larger devices in the future.

The access time for memory operation is essentially
zero beyond the time needed for the serial protocol.
That is, the memory is read or written at the speed of
the two-wire bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. That is, by the t ime a
new bus transaction can be shifted into the part, a
write operation will be complete. This is explained in
more detail in the interface section below.

Users expect several obvious system benefits from
the FM24C256 due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.

Note that the FM24C256 contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to
ensure that VDD is within data sheet tolerances to
prevent incorrect operation.

Two-wire Interface

The FM24C256 employs a bi-directional two-wire
bus protocol using few pins or board space. Figure 2
illustrates a typical system configuration using the
FM24C256 in a microcontroller-based system. The
industry standard two-wire bus is familiar to many
users but is described in this section.

By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24C256 always is a slave device.

The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including start, stop, data bit, or acknowledge. Figure
3 illustrates the signal conditions that specify the four
states. Detailed timing diagrams are in the electrical
specifications.

Figure 2. Typical Syst em Configuration

Microcontroller

SDA SCL

FM24C256

A0 A1 A2

SDA SCL

FM24C64

A0 A1 A2

VDD

Rmin = 1.8 K Ω

Rmax = tR/Cbus

Ramtron FM24C256

10 April 2001 4/12

Figure 3. Data Transfer Protocol

Stop

(Master)

Start

(Master)

7

Data bits

(Transmitter)

6 0

Data bit

(Transmitter)

Acknowledge

(Receiver)

SCL

SDA

Start Condition

A start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All commands should be preceded by a start
condition. An operation in progress can be aborted by
asserting a start condition at any time. Aborting an
operation using the start condition will ready the
FM24C256 for a new operation.

If during operation the power supply dro ps below the
specified VDD minimum, the system should issue a
start condition prior to performing another operation.

Stop Condition

A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24C256 should end
with a stop condition. If an operation is in progress
when a stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a stop condition.

Data/Address Transfer

All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.

Acknowledge

The acknowledge takes place after the 8th data bit has
been transferred in any transaction. During this state
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
no-acknowledge and the operation is aborted.

The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the no-acknowledge ends the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.

Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24C256
will continue to place data onto the bus as long as
the receiver sends acknowledges (and clocks). When
a read operation is complete and no more data is
needed, the receiver must not acknowledge the last
byte. If the receiver acknowledges the last byte, this
will cause the FM24C256 to attempt to drive the bus
on the next clock while the master is sending a new
command such as stop.

Slave Address

The first byte that the FM24C256 expects after a
start condition is the slave address. As shown in
Figure 4, the slave address contains the device type,
the device select address bits, and a bit that specifies
if the transaction is a read or a write.

Bits 7-4 are the device type and should be set to
1010b for the FM24C256. These bits allow other
types of function types to reside on the 2-wire bus
within an identical address range. Bits 3-1 are the
address select bits. They must match the
corresponding value on the external address pins to
select the device. Up to eight FM24C256s can reside
on the same two-wire bus by assigning a different
addres s to each. Bit 0 is the read/write bit. A 0
indicates a write operation.

Ramtron FM24C256

10 April 2001 5/12

Figure 4. Slave Address

1 0 1 0 A2 A1 A0 R/W

Slave

ID

Dev ice

Sel ect

7 6 5 4 3 2 1 0

Addressing Overview

After the FM24C256 (as receiver) acknowledges the
device address, the master can place the memory
address on the bus for a write operation. The address
requires two bytes. The first is the MSB. Since the
device uses only 15 address bits, the value of the
upper bits is don’t care. Following the MSB is the
LSB with the remaining eight address bits. The
address value is latched internally. Each access
causes the latched address value to be incremented
automatically. The current address is the value that is
held in the latch -- either a newly written value or the
address following the last access. The current address
will be held for as long as power remains or until a
new value is written. Reads always use the current
address. A random read address can be loaded by
beginning a write operation as explained below.

After transmission of each data byte, just prior to the
acknowledge, the FM24C256 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (7FFFh) is reached, the address latch will
roll over to 0000h. There is no limit to the number of
bytes that can be accessed with a single read or write
operation.

Data Transfer

After the address information has been transmitted,
data transfer between the bus master and the
FM24C256 can begin. For a read operation the
FM24C256 will place 8 data bits on the bus then wait
for an acknowledge from the master. If the
acknowledge occurs, the FM24C256 will transfer the
next sequential byte. If the acknowledge is not sent,
the FM24C256 will end the read operation. For a
write operation, the FM24C256 will accept 8 data
bits from the master then send an acknowledge. All
data transfer occurs msb (most significant bit) first.

Memory Operation

The FM24C256 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24C256 and a similar
configuration EEPROM during writes. The
complete operation for both writes and reads is
explained below.

Write Operation

All writes begin with a device address, then a
memory address. The bus master indicates a write
operation by setting the lsb of the device address to
a 0. After addressing, the bus master sends each byte
of data to the memory and the memory generates an
acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
from 7FFFh to 0000h.

Unlike other nonvolatile memory technologies,
there is no effective write delay with FRAM. Since
the read and write access times of the underlying
memory are the same, the user experiences no delay
through the bus. The entire memory cycle occurs in
less time than a single bus clock. Therefore, any
operation including read or write can occur
immediately following a write. Acknowledge
polling, a technique used with EEPROMs to
determine if a write is complete is unnecessary and
will always return a ready condition.

Internally, an actual memory write occurs after the
8th data bit is transferred. It will be complete before
the acknowledge is sent. Therefore, if the user
desires to abort a write without altering the memory
contents, this should be done using start or stop
condition prior to the 8th data bit. The FM24C256
uses no page buffering.

The memory array can be write protected using the
WP pin. Setting the WP pin to a high condition
(VIH) will write-protect all addresses. The
FM24C256 will not acknowledge data bytes that are
written when WP is active. In addition, the address
counter will not increment if writes are attempted to
these addresses. Setting WP to a low state (VIL)
will deactivate this feature. WP is pulled down to an
inactive state internally. The setting of WP should
remain stable from the start command until the
address is complete.

Figure 5 below illustrates both a single-byte and
multiple-write.

Ramtron FM24C256

10 April 2001 6/12

Figure 5 Byte Write

S ASlave Address 0 Address MSB A Data Byte A P

By Master

By FM24C256

Start Address & Data

Stop

Acknowledge

Address LSB A

X

Figure 6 Multiple Byte Write

S ASlave Address 0 Address MSB A Data Byte A P

By Master

By FM24C256

Start

Address & Data

Stop

Acknowledge

Address LSB A

X

Data Byte A

Read Operation

There are two basic types of read operations. They
are current address read and selective address read. In
a current address read, the FM24C256 uses the
internal address latch to supply the address. In a
selective read, the user performs a procedure to set
the address to a specific value.

Current Address & Sequential Read
As mentioned above the FM24C256 uses an internal

latch to supply the address for a read operation. A
current address read uses the existing value in the
address latch as a starting place for the read
operation. The system reads from the address
immediately following that of the last operation.

To perform a current address read, the bus master
supplies a device address with the lsb set to 1. This
indicates that a read operation is requested. After
receiving the complete device address, the
FM24C256 will begin shifting out data from the
current address on the next clock. The current address
is the value held in the internal address latch.

Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte, the internal address
counter will be incremented.

Each time the bus master acknowledges a byte,
this indicates that the FM24C256 should read
out the next sequential byte.

There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
most likely create a bus contention as the FM24C256

attempts to read out additional data onto the bus. The
four valid methods are as follows.

1. The bus master issues a no-acknowledge in the
9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
preferred.

2. The bus master issues a no-acknowledge in the
9th clock cycle and a start in the 10th.

3. The bus master issues a stop in the 9th clock
cycle.

4. The bus master issues a start in the 9th clock
cycle.

If the internal address reaches 7FFFh, it will wrap
around to 0000h on the next read cycle. Figures 7 and
8 below show the proper operation for current
address reads.

Selective (Random) Read
There is a simple technique that allows a user to

select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.

To perform a selective read, the bus master sends out
the device address with the lsb set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
loaded into the internal address latch. After the
FM24C256 acknowledges the address, the bus master
issues a start condition. This simultaneously aborts
the write operation and allows the read command to
be issued with the device address lsb set to a 1. The
operation is now a current address read.

Ramtron FM24C256

10 April 2001 7/12

Figure 7 Current Address Read

S ASlave Address 1 Data Byte 1 P

By Master

By FM24C256

Start Address

Stop

Acknowledge

No

Acknowledge

Data

Figure 8 Sequential Read

S ASlave Address 1 Data Byte 1 P

By Master

By FM24C256

Start Address

Stop

Acknowledge

No

Acknowledge

Data

Data ByteA

Acknowledge

Figure 9 Selective (Random) Read

S ASlave Address 1 Data Byte 1 P

By Master

By FM24C256

Start Address

Stop

No

Acknowledge

Data

S ASlave Address 0 Address MSB A

Start

Address

Acknowledge

Address LSB A

Data Retention and Endurance

Data retention is specified in the electrical
specifications below. For purposes of clarity, this
section contrasts the retention and endurance of
FRAM with EEPROM. The retention performance
of FRAM is very comparable to EEPROM in its
characteristics. However, the effect of endurance
cycles on retention is different.

A typical EEPROM has a write endurance
specification that is fixed. Surpassing the specified
level of cycles on an EEPROM usually leads to a
hard memory failure. By contrast, the effect of
increasing cycles on FRAM produces an increase in
the soft error rate. That is, there is a higher likelihood
of data loss but the memory continues to function
properly. A hard failure would not occur by simply
exceeding the endurance specification; simply a
reduction in data retention reliability. While enough
cycles would cause an apparent hard error, this is
simply a very high soft error rate. This characteristic
makes it problematic to assign a fixed endurance
specification.

Endurance is a soft specification. Therefore, the user
may operate the device with different levels of
endurance cycling for different portions of the
memory. For example, critical data needing the
highest reliability level could be stored in memory
locations that receive comparatively few cycles. Data
with shorter-term use could be located in an area
receiving many more cycles. A scratchpad area,
needing little if any retention can be cycled until
there is virtually no retention capability remaining.
This would occur several orders of magnitude above
the endurance spec.

Internally, a FRAM operates with a read and restore
mechanism similar to a DRAM. Therefore,
endurance cycles are applied for each access: read or
write. The FRAM architecture is based on an array of
rows and columns. Each access causes a cycle for an
entire row. Therefore, data locations targeted for
substantially differing numbers of cycles should not
be located within the same row. In the FM24C256, a
row is 64 bits wide. Each 8 bytes in the address
marks the beginning of a new row.

Ramtron FM24C256

10 April 2001 8/12

Applications

The versatility of FRAM technology fits into many
diverse applications. Clearly the strength of higher
write endurance and faster writes make FRAM
superior to EEPROM in all but one-time
programmable applications. The advantage is most
obvious in data collection environments where writes
are frequent and data must be nonvolatile.

The attributes of fast writes and high write endurance
combine in many innovative ways. A short list of
ideas is pr ovided here.

1. Data collection. In applications where data is
collected and saved, FRAM provides a superior
alternative to other solutions. It is more cost effective
than battery backup for SRAM and provides better
write attributes than EEPROM.

2. Configuration. Any nonvolatile memory can
retain a configuration. However, if the configuration
changes and power failure is a possibility, the higher
write endurance of FRAM allows changes to be
recorded without restriction. Any time the system
state is altered, the change can be written. This avoids
writing to memory on power down when the
available time is short and power scarce.

3. High noise environments. Writing to EEPROM
in a noisy environment can be challenging. When
severe noise or power fluctuations are present, the
long write time of EEPROM creates a window of
vulnerability during which the write can be
corrupted. The fast write of FRAM is complete
within a microsecond. This time is typically too short
for noise or power fluctuation to disturb it.

4. Time to market. In a complex system, multiple

software routines may need to access the nonvolatile
memory. In this environment the time delay
associated with programming EEPROM adds undue
complexity to the software development. Each
software routine must wait for complete
programming before allowing access to the next
routine. When time to market is critical, FRAM can
eliminate this simple obstacle. As soon as a write is
issued to the FM24C256, it is effectively done -- no
waiting.

5. RF/ID. In the area of contactless memory,

FRAM provides an ideal solution. Since RF/ID
memory is powered by an RF field, the long
programming time and high current consumption
needed to write EEPROM is unattractive. FRAM
provides a superior solution. The FM24C256 is
suitable for multi -chip RF/ID products.

6. Maintenance tracking. In sophisticated systems,

the operating history and system state during a failure
is important knowledge. Maintenance can be
expedited when this information has been recorded.
Due to the high write endurance, FRAM makes an
ideal system log. In addition, the convenient 2-wire
interface of the FM24C256 allows memory to be
distributed throughout the system using minimal
additional resources.

Ramtron FM24C256

10 April 2001 9/12

Electrical Specifications

Absolute Maximum Ratings

Description Ratings

Ambient storage or operating temperature

-40°C to + 85°C

Voltage on any pin with respect to ground -1.0V to +7.0V
D.C. output current on any pin 5 mA
Lead temperature (Soldering, 10 seconds)

300° C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only, and the functional operation of the device at these or any other conditions above those listed in the
operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability

DC Operating Conditions TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified

Symbol Parameter Min Typ Max Units Notes

VDD Main Power Supply 4.5 5.0 5.5 V 1
IDD VDD Supply Current

@ SCL = 100 kHz
@ SCL = 400 kHz
@ SCL = 1 MHz

115
400
1

150
500

1.2

µA
µA

mA

2

ISB Standby Current 1 10

µA

3

ILI Input Leakage Current 10

µA

4

ILO Output Leakage Current 10

µA

4

VIL Input Low Voltage -0.3 VDD x 0.3 V 1,5
VIH Input High Voltage VDD x 0.7 VDD + 0.5 V 1,5
VOL Output Low Voltage

@ IOL = 3 mA

0.4 V 1

ZI Input impedance of

WP, A0 -2

25
1

KΩ
MΩ

6

VHYS Input Hysteresis VDD x .05 V 1, 5

Notes

1. Referenced to VSS.

2. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V

3. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.

4. VIN or VOUT = VSS to VDD. Does not apply to pins with internal pull down resistors.

5. This parameter is characterized but not tested.

6. The input pull-down circuit is strong (25KΩ) when the input voltage is below VIL and weak (1MΩ) when the

input voltage is above VIH. This impedance is characterized and not tested.

Ramtron FM24C256

10 April 2001 10/12

AC Parameters TA = -40° C to + 85° C, VDD = 4.5V to 5.5V, CL = 100 pF unless otherwise specified

Symbol Parameter Min Max Min Max Min Max Units Notes

f

SCL

SCL Clock Frequency 0 100 0 400 0 1000 kHz

t

LOW

Clock Low Period 4.7 1.3 0.6

µs

t

HIGH

Clock High Period 4.0 0.6 0.4

µs

tAA SCL Low to SDA Data Out Valid 3 0.9 0.55

µs

t

BUF

Bus Free Before New

Transmission

4.7 1.3 0.5

µs

t

HD:STA

Start Condition Hold Time 4.0 0.6 0.25

µs

t

SU:STA

Start Condition Setup for Repeated

Start

4.7 0.6 0.25

µs

t

HD:DAT

Data In Hold 0 0 0 ns

t

SU:DAT

Data In Setup 250 100 100 ns
tR Input Rise Time 1000 300 300 ns 1
tF Input Fall Time 300 300 100 ns 1
t

SU:STO

Stop Condition Setup 4.0 0.6 0.25

µs

tDH Data Output Hold

(from SCL @ VIL)

0 0 0 ns

tSP Noise Suppression Time Constant

on SCL, SDA

50 50 50 ns

Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations.

1 This parameter is periodically sampled and not 100% tested.

Capacitance TA = 25° C, f=1.0 MHz, VDD = 5V

Symbol Parameter Max Units Notes

C

I/O

Input/output capacitance (SDA) 8 pF 1

CIN Input capacitance 6 pF 1

Notes

1 This parameter is periodically sampled and not 100% tested.

AC Test Conditions Equivalent AC Load Circuit

Input Pulse Levels VDD * 0.1 to VDD * 0.9
Input rise and fall times 10 ns
Input and output timing levels VDD*0.5

5.5V

Output

1800 Ω

100 pF

Ramtron FM24C256

10 April 2001 11/12

Diagram Notes

All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read
and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional
relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only.

Read Bus Timing

t

SU:SDA

Start

t

R

`

t

F

Stop Start

t

BUF

t

HIGH

1/fSCL

t

LOW

t

SP

t

SP

Acknowledge

t

HD:DAT

t

SU:DAT

t

AA

t

DH

SCL

SDA

Write Bus Timing

t

SU:STO

Start

Stop Start Acknowledge

t

AA

t

HD:DAT

t

HD:STA

t

SU:DAT

SCL

SDA

Data Retention TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified

Parameter Min Units Notes

Data Retention 10 Years 1

Notes

1. Data retention is specified at 85° C. The relationship between retention, temperature, and the associated

reliability level is characterized separately.

Ramtron FM24C256

10 April 2001 12/12

20-pin SOP

Pin 1

Index

Area

E H

D

A1

A

B

e

.10 mm
.004 in.

α

h

45

L

C

Controlling dimensions is in millimeters. Conversions to inches are
not exact.

Symbol Dim Min Nom. Max

A mm

in.

2.35

0.0926

2.65

0.1043

A1 mm

in.

0.10

0.004

0.30

0.0118

B mm

in.

0.33

0.013

0.51

0.020

C mm

in.

0.23

0.0091

0.32

0.0125

D mm

in.

12.6

0.4961

13.0

0.5118

E mm

in.

7.40

0.2914

7.60

0.2992

e mm

in.

1.27 BSC

0.050 BSC

H mm

in.

10.00

0.394

10.65

0.419

h mm

in.

0.25

0.010

0.75

0.029

L mm

in.

.40

0.016

1.27

0.050

α

0°

8°