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FIN1102
LVDS 2 Port High Speed Repeater
FIN1 102 LVDS 2 Port High Speed Repeater
January 2002
Revised February 2002
General Description
This 2 port repeater is designed for high speed interco nnects utilizing Low Voltage Differential Signaling (LVDS)
technology. The FIN1102 accepts and outputs LVDS levels
with a typical differential output swing of 330 mV which provides low EMI at ultr a low power dissipation even at high
frequencies. The FIN1102 provides a V
coupling on the inputs. In addition the FIN1102 can also
directly accept LVPECL, HSTL, and SSTL-2 for translat ion
to LVDS.
reference for AC
BB
Features
■ Greater than 800 Mbps full differential path
■ 3.3V power supply operation
■ 3.5 ps maximum random jitter and 135 ps maximum
deterministic jitter
■ Wide rail-to-rail common mode range
■ LVDS receiver inputs accept LVPECL, HSTL, and
SSTL-2 directly
■ Ultra low power consumption
■ 20 ps typical channel-to-chann el skew
■ Power off protection
■
> 7 kV HBM ESD Protection
■ Meets or exceeds the TIA/EIA-644-A LVDS standard
■ 14-lead TSSOP package saves space
■ Open circuit fail safe protection
■ V
reference output
BB
Ordering Code:
Order Number Package Number Package Description
FIN1102MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also availab l e in Tape and Reel. Specify by appending su ffix let te r “X” to the ordering code.
Pin Descriptions
Pin Name Description
, R
R
IN1+
R
, R
IN1−
D
, D
OUT1+
, D
D
OUT1−
EN Driver Enable Pin for All Output
V
CC
GND Ground
V
BB
Non-inverting LVDS Input
IN2+
Inverting LVDS Input
IN2−
Non-inverting Driver Output
OUT2+
Inverting Driver Output
OUT2−
Power Supply
Reference Voltage Output
Connection Diagram
Function Table
Inputs Outputs
EN
HHLHL
HLHLH
HFail Safe CaseH L
LXXZZ
H = HIGH Logic Le v el
L = LOW Logic Level
X = Don't Care
Z = High Impedance
© 2002 Fairchild Semiconductor Corporation DS500657 www.fairchildsemi.com
D
IN+
D
IN−
D
OUT+
D
OUT−
Functional Diagram
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Absolute Maximum Ratings(Note 1) Recommended Operating
Supply Voltage (VCC) −0.5V to +4.6V
FIN1102
LVDS DC Input Voltage (V
LVDS DC Output Voltage (V
Driver Short Circuit Current (I
Storage Temperature Range (T
Max Junction Temperature (T
Lead Temperature (T
) −0.5V to +4.6V
IN
) −0.5V to +4.6V
OUT
) Continuous 10 mA
OSD
) −65°C to +150°C
STG
)150°C
J
)
L
(Soldering, 10 seconds) 260
ESD (Human B ody Model) 7000V
ESD (Machine Model) 300V
Conditions
Supply Voltage (V
Magnitude of Differential
Voltage (|V
Common Mode Voltage
Range (V
Operating Temperature (T
°C
Note 1: The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperatur e and output/input loading va riables. Fairchild
does not recommend operation of circu it s o ut s ide databook specific ation.
) 3.0V to 3.6V
CC
|) 100 mV to V
ID
)(0V + |VID|/2) to (VCC − |VID|/2)
IC
) −40°C to +85°C
A
DC Electrical Characteristics
Symbol Parameter Test Conditions
V
Differential Input Threshold HIGH See Figure 1; VIC = +0.05V, +1.2V, or VCC − 0.05V 100 mV
TH
V
Differential Input Threshold LOW See Figure 1; VIC = +0.05V, +1.2V, or VCC − 0.05V −100 mV
TL
V
Input HIGH Voltage (EN) 2.0 V
IH
V
Input LOW Voltage (EN) GND 0.8 V
IL
V
Output Differential Voltage 250 330 450 mV
OD
∆V
ODVOD
V
OS
∆V
OS
I
OS
I
IN
I
OFF
I
CCZ
I
CC
I
OZ
V
IC
C
IN
C
OUT
V
BB
Note 2: All typical values are at TA = 25°C and with VCC = 3.3V .
Magnitude Change from
Differential LOW-to-HIGH RL = 100 Ω, Driver Enabled,
Offset Voltage See Figure 2 1.125 1.23 1.375 V
Offset Magnitude Change from
Differential LOW-to-HIGH
Short Circuit Output Current D
Input Current (EN, D
Power Off Input or Output Current VCC = 0V, VIN or V
Disabled Power Supply Current Drivers Disabled 4 7 mA
Power Supply Current Drivers Enabled, Any Valid Input Con dition 16.7 23 mA
Disabled Output Leakage Current Driver Disabled, D
Common Mode Voltage Range |VID| = 100 mV to V
Input Capacitance Enable Input 2.5
Output Capacitance 2.8 pF
Output Reference Voltage VCC = 3.3V, IBB = 0 to −275 µA 1.125 1.2 1.375 V
INx+
, D
INx−
= 0V and D
OUT+
Driver Enabled
V
= 0V, Driver Enabled ±3.4 ±6mA
OD
)VIN = 0V to VCC, Other Input = VCC or 0V
(for Differential Inputs)
= 0V to 3.6V
D
OUT−
= 0V,
OUT−
= 0V to 3.6V ±20 µA
OUT
= 0V to 3.6V or
OUT+
CC
LVDS Input 2.1
Min Typ Max
(Note 2)
0V + |VID|/2 VCC − (|VID|/2) V
CC
Units
CC
25 mV
25 mV
−3.4 −6mA
±20 µA
±20 µA
V
pF
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AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol Parameter Test Conditions
t
Differential Output Propagation Delay
PLHD
LOW-to-HIGH
t
t
t
t
t
t
t
f
t
Differential Output Propagation Delay
PHLD
HIGH-to-LOW R
Differential Output Rise Time (20% to 80%) |VID| = 200 mV to 450 mV, 0.29 0.4 0.58 ns
TLHD
Differential Output Fall Time (80% to 20%) VIC = |VID|/2 to VCC − (|VID|/2), 0.29 0.4 0.58 ns
THLD
Pulse Skew |t
SK(P)
, Channel-to-Channel Skew See Figure 3 and Figure 4 0.02
SK(LH)
(Note 4) 0.02
SK(HL)
Part-to-Part Skew (Note 5) 0.5 ns
SK(PP)
Maximum Frequency (Note 6)(Note 7) 400 800 MHz
MAX
Differential Output Enable Time
PZHD
- t
| Duty Cycle = 50%, 0.02 0.2 ns
PLH
PHL
= 100 Ω, CL = 5 pF,
L
from Z to HIGH
t
Differential Output Enable Time
PZLD
from Z to LOW RL = 100 Ω, CL = 5 pF,
t
Differential Output Disable Time See Figure 5 and Figure 6
PHZD
from HIGH to Z
t
Differential Output Disable Time
PLZD
from LOW to Z
t
LVDS Data Jitter, |VID| = 300 mV, PRBS = 223 - 1,
DJ
Deterministic VIC = 1.2V at 800 Mbps
t
LVDS Clock Jitter, |VID| = 300 mV,
RJ
Random (RMS) VIC = 1.2V at 400 MHz
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V, VID = 300 mV, VIC = 1.2V, unless otherwise specifie d.
Note 4: t
tion.
Note 5: t
direction (either Low-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: Passing criteria for maximum frequency is the output V
Note 7: Output loading is transm is sion line environment only; C
, t
SK(LH)
SK(PP)
is the skew between spe cifi ed out puts of a sing le dev ice whe n the ou tput s have iden tical lo ads an d ar e switch ing in the sam e direc-
SK(HL)
is the magnitude of th e difference i n differential p ropagation delay time s between i dentical ch annels of tw o devices switching in the same
> 200 mV and the duty cycle is 45% to 55% with all channels switching.
OD
is < 1 pF of stray test fixture capacitance.
L
Min Typ Max
(Note 3)
Units
0.75 1.1 1.75 ns
0.75 1.1 1.75 ns
0.15 ns
2.3 5 ns
2.5 5 ns
1.6 5 ns
1.9 5 ns
85 135 ps
2.1 3.5 ps
FIN1102
FIGURE 1. Differential Receiver Voltage Definitions and
Propagation and Transition Time Test Circuit
FIGURE 2. Differential Driver DC Test Circuit
Note A: All LVDS input pulses hav e f requency = 10 MHz, tR or
< = 0.5 ns
t
F
includes all probe and test fixture capacitances
Note B: C
L
FIGURE 3. Differential Driver Propagation Delay
and Transition Time Test Circuit
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FIN1102
Note A: All input pulses have freq uency = 10MHz, tR or tF < = 2 ns
includes all probe and test fixture capacit ances
Note B: C
L
FIGURE 5. Differential Driver Enable and Disable Circuit
FIGURE 4. AC Waveform
FIGURE 6. Enable and Disable AC Waveforms
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FIN1 102 LVDS 2 Port High Speed Repeater
14-Lead Thin Shrin k Small Ou tlin e Pack age (TSSOP), JEDEC MO-153, 4.4mm Wide
Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the l abe ling, can be reasonably expected to result in a significant injury to the
user.
Package Number MTC14
2. A critica l com ponen t in any compo nent o f a l ife supp ort
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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