Page 1
FDSS2407
N-Channel Dual MOSFET
62V, 3.3A, 132mΩ
FDSS2407 N-Channel Dual MOSFET
December 2004
Features
62V, 132mΩ, 5V Logic Level Gate Dual MOSFET in SO-8
5V Logic Level feedback signal of the drain to source
voltage. Multiple devices can be wired “OR’d” to a single
monitoring circuit input.
Gate Drive Disable Input. Multiple devices controllable by
a single disable transistor.
Qualified to AEC Q101
Applications
Automotive Injector Driver
Solenoid Driver
Source 1
Branding Dash
General Description
This dual N-Channel MOSFET provides added functions as
compared to a conventional Power MOSFET. These are: 1.
A drain to source voltage feedback signal and 2. A gate
drive disable control function that previously required
external discrete circuitry. Including these functions within
the MOSFET saves printed circuit board space. The drain to
source voltage feedback function provides a 5V level output
whenever the drain to source voltage is above 62V. This can
monitor the time an inductive load takes to dissipate its
stored energy. Multiple feedback signals can be wired
“OR’d” together to a single input of the monitoring circuit.
The gate disable function allows the device to be turned off
independent of the drive signal on the gate. This function
permits a second control circuit the ability to deactivate the
load if necessary. It can also be wired “OR’d” allowing
multiple devices to be controlled by a single open collector /
drain control transistor.
Internal Diagram
1
8
Drain 1
1
2
3
4
SO-8
Pin 5 - Drain Feedback Output
Pin 7 - Gate Drive Disable Input
©2004 Fairchild Semiconductor Corporation
FDSS2407 Rev. A
5
Gate 1
Source 2
Gate 2
2
3
4
7
Gate Disable
6
Drain 2
5
Drain FBK
www.fairchildsemi.com1
Page 2
FDSS2407 N-Channel Dual MOSFET
MOSFET Maximum Ratings T
=25°C unless otherwise noted
A
Symbol Parameter Ratings Units
V
DSS
V
GS
Drain to Source Voltage 62 V
Gate to Source Voltage ±20 V
Drain Current
I
D
Continuous (T
Continuous (T
= 25oC, VGS = 10V, R
A
= 25oC, VGS = 5V, R
A
= 55oC/W)
θJA
= 55oC/W) 3.0 A
θJA
3.3 A
Pulsed Figure 4 A
E
AS
P
D
, T
T
J
STG
Single Pulse Avalanche Energy ( Note 1) 140 mJ
Power dissipation 2.27 W
o
Derate above 25
C18mW/
Operating and Storage Temperature -55 to 150
Thermal Characteristics
R
θJA
R
θJA
R
θJA
Pad Area = 0.50 in2 (323 mm2) (Note 2) 55
Pad Area = 0.027 in2 (17.4 mm2) (Note 3) 180
Pad Area = 0.006 in2 (3.87 mm2) (Note 4) 200
o
C/W
o
C/W
o
C/W
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
2407 FDSS2407 SO-8 330 mm 12 mm 2500
Electrical Characteristics T
Symbol Parameter Test Conditions Min Typ Max Units
= 25°C unless otherwise noted
A
o
C
o
C
Off Characteristics
B
I
DSS
I
GSS
VDSS
Drain to Source Breakdown Voltage ID = 5mA, VGS = 0V 62 - - V
Zero Gate Voltage Drain Current
Gate to Source Leakage Current VGS = ±20V - - ±100 nA
On Characteristics
V
GS(TH)
r
DS(ON)
Gate to Source Threshold Voltage VGS = VDS, ID = 250µA1-3V
Drain to Source On Resistance
Dynamic Characteristics
C
ISS
C
OSS
C
RSS
R
G
Q
g(TOT)
Q
g(TH)
Q
gs
Q
gs2
Q
gd
Input Capacitance
Output Capacitance - 140 - pF
Reverse Transfer Capacitance - 16 - pF
Gate Resistance - 8500 - Ω
Total Gate Charge at 5V VGS = 0V to 5V
Threshold Gate Charge V
Gate to Source Gate Charge - 1.2 - nC
Gate Charge Threshold to Plateau - 0.8 - nC
Gate to Drain “Miller” Charge - 2.0 - nC
= 15V, VGS=0V - - 1
V
DS
V
= 15V, VGS=0V,
DS
=150oC
T
A
I
= 3.3A, VGS = 10V - 0.099 0.110
D
= 3.0A, VGS = 5V - 0.115 0.132
I
D
V
= 15V, VGS = 0V,
DS
- - 2 5 0
- 300 - pF
f = 75kHz
-3.34.3nC
= 0V to 1V - 0.4 0.5 nC
GS
V
DD
= 3.3A
I
D
I
= 1.0mA
g
= 30V
µA
Ω
FDSS2407 Rev. A
2
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Page 3
Switching Characteristics (V
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Turn-On Time
Turn-On Delay Time - 630 - ns
Rise Time - 1200 - ns
Turn-Off Delay Time - 8700 - ns
Fall Time - 3500 - ns
Turn-Off Time - - 18500 ns
GS
= 10V)
Drain-Source Diode Characteristics
V
SD
t
rr
Q
RR
Source to Drain Diode Voltage
Reverse Recovery Time ISD = 3.3A, dISD/dt = 100A/µs--45ns
Reverse Recovered Charge ISD = 3.3A, dISD/dt = 100A/µs- -60nC
Drain Feedback Characteristics
V
FBK(Low)
V
FBK(High)
Feedback to Source Voltage VDS = 35V, R
Feedback to Source Voltage VDS = 62V, R
Gate Drive Disable Characteristics
V
DIS(High)
V
DIS(Low)
Gate Drive Disable Input Voltage, Gate
Enabled
Gate Drive Disable Input Voltage, Gate
Disabled
- - 2700 ns
= 30V, ID = 3.3A
V
DD
= 10V, RGS = 47Ω
V
GS
I
= 3.3A - - 1.25 V
SD
= 1.7A - - 1.0 V
I
SD
FBK-SOURCE
FBK-SOURCE
V
= 5V, ID = 3.0A, TJ=25oC3 - - V
GS
VGS = VDS = 10V, ID ≤ 250µA,
=150oC
T
J
=51KΩ -11.5V
=51KΩ 3.5 4.4 - V
--0.4V
FDSS2407 N-Channel Dual MOSFET
Notes:
1. Starting TJ = 25°C, L = 42mH, IAS = 2.6A, VDD = 62V, VGS = 10V.
2. 55oC/W measured using FR-4 board with 0.50 in2 (323 mm2) copper pad at 1 second.
3. 180oC/W measured using FR-4 board with 0.027 in2 (17.4 mm2) copper pad at 1000 seconds.
4. 200oC/W measured using FR-4 board with 0.006 in2 (3.87 mm2) copper pad at 1000 seconds.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
FDSS2407 Rev. A
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
certification.
3
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Page 4
Typical Characteristics T
= 25°C unless otherwise noted
A
FDSS2407 N-Channel Dual MOSFET
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
125
TA, AMBIENT TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
0.1
, NORMALIZED
θJA
Z
THERMAL IMPEDANCE
0.01
-5
10
-4
10
-3
10
10
t, RECTANGULAR PULSE DURATION (s)
SINGLE PULSE
-2
4
VGS = 10V
3
2
, DRAIN CURRENT (A)
D
I
1
R
θJA
0
25 50 75 100 125 150
VGS = 5V
= 55oC/W
TA, AMBIENT TEMPERATURE (oC)
Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature
R
= 55oC/W
θJA
P
DM
t
1
t
θJA
10
x R
2
2
+ T
θJA
A
2
3
10
NOTES:
DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z
-1
10
0
10
1
10
200
100
, PEAK CURRENT (A)
10
DM
I
3
-5
10
FDSS2407 Rev. A
VGS = 10V
Figure 3. Normalized Maximum Transient Thermal Impedance
TA = 25oC
FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:
I = I25
1
10
10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
VGS = 5V
-4
R
= 55oC/W
θJA
-3
10
-2
10
-1
10
0
10
t, PULSE W IDTH (s)
Figure 4. Peak Current Capability
4
o
C DERATE PEAK
150 - T
A
125
2
10
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3
10
Page 5
FDSS2407 N-Channel Dual MOSFET
Typical Characteristics (Continued) T
100
10
OPERATION IN THIS
1
, DRAIN CURRENT (A)
D
I
0.1
AREA MAY BE
LIMITED BY r
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
110
DS(ON)
R
θJA
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
15
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 15V
DD
10
TJ = 25oC
100µs
1ms
10ms
= 55oC/W
= 25°C unless otherwise noted
A
10
STARTING TJ = 150oC
, AVALANCHE CURRENT (A)
If R = 0
AS
I
tAV = (L)(IAS)/(1.3*RATED BV
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BV
1
100
0.01 0.1 1
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
15
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
10
VGS = 10V
STARTING TJ = 25oC
- VDD)
DSS
- VDD) +1]
DSS
tAV, TIME IN AVALANCHE (ms)
Capability
10
VGS = 5V
VGS = 3.5V
5
, DRAIN CURRENT (A)
D
I
TJ = 150oC
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5
VGS, GATE TO SOURCE VOLTAGE (V)
TJ = -55oC
Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics
240
210
ID = 3.3A
180
150
, DRAIN TO SOURCE
ON RESISTANCE (mΩ)
DS(ON)
r
120
ID = 1A
90
246810
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
5
, DRAIN CURRENT (A)
D
I
0
0 0.5 1.0 1.5 2.0 2.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.5
1.0
ON RESISTANCE
NORMALIZED DRAIN TO SOURCE
0.5
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
VGS = 3V
VGS = 10V, ID = 3.3A
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
FDSS2407 Rev. A
5
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Page 6
FDSS2407 N-Channel Dual MOSFET
Typical Characteristics (Continued) T
1.2
1.0
0.8
NORMALIZED GATE
THRESHOLD VOLTAGE
0.6
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
= 25°C unless otherwise noted
A
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
6
FBK voltage measured across
a 51KΩ load resistor.
5
4
3
2
FBK, FEEDBACK VOLTAGE (V)
1
0
TJ = 25oC
20 30 40 50 60 70
TJ = 150oC
TJ = -55oC
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.2
ID = 5mA
1.1
1.0
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
0.9
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
1000
C
= CGS + C
ISS
C
≅ C
OSS
100
C, CAPACITANCE (pF)
V
= 0V, f = 75kHz
GS
10
0.1
VDS, DRAIN TO SOURCE VOLTAGE (V)
110
DS
C
= C
RSS
GD
+ C
GD
GD
20
Figure 13. Feedback Voltage vs Drain to Source
Voltage
500
400
300
200
, DRAIN TO SOURCE
ON RESISTANCE (mΩ)
DS(ON)
r
100
0
12345
V
, GATE DISABLE VOLTAGE (V)
DIS
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 5V, ID = 3A
TJ = 150oC
TJ = 25oC
TJ = -55oC
Figure 15. Drain to Source On Resistance vs
Gate Disable Voltage
FDSS2407 Rev. A
Figure 14. Capacitance vs Drain to Source
Voltage
10
TJ = 150oC
8
TJ = 25oC
6
4
, GATE TO SOURCE
GS
VOLTAGE
V
2
0
012345
TJ = -55oC
V
, GATE DISABLE VOLTAGE (V)
DIS
Figure 16. Gate to Source Voltage vs Gate
Disable Voltage
6
VGS = V
DS
ID = 250µA
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Page 7
FDSS2407 N-Channel Dual MOSFET
Typical Characteristics (Continued) T
10
VDD = 30V
8
6
4
2
, GATE TO SOURCE VOLTAGE (V)
GS
V
0
02468
Figure 17. Gate Charge Waveforms for Constant Gate Currents
Test Circuits and Waveforms
V
DS
L
VAR Y tP TO OBTAIN
REQUIRED PEAK I
V
GS
AS
R
G
DUT
= 25°C unless otherwise noted
A
WAVEFORMS IN
DESCENDING ORDER:
ID = 3.3A
ID = 1A
Qg, GATE CHARGE (nC)
+
V
DD
-
BV
DSS
t
P
I
AS
V
DS
V
DD
t
0V
P
I
AS
0.01Ω
0
t
AV
Figure 18. Unclamped Energy Test Circuit Figure 19. Unclamped Energy Waveforms
V
DS
R
I
g(REF)
L
V
GS
+
V
DD
-
DUT
V
DD
V
0
I
g(REF)
GS
= 1V
Q
g(TOT)
V
DS
V
GS
Q
gs2
Q
g(TH)
Q
gs
Q
gd
0
Figure 20. Gate Charge Test Circuit Figure 21. Gate Charge Waveforms
V
= 5V
GS
FDSS2407 Rev. A
7
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Page 8
Test Circuits and Waveforms (Continued)
FDSS2407 N-Channel Dual MOSFET
V
DS
R
L
V
GS
R
GS
V
GS
DUT
+
V
DD
-
V
DS
0
V
GS
10%
0
t
d(ON)
90%
t
ON
50%
10%
t
r
PULSE WIDTH
t
d(OFF)
Figure 22. Switching Time Test Circuit Figure 23. Switching Time Waveforms
V
DS
+
LM324
-
NC
V
DISABLE
DUT
90%
t
OFF
t
f
90%
10%
50%
FDSS2407 Rev. A
Figure 24. Gate to Source Voltage vs Gate Disable Voltage
8
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Page 9
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and
(oC), and thermal resistance R
A
is never exceeded.
JM
DM
θJA
, in an
(oC/W)
serves as the basis for establishing the rating of the part.
P
-------------------------------=
DM
TJMTA–()
R
θJA
(EQ. 1)
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
and influenced by many factors:
is complex
DM
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 25
defines the R
copper (component side) area. This is for a horizontally
for the device as a function of the top
θJA
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
160
COPPER BOARD AREA - DESCENDING ORDER
2
0.020 in
2
0.140 in
2
0.257 in
, THERMAL
qJA
Z
C/W)
o
IMPEDANCE (
120
80
40
0.380 in
0.493 in
2
2
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 25 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
R
The transient thermal impedance (Z
varied top copper board area. Figure 26 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
79.9
θ JA
200
150
C/W)
o
(
θJA
R
100
50
0.001 0.01 1 10
15
+=
------------- ------------------
0.14 Area+
θJA
R
θJA
AREA, TOP COPPER AREA (in2)
0.1
(EQ. 2)
) is also effected by
= 79.9 + 15/(0.14+Area)
Figure 25. Thermal Resistance vs Mounting
Pad Area
FDSS2407 N-Channel Dual MOSFET
FDSS2407 Rev. A
0
-1
10
0
10
t, RECTANGULAR PULSE DURATION (s)
1
10
2
10
3
10
Figure 26. Thermal Impedance vs Mounting Pad Area
9
www.fairchildsemi.com
Page 10
PSPICE Electrical Model
.SUBCKT FDSS2407 2 1 3 101 102 ; rev July 2004
Ca 12 8 1e-10
Cb 15 14 4e-10
Cin 6 8 2.8e-10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
CGATE 9 20 5e-9
DDISABLE 20 101 DDISABLEMOD
DFBK1 104 103 DFBK1MOD
DFBK2 7 104 DFBK2MOD
DFBK3 104 102 DFBK3MOD
RFBK1 5 103 RFBK1MOD 13e3
RFBK2 104 7 RFBK2MOD 2.15e3
Ebreak 11 7 17 18 67.4
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
GATE
1
Lgate 1 9 1.8e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 0.6e-9
RLgate 1 9 18
GATE
DISABLE
101
RLdrain 2 5 10
RLsource 3 7 6
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 3.5e-2
LGATE
RLGATE
DDISABLE
CGATE
RGATE
9
CA
ESG
EVTEMP
+
20
S1A
12
S1B
18
22
Rgate 9 20 RgateMOD 8.63e3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 5.3e-2
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*20),3.5))}
.MODEL DbodyMOD D (IS=1.1E-12 N=1.05 IKF=4e-1 RS=4.2e-2 TRS1=3e-4 TRS2=1.3e-6
+ CJO=3.3e-10 TT=3e-8 M=0.38, XTI=3.5)
.MODEL DbreakMOD D (RS=1 TRS1=1e-3 TRS2=-9e-6)
.MODEL DplcapMOD D (CJO=1.97e-10 IS=1e-30 N=10 M=0.84)
.MODEL DDISABLEMOD D (RS=30 IS=1e-15 BV=4.7 TBV1=-3e-4 TBV2=-3e-6 XTI=0)
.MODEL DFBK1MOD D (IS=1e-15 BV=23.8 IKF=2 TBV1=-6e-4 TBV2=6e-6)
.MODEL DFBK2MOD D (RS=1 IS=1e-30 BV=5.6 N=3.3 NBV=1)
.MODEL DFBK3MOD D (RS=1 IS=1e-15 BV=4.2 NBV=2.5)
.MODEL MmedMOD NMOS (VTO=1.7 KP=1.08 IS=1e-30 N=10 TOX=1 L=1u W=1u RG= 8.56e3)
.MODEL MstroMOD NMOS (VTO=2 KP=14 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.5 kp=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG= 8.56e4 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.05e-3 TC2=-9e-7)
.MODEL RdrainMOD RES (TC1=9e-3 TC2=2.7e-5)
.MODEL RSLCMOD RES (TC1=2e-3 TC2=6e-6)
.MODEL RsourceMOD RES (TC1=3e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-1.1e-3 TC2=-3.3e-6)
.MODEL RvtempMOD RES (TC1=-1.6e-3 TC2=1e-7)
.MODEL RFBK1MOD RES (TC1=-1.4e-3 TC2=1e-6)
.MODEL RFBK2MOD RES (TC1=-1.4e-3 TC2=1e-6)
.MODEL RgateMOD RES (TC1=-1.4e-3 TC2=1e-5)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-3.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.0 VOFF=-4.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.0 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-1.0)
.ENDS
DPLCAP
10
RSLC2
6
8
EVTHRES
+
+
19
8
6
-
S2A
13814
13
S2B
13
+
+
6
EGS EDS
8
-
-
15
CIN
CB
-
+
-
5
51
5
51
21
MSTRO
14
5
8
RSLC1
+
ESLC
50
RDRAIN
16
8
MMED
8
DBREAK
11
+
EBREAK
17
18
-
MWEAK
RSOURCE
RBREAK
17 18
IT
RVTHRES
DBODY
RFBK2
7
-
+
22
103
104
RVT EMP
19
VBAT
LDRAIN
RLDRAIN
RFBK1
DFBK1
DFBK3
DFBK2
LSOURCE
RLSOURCE
DRAIN
INJ FBK
102
SOURCE
FDSS2407 N-Channel Dual MOSFET
2
3
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
10
www.fairchildsemi.com
FDSS2407 Rev. A
Page 11
SABER Electrical Model
REV July 2004
template FDSS2407 n2,n1,n3,n101,n102
electrical n2,n1,n3,n101,n102
{
var i iscl
dp..model dbodymod = (isl=1.1e-12,nl=1.05,ikf=4e-1,rs=4.2e-2,trs1=3e-4,trs2=1.3e-6,cjo=3.3e-10,tt=3e-8,m=0.38,xti=3.5)
dp..model dbreakmod = (rs=1,trs1=1e-3,trs2=-9e-6)
dp..model ddisablemod = (rs=30, isl=1e-15,bv=4.7,tbv1=-3e-4,tbv2=-3e-6,xti=0)
dp..model dfbk1mod = (isl=1e-15,bv=23.8,ikf=2,tbv1=-6e-4,tbv2=6e-6)
dp..model dfbk2mod = (rs=1,isl=1e-30,bv=5.6,nl=3.3,nbv=1)
dp..model dfbk3mod = (rs=1,isl=1e-15,bv=4.2,nbv=2.5)
dp..model dplcapmod = (cjo=1.97e-10,isl=10e-30,nl=10,m=0.84)
m..model mmedmod = (type=_n,vto=1.7,kp=1.08,is=1e-30,tox=1)
m..model mstrongmod = (type=_n,vto=2,kp=14,is=1e-30,tox=1)
m..model mweakmod = (type=_n,vto=1.5,kp=0.04,is=1e-30, tox=1,rs=0.1)
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.0,voff=-3.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.0,voff=-4.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.0,voff=-0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-1.0)
c.ca n12 n8 = 1e-10
c.cb n15 n14 = 4e-10
c.cin n6 n8 = 2.8e-10
c.cgate n9 n20 = 5e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
dp.ddisable n20 n101 = model=ddisablemod
dp.dfbk1 n104 n103 = model=dfbk1mod
dp.dfbk2 n7 n104 = model=dfbk2mod
dp.dfbk3 n104 n102 = model=dfbk3mod
spe.ebreak n11 n7 n17 n18 = 67.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 1.8e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 0.6e-9
GATE
1
GATE
DISABLE
101
LGATE
RLGATE
DDISABLE
res.rlgate n1 n9 = 18
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 6
res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=-9e-7
res.rdrain n50 n16 = 3.5e-2,tc1=9e-3,tc2=2.7e-5
res.rgate n9 n20 = 8.63e3,tc1=-1.4e-3,tc2=1e-5
res.rfbk1 n5 n103 = 13e3,tc1=-1.4e-3,tc2=1e-6
res.rfbk2 n104 n7 = 2.15e3,tc1=-1.4e-3,tc2=1e-6
res.rslc1 n5 n51 = 1e-6,tc1=2e-3,tc2=6e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 5.3e-2,tc1=3e-3,tc2=1e-6
res.rvthres n22 n8 = 1,tc1=-1.1e-3,tc2=-3.3e-6
res.rvtemp n18 n19 = 1,tc1=-1.6e-3,tc2=1e-7
CGATE
RGATE
9
CA
ESG
EVTEMP
+
18
22
20
S1A
12
S1B
EGS EDS
10
6
8
+
-
13814
13
+
+
RSLC2
6
S2A
13
S2B
6
8
-
-
DPLCAP
EVTHRES
+
19
8
CIN
15
CB
-
+
-
5
51
MSTRO
14
5
8
RSLC1
ISCL
50
RDRAIN
16
21
8
MMED
8
DBREAK
11
MWEAK
EBREAK
+
RSOURCE
RBREAK
17 18
IT
RVTHRES
17
18
-
DBODY
RFBK2
7
-
+
22
RVT EMP
19
103
104
VBAT
LDRAIN
RLDRAIN
RFBK1
DFBK1
DFBK3
DFBK2
LSOURCE
RLSOURCE
DRAIN
INJ FBK
102
SOURCE
FDSS2407 N-Channel Dual MOSFET
2
3
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/20))** 3.5))
}
}
11
FDSS2407 Rev. A
www.fairchildsemi.com
Page 12
FDSS2407 N-Channel Dual MOSFET
SPICE Thermal Model
REV July 2004
FDSS2407T
Copper Area =0.5 in
2
CTHERM1 Junction c2 1.2e-4
CTHERM2 c2 c3 2e-3
CTHERM3 c3 c4 2e-2
CTHERM4 c4 c5 3.0e-2
CTHERM5 c5 c6 4e-2
CTHERM6 c6 c7 7e-2
CTHERM7 c7 c8 2e-1
CTHERM8 c8 Ambient 2.8
RTHERM1 Junction c2 1.4
RTHERM2 c2 c3 2.0
RTHERM3 c3 c4 2.8
RTHERM4 c4 c5 9.0
RTHERM5 c5 c6 18.0
RTHERM6 c6 c7 26.0
RTHERM7 c7 c8 28.0
RTHERM8 c8 Ambient 29.0
SABER Thermal Model
Copper Area = 0.5 in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th c2 =1.2e-4
ctherm.ctherm2 c2 c3 =2e-3
ctherm.ctherm3 c3 c4 =2e-2
ctherm.ctherm4 c4 c5 =3.0e-2
ctherm.ctherm5 c5 c6 =4e-2
ctherm.ctherm6 c6 c7 =7e-2
ctherm.ctherm7 c7 c8 =2e-1
ctherm.ctherm8 c8 tl =2.8
rtherm.rtherm1 th c2 =1.4
rtherm.rtherm2 c2 c3 =2.0
rtherm.rtherm3 c3 c4 =2.8
rtherm.rtherm4 c4 c5 =9.0
rtherm.rtherm5 c5 c6 =18.0
rtherm.rtherm6 c6 c7 =26.0
rtherm.rtherm7 c7 c8 =28.0
rtherm.rtherm8 c8 tl =29.0
}
2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
JUNCTION
th
CTHERM1
8
CTHERM2
7
CTHERM3
6
CTHERM4
5
CTHERM5
4
CTHERM6
3
CTHERM7
2
CTHERM8
tl
AMBIENT
FDSS2407 Rev. A
12
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FDSS2407 N-Channel Dual MOSFET
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design
Preliminary First Production This datasheet contains preliminary data, and
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete Not In Production This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I15
FDSS2407 Rev. A
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