Datasheet FDS8978 Datasheet (Fairchild)

FDS8978 N-Channel PowerTrench

30V, 7.5A, 18mΩ

®

MOSFET

FDS8978 Dual N-Channel PowerTrench

January 2011

Features

 r

 High performance trench technology for extremely low

 Low gate charge

 High power and current handling capability

 100% Rg Tested

 RoHS Compliant

= 18mΩ, V

DS(on)

= 21mΩ, V

DS(on)

r

DS(on)

SO-8

MOSFET Maximum Ratings T

Symbol Parameter Ratings Units

V

DSS

V

GS

I

D

E

AS

P

D

, T

T

J

STG

= 10V, ID = 7.5A

GS

= 4.5V, ID = 6.9A

GS

D2

D1

G2

S2

G1

Pin 1

Drain to Source Voltage 30 V

Gate to Source Voltage ±20 V

Drain Current

Continuous (T

Pulsed 49 A

Single Pulse Avalanche Energy (Note 1) 57 mJ

Power dissipation 1.6 W

Derate above 25

Operating and Storage Temperature -55 to 150

= 25oC, VGS = 10V, R

A

= 25oC, VGS = 4.5V, R

A

o

C13mW/

S1

= 25°C unless otherwise noted

A

θJA

General Description

This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low r

and fast switching speed.

DS(on)

Applications

 DC/DC converters

D2

5

6

D2

D1

= 50oC/W)

= 50oC/W) 6.9 A

7

8

Q2

Q1

7.5 A

4

3

2

1

G2

S2

G1

S1

o

®

MOSFET

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

Thermal Resistance, Junction to Case (Note 2) 40

Thermal Resistance, Junction to Ambient (Note 2a) 78

Thermal Resistance, Junction to Ambient (Note 2c) 135

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDS8978 FDS8978 SO-8 330mm 12mm 2500 units

1

o

C/W

o

C/W

o

C/W

www.fairchildsemi.com

FDS8978 Dual N-Channel PowerTrench

Electrical Characteristics T

= 25°C unless otherwise noted

J

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B

VDSS

I

DSS

I

GSS

Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V

V

= 24V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TJ = 150oC - - 250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(on)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1.2 - 2.5 V

ID = 7.5A, VGS = 10V - 14 18

Drain to Source On Resistance

ID = 6.9A, VGS = 4.5V - 17 21

I

= 7.5A, VGS = 10V,

D

TJ = 150oC

- 22 29

Dynamic Characteristics

C

ISS

C

OSS

C

RSS

R

G

Q

g(TOT)

Q

g(5)

Q

gs

Q

gs2

Q

gd

Input Capacitance

Output Capacitance - 191 - pF

Reverse Transfer Capacitance - 11 2 - pF

VDS = 15V, VGS = 0V, f = 1MHz

- 907 1270 pF

Gate Resistance VGS = 0.5V, f = 1MHz - 1.2 4.0 Ω

Total Gate Charge at 10V VGS = 0V to 10V

Total Gate Charge at 5V VGS = 0V to 5V - 9 14 nC

VDD = 15V ID = 7.5A

- 17 26 nC

Gate to Source Gate Charge - 2.3 - nC

Gate Charge Threshold to Plateau - 1.5 - nC

Gate to Drain “Miller” Charge - 3.3 - nC

µA

mΩ

®

MOSFET

Switching Characteristics (V

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time

Turn-On Delay Time - 7 10.5 ns

Rise Time - 37 55.5 ns

Turn-Off Delay Time - 48 72 ns

Fall Time - 24 36 ns

Turn-Off Time - 72 108 ns

GS

= 10V)

- 44 66 ns

VDD = 15V, ID = 7.5A VGS = 10V, RGS = 16Ω

Drain-Source Diode Characteristics

I

= 7.5A - - 1.25 V

V

SD

t

rr

Q

RR

Notes:

1: Starting TJ = 25°C, L = 1mH, IAS = 7.5A, VDD = 30V, VGS = 10V. 2: R

θJA

drain pins. R

a) 78°C/W when mounted on a 0.5 in

b) 125°C/W when mounted on a 0.02 in2 pad of 2 oz copper. c) 135°C/W when mounted on a minimun pad.

Source to Drain Diode Voltage

Reverse Recovery Time ISD = 7.5A, dISD/dt = 100A/µs - 19 25 ns

Reverse Recovered Charge ISD = 7.5A, dISD/dt = 100A/µs - 10 13 nC

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the

is guaranteed by design while R

θJC

2

pad of 2 oz copper.

is determined by the user’s board design.

θJA

SD

I

= 2.1A - - 1.0 V

SD

www.fairchildsemi.com2

FDS8978 Dual N-Channel PowerTrench

Typical Characteristics T

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

Figure 1.

Normalized Power Dissipation vs

= 25°C unless otherwise noted

J

Ambient Temperature

2

1

θJA

Z

0.1

DUTY CYCLE-DESCENDING ORDER

D = 0.5

0.2

0.1

0.05

0.02

0.01

125

8

7

6

5

V

= 10V

GS

4

V

= 4.5V

3

, DRAIN CURRENT (A)

2

D

I

1

R

= 78oC/W

θJA

0

25 50 75 100 125 150

, AMBIENT TEMPERATURE (

T

A

Figure 2.

Maximum Continuous Drain Current vs

GS

Ambient Temperature

o

C)

®

MOSFET

NORMALIZED THERMAL

IMPEDANCE,

0.001

1000

, PEAK TRANSIENT POWER (W)

(PK)

P

0.01

100

10

0.5

SINGLE PULSE

R

= 135oC/W

θJA

-4

10

-3

10

Figure 3.

-2

10

t, RECTANGULAR PULSE DURATION (s)

-1

10

0

10

1

10

Normalized Maximum Transient Thermal Impedance

VGS = 10V

2

10

SINGLE PULSE

R

= 135oC/W

θJA

= 25oC

T

A

3

10

1

-4

10

-3

10

Figure 4.

-2

10

-1

10

t, PULSE WIDTH (s)

0

10

Single Pulse Maximum Power Dissipation

1

2

10

3

10

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Typical Characteristics T

= 25°C unless otherwise noted

J

FDS8978 Dual N-Channel PowerTrench

100

If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

10

, AVALANCHE CURRENT (A)

AS

I

1

STARTING TJ = 150oC

0.01 0.1 1 10 100

tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 5.

Unclamped Inductive Switching

Capability

50

PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX

40

30

20

, DRAIN CURRENT (A)

10

D

I

VGS = 10V

VGS = 5V

VGS = 4.5V

VGS = 3.5V

VGS = 3V

50

PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX

40

V

= 5V

DS

30

20

, DRAIN CURRENT (A)

10

D

I

0

12345

50

40

30

20

, DRAIN TO SOURCE

ON RESISTANCE (mW)

DS(ON)

r

10

TJ = 25oC

TJ = 150oC

VGS, GATE TO SOURCE VOLTAGE (V)

Figure 6.

ID = 10.2A

ID = 1A

TJ = -55oC

Transfer Characteristics

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

®

MOSFET

0

0.0 0.2 0.4 0.6 0.8 1.0

VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Saturation Characteristics

1.6 PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

1.4

1.2

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.8

-80 -40 0 40 80 120 160

Figure 9.

TJ, JUNCTION TEMPERATURE (oC)

Normalized Drain to Source On

Resistance vs Junction Temperature

VGS = 10V, ID = 10.2A

0

246810

Figure 8.

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

-80 -40 0 40 80 120 160

Figure 10.

, GATE TO SOURCE VOLTAGE (V)

V

GS

Drain to Source On Resistance vs Gate

Voltage and Drain Current

VGS = VDS, ID = 250µA

TJ, JUNCTION TEMPERATURE (oC)

Normalized Gate Threshold Voltage vs

Junction Temperature

www.fairchildsemi.com4

FDS8978 Dual N-Channel PowerTrench

Typical Characteristics T

1.10 ID = 250µA

1.05

1.00

0.95

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.90

-80 -40 0 40 80 120 160

T

, JUNCTION TEMPERATURE (oC)

J

Figure 11.

Normalized Drain to Source

= 25°C unless otherwise noted

J

Breakdown Voltage vs Junction Temperature

10

VDD = 15V

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0369121518

Qg, GATE CHARGE (nC)

WAVEF OR MS IN DESCENDING ORDER:

ID = 7.5A

= 1A

I

D

2000

C

= CGS + C

1000

C

= C

RSS

GD

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

10

0.1 1 10

Figure 12.

VDS, DRAIN TO SOURCE VOLTAGE (V)

Capacitance vs Drain to Source

ISS

C

≅ C

OSS

DS

Voltage

60

10

1

, DRAIN CURRENT (A)

D

I

0.1

0.01

THIS AREA IS LIMITED BY r

DS(on)

SINGLE PULSE

= MAX RATED

T

J

o

= 125

θJA

A

= 25

C/W

o

C

R

T

0.01 0.1 1 10 100

VDS, DRAIN to SOURCE VOLTAGE (V)

+ C

GD

100us

100ms

30

®

MOSFET

1ms

10ms

1s

10s

DC

Figure 13.

Gate Charge Waveforms for Constant

Gate Currents

Figure 14. Forward Bias Safe Operating Area

www.fairchildsemi.com5

Test Circuits and Waveforms

FDS8978 Dual N-Channel PowerTrench

VAR Y t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

t

0V

P

Figure 15.

I

g(REF)

V

DS

L

0.01Ω

+

V

DD

-

0

R

AS

G

DUT

I

AS

Unclamped Energy Test Circuit Figure 16.

V

DS

L

V

GS

DUT

+

V

DD

-

V

DD

V

0

I

g(REF)

0

GS

= 1V

BV

DSS

t

P

I

AS

t

AV

Unclamped Energy Waveforms

Q

g(TOT)

V

DS

Q

gs2

Q

g(TH)

Q

gs

g(5)

Q

gd

V

GS

VGS = 5V

V

DS

V

DD

®

V

= 10V

GS

MOSFET

Figure 17.

V

GS

Figure 19.

Gate Charge Test Circuit Figure 18.

V

GS

R

GS

Switching Time Test Circuit Figure 20.

Gate Charge Waveforms

V

DS

R

DUT

L

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

Switching Time Waveforms

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Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, P application. Therefore the application’s ambient temperature, T must be reviewed to ensure that T Equation 1 mathematically represents the relationship and

(oC), and thermal resistance R

A

is never exceeded.

JM

DM

θJA

, in an

(oC/W)

serves as the basis for establishing the rating of the part.

P

TJMTA–()

--------------------------- ----=

DM

R

θJA

(EQ. 1)

In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of P and influenced by many factors:

is complex

DM

1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board.

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R

for the device as a function of the top copper (compo-

θJA

nent side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary in formation for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized

150

COPPER BOARD AREA - DESCENDING ORDER

2

0.04 in

2

0.28 in

120

C/W)

o

90

, THERMAL

60

θJA

Z

IMPEDANCE (

30

0.52 in

0.76 in

1.00 in

2

maximum transient

thermal impedance curve.

Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.

R

The transient thermal impedance (Z varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal imped ance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas.

Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.

-

64

θJA

200

150

C/W)

o

(

θJA

R

100

50

0.001 0.01 0.1 1 10

26

+=

-------------------------------

0.23 Area+

AREA, TOP COPPER AREA (in2)

(EQ. 2)

) is also effected by

θJA

R

= 64 + 26/(0.23+Area)

θJA

Figure 21. Thermal Resistance vs Mounting

Pad Area

FDS8978 Dual N-Channel PowerTrench

-

®

MOSFET

0

-1

10

Figure 22. Thermal Impedance vs Mounting Pad Area

0

10

t, RECTANGULAR PULSE DURATION (s)

1

10

2

10

www.fairchildsemi.com7

3

10

PSPICE Electrical Model

.SUBCKT FDS8978 2 1 3 *February 2005

Ca 12 8 7.8e-10 Cb 15 14 7.8e-10 Cin 6 8 .78e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 32.9 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1

It 8 17 1

Lgate 1 9 5.29e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 0.18e-9

RLgate 1 9 52.9 RLdrain 2 5 10 RLsource 3 7 1.8

Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1.6e-3 Rgate 9 20 2.3 RSLC1 5 51 RSLCMOD 1e-6

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

EVTEMP +

20

S1A

12

S1B

18 22

DPLCAP

10

RSLC2

6

8

EVTHRES

+

19

8

6

-

S2A

14

13

8

S2B

13

+

6

EGS EDS

8

-

15

CIN

CB

-

+

-

5

51

5

51

-

RDRAIN

21

MSTRO

14

5 8

RSLC1

+

ESLC

50

16

8

MMED

8

DBREAK

11

+

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 8.9e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))}

.MODEL DbodyMOD D (IS=2.0E-12 IKF=10 N=1.01 RS=7.0e-3 TRS1=8e-4 TRS2=2e-7 + CJO=3.5e-10 M=0.55 TT=7e-11 XTI=2) .MODEL DbreakMOD D (RS=0.2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=3.8e-10 IS=1e-30 N=10 M=0.45)

.MODEL MstroMOD NMOS (VTO=2.36 KP=150 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=1.95 KP=5.0 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.3) .MODEL MweakMOD NMOS (VTO=1.57 KP=0.02 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1)

.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7) .MODEL RdrainMOD RES (TC1=15e-3 TC2=0.1e-5) .MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=1e-3 TC2=3e-6) .MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=2e-7) .MODEL RvthresMOD RES (TC1=-2.0e-3 TC2=-6e-6) MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-1.0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.0 VOFF=-1.5).ENDSNote: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

17 18

-

7

RVTEMP

19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDS8978 Dual N-Channel PowerTrench

®

MOSFET

www.fairchildsemi.com8

SABER Electrical Model

REV February 2005 template FDS8978 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.0e-12,ikf=10,nl=1.01,rs=7.0e-3,trs1=8e-4,trs2=2e-7,cjo=3.5e-10,m=0.55,tt=7e-11,xti=2) dp..model dbreakmod = (rs=0.2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=3.8e-10,isl=10e-30,nl=10,m=0.45) m..model mstrongmod = (type=_n,vto=2.36,kp=150,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=1.95,kp=5.0,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.57,kp=0.02,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=-1.0)

10

DPLCAP

5

sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.0,voff=-1.5) c.ca n12 n8 = 7.8e-10 c.cb n15 n14 = 7.8e-10

RSLC2

c.cin n6 n8 = .78e-9

dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 32.9 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1

GATE

1

LGATE

RLGATE

RGATE

9

ESG

EVTEMP

+

18 22

20

-

+

-

6 8

EVTHRES

+

6

-

19

8

CIN

spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1

l.lgate n1 n9 = 5.29e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 0.18e-9

res.rlgate n1 n9 = 52.9 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 1.8

12

CA

S1A

14

13

8

S1B

13

+

6

EGS EDS

8

-

S2A

S2B

15

CB

+

5 8

-

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7 res.rdrain n50 n16 = 1.6e-3, tc1=15e-3,tc2=0.1e-5 res.rgate n9 n20 = 2.3 res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 8.9e-3, tc1=1e-3,tc2=3e-6 res.rvthres n22 n8 = 1, tc1=-2.0e-3,tc2=-6e-6 res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5)) } }

RSLC1

51

ISCL

50

RDRAIN

16

21

MSTRO

14

8

MMED

8

DBREAK

11

MWEAK

EBREAK

+

RSOURCE

RBREAK

17 18

IT

RVTHRES

17 18

7

+

RVTEMP

19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDS8978 Dual N-Channel PowerTrench

®

MOSFET

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SPICE Thermal Model

REV February 2005 template FDS8878 n2,n1,n3 Copper Area =1.0 in CTHERM1 TH 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 2e-1 CTHERM7 3 2 1 CTHERM8 2 TL 3

RTHERM1 TH 8 1e-1 RTHERM2 8 7 5e-1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERM8 2 TL 25

2

th

RTHERM1

8

RTHERM2

7

RTHERM3

FDS8978 Dual N-Channel PowerTrench

JUNCTION

CTHERM1

CTHERM2

CTHERM3

SABER Thermal Model

Copper Area = 1.0 in template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =2.0e-3 ctherm.ctherm2 8 7 =5.0e-3 ctherm.ctherm3 7 6 =1.0e-2 ctherm.ctherm4 6 5 =4.0e-2 ctherm.ctherm5 5 4 =9.0e-2 ctherm.ctherm6 4 3 =2e-1 ctherm.ctherm7 3 2 1 ctherm.ctherm8 2 tl 3

rtherm.rtherm1 th 8 =1e-1 rtherm.rtherm2 8 7 =5e-1 rtherm.rtherm3 7 6 =1 rtherm.rtherm4 6 5 =5 rtherm.rtherm5 5 4 =8 rtherm.rtherm6 4 3 =12 rtherm.rtherm7 3 2 =18 rtherm.rtherm8 2 tl =25 }

COMPONANT 0.04 in

2

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

TABLE 1. THERMAL MODELS

0.28 in

2

0.52 in

2

6

5

4

3

2

tl

0.76 in

CASE

2

CTHERM4

CTHERM5

CTHERM6

CTHERM7

CTHERM8

1.0 in

®

MOSFET

2

CTHERM6 1.2e-1 1.5e-1 2.0e-1 2.0e-1 2.0e-1

CTHERM7 0.5 1.0 1.0 1.0 1.0

CTHERM8 1.3 2.8 3.0 3.0 3.0

RTHERM6 26 20 15 13 12

RTHERM7 39 24 21 19 18

RTHERM8 55 38.7 31.3 29.7 25

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tm

®

tm

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The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor an d/or its globa l subsidiaries, and is not intended to be an exhaustive list of all such trademarks.

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SM

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used here in:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

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Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support Counterfeiting of semiconductor parts is a growing problem in the in dustry. All manufactures of semiconductor products are experi encing counterfeiting of their parts. Customers who inadvertently purchase counterfeit part s experi ence ma ny pr oblems such as lo ss of brand r eput ation, sub stan dard perfor mance, failed

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committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct o r from authorized distr ibutors.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative / In Design

Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any ti me without notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.

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Rev. I51