Datasheet FDS8870 Datasheet (Fairchild)

tm

FDS8870 N-Channel PowerTrench

30V, 18A, 4.2mΩ

®

MOSFET

FDS8870 N-Channel PowerTrench

April 2007

Features

 r

 High performance trench technology for extremely low

 Low gate charge

 High power and current handling capability

 RoHS Compliant

Branding Dash

DS(on)

r

DS(on)

= 4.2mΩ, V

= 4.9mΩ, V

= 10V, ID = 18A

GS

= 4.5V, ID = 17A

GS

General Description

This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low r

and fast switching speed.

DS(on)

Applications

 DC/DC converters

5

4

®

MOSFET

1

2

3

4

SO-8

5

6

7

8

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3

2

1

FDS8870 N-Channel PowerTrench

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

A

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Source Voltage 30 V

Gate to Source Voltage ±20 V

Drain Current

I

D

Continuous (TA = 25oC, VGS = 10V, R

Continuous (TA = 25oC, VGS = 4.5V, R

= 50oC/W)

θJA

= 50oC/W) 17 A

θJA

18 A

Pulsed 134 A

E

AS

P

D

TJ, T

STG

Single Pulse Avalanche Energy (Note 1) 420 mJ

Power dissipation 2.5 W

Derate above 25oC 20 mW/oC

Operating and Storage Temperature -55 to 150

Thermal Characteristics

R

θJC

R

θJA

R

θJA

Thermal Resistance, Junction to Case (Note 2) 25

Thermal Resistance, Junction to Ambient (Note 2a) 50

Thermal Resistance, Junction to Ambient (Note 2b) 125

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape W i dt h Quantity

FDS8870 FDS8870 SO-8 330mm 12mm 2500 units

Electrical Characteristics T

Symbol Parameter Test Conditions Min Typ Max Units

= 25°C unless otherwise noted

J

o

C/W

o

C/W

o

C/W

o

C

®

MOSFET

Off Characteristics

B

I

DSS

I

GSS

VDSS

Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V

Zero Gate Voltage Drain Current

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(on)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1.2 - 2.5 V

Drain to Source On Resistance

Dynamic Characteristics

C

ISS

C

OSS

C

RSS

R

G

Q

g(TOT)

Q

g(5)

Q

g(TH)

Q

gs

Q

gs2

Q

gd

Input Capacitance

Output Capacitance - 900 - pF

Reverse Transfer Capacitance - 450 - pF

Gate Resistance VGS = 0.5V, f = 1MHz 0.5 2.0 3.5 Ω

Total Gate Charge at 10V VGS = 0V to 10V

Total Gate Charge at 5V VGS = 0V to 5V - 45 62 nC

Threshold Gate Charge VGS = 0V to 1V - 4.6 6.0 nC

Gate to Source Gate Charge - 11 - nC

Gate Charge Threshold to Plateau - 6.4 - nC

Gate to Drain “Miller” Charge - 15 - nC

VDS = 24V - - 1

VGS = 0V TJ = 150oC - - 250

ID = 18A, VGS = 10V - 3.5 4.2

ID = 17A, VGS = 4.5V - 3.9 4.9

ID = 18A, VGS = 10V, TJ = 150oC

VDS = 15V, VGS = 0V,

- 5.5 7.2

- 4615 - pF

f = 1MHz

- 85 11 2 nC

VDD = 15V ID = 18A Ig = 1.0mA

µA

mΩ

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Switching Characteristics (V

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time

Turn-On Delay Time - 9 - ns

Rise Time - 48 - ns

Turn-Off Delay Time - 60 - ns

Fall Time - 21 - ns

Turn-Off Time - - 122 ns

GS

= 10V)

- - 86 ns

VDD = 15V, ID = 18A VGS = 10V, RGS = 3.3Ω

Drain-Source Diode Characteristics

I

= 18A - - 1.25 V

V

SD

t

rr

Q

RR

Notes:

1: Starting TJ = 25°C, L = 1mH, IAS = 29A, VDD = 30V, VGS = 10V. 2: R

θJA

drain pins. R

a) 50°C/W when mounted on a 1in

b) 125°C/W when mounted on a minimum pad.

Source to Drain Diode Voltage

Reverse Recovery Time ISD = 18A, dISD/dt = 100A/µs - - 37 ns

Reverse Recovered Charge ISD = 18A, dISD/dt = 100A/µs - - 22 nC

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the

is guaranteed by design while R

θJC

2

pad of 2 oz copper.

is determined by the user’s board design.

θJA

SD

ISD = 2.1A - - 1.0 V

FDS8870 N-Channel PowerTrench

®

MOSFET

www.fairchildsemi.com3

FDS8870 N-Channel PowerTrench

Typical Characteristics T

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 150

TA, AMBIENT TEMPERATURE (oC)

= 25°C unless otherwise noted

J

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

1

DUTY CYCLE-DESCENDING ORDER

D = 0.5

0.1

θJA

Z

0.01

0.2

0.1

0.05

0.02

0.01

125

20

15

VGS = 10V

R

θJA

VGS = 4.5V

=50oC/W

TA, AMBIENT TEMPERATURE (oC)

10

, DRAIN CURRENT (A)

D

I

5

0

25 50 75 100 125 150

Figure 2. Maximum Continuous Drain Current vs

Ambient Temperature

®

MOSFET

NORMALIZED THERMAL

IMPEDANCE,

0.001

0.0001

3000

1000

100

10

, PEAK TRANSIENT POWER (W)

(PK)

P

0.5

SINGLE PULSE

R

= 125oC/W

θJA

-4

10

-3

10

-2

10

t, RECTANGULAR PULSE DURATION (s)

-1

10

0

10

1

10

2

10

3

10

Figure 3. Normalized Maximum Transient Thermal Impedance

VGS = 10V

1

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

0

10

1

10

SINGLE PULSE

R

= 125oC/W

θJA

T

= 25oC

A

2

10

3

10

Figure 4. Single Pulse Maximum Power Dissipation

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FDS8870 N-Channel PowerTrench

Typical Characteristics T

100

If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

10

, AVALANCHE CURRENT (A)

AS

I

1

0.1 1 10 100

STARTING TJ = 150oC

tAV, TIME IN AVALANCHE (ms)

= 25°C unless otherwise noted

J

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 5. Unclamped Inductive Switching

Capability

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

0 0.1 0.2 0.3 0.4 0.5

VGS = 10V

TA = 25oC PULSE DURATION = 80µs

VGS = 2.5V

VDS, DRAIN TO SOURCE VOLTAGE (V)

DUTY CYCLE = 0.5% MAX

VGS = 5V

VGS = 4V

VGS = 3V

50

PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX

40

V

= 5V

DS

30

20

, DRAIN CURRENT (A)

D

10

I

0

1.5 2.0 2.5 3.0 3.5

TJ = 150oC

VGS, GATE TO SOURCE VOLTAGE (V)

TJ = 25oC

TJ = -55oC

Figure 6. Transfer Characteristics

14

ID = 15A

12

10

8

, DRAIN TO SOURCE

ON RESISTANCE (mW)

DS(on)

r

6

4

246810

VGS, GATE TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

®

MOSFET

Figure 7. Saturation Characteristics Figure 8. Drain to Source On Resistance vs Gate

1.6 PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

1.4

1.2

1.0

ON RESISTANCE

0.8

NORMALIZED DRAIN TO SOURCE

0.6

-80 -40 0 40 80 120 160

TJ, JUNCTION TEMPERATURE (oC)

Figure 9. Normalized Drain to Source On

Resistance vs Junction Temperature

VGS = 10V, ID = 15A

Voltage and Drain Current

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

-80 -40 0 40 80 120 160

TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

Figure 10. Normalized Gate Threshold Voltage vs

Junction Temperature

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FDS8870 N-Channel PowerTrench

Typical Characteristics T

1.10 ID = 250µA

1.05

1.00

0.95

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.90

-80 -40 0 40 80 120 160

TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

J

Figure 11. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 15V

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 1020304050

Qg, GATE CHARGE (nC)

WAVEFORMS IN DESCENDING ORDER:

ID = 15A ID = 1A

5000

C

= CGS + C

ISS

C

OSS

1000

C

RSS

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

100

0.1 1 10

GD

≅ C

+ C

DS

GD

= C

GD

VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 12. Capacitance vs Drain to Source

Voltage

300

100

10

THIS AREA IS

1

LIMITED BY r

, DRAIN CURRENT (A)

D

0.1

I

0.01

0.01 0.1 1 10 100

DS(on)

SINGLE PULSE

= MAX RATED

T

J

o

= 125

θJA

= 25

A

C/W

o

C

R

T

VDS, DRAIN to SOURCE VOLTAGE (V)

30

®

MOSFET

100us

1ms

10ms

100ms

1s

10s

DC

Figure 13. Gate Charge Waveforms for Constant

Gate Currents

Figure 14. Forward Bias Safe Operating Area

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Test Circuits and Waveforms

FDS8870 N-Channel PowerTrench

BV

DSS

t

P

V

DS

VAR Y tP TO OBTAIN

REQUIRED PEAK I

V

GS

V

DS

L

I

AS

R

AS

G

+

V

DD

-

DUT

t

0V

P

I

AS

0.01Ω

0

t

AV

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

I

g(REF)

DS

Λ

V

GS

+

V

DD

−

DUT

V

DD

V

0

I

g(REF)

0

GS

= 1V

Q

g(TOT)

V

DS

Q

gs2

Q

g(TH)

Q

gs

g(5)

Q

gd

V

GS

VGS = 5V

V

DD

®

MOSFET

V

= 10V

GS

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

V

GS

R

GS

V

GS

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

V

DS

R

L

+

V

DD

-

V

DS

0

DUT

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

t

d(OFF)

90%

t

OFF

t

f

90%

10%

50%

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Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, P application. Therefore the application’s ambient temperature, T must be reviewed to ensure that T Equation 1 mathematically represents the relationship and

(oC), and thermal resistance R

A

is never exceeded.

JM

DM

(oC/W)

θJA

, in an

serves as the basis for establishing the rating of the part.

P

TJMTA–()

----------------------------- --=

DM

R

θJA

(EQ. 1)

In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of P and influenced by many factors:

is complex

DM

1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board.

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R

for the device as a function of the top copper (compo-

θJA

nent side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary in formation for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized

150

COPPER BOARD AREA - DESCENDING ORDER

2

0.04 in

2

0.28 in

120

C/W)

o

90

, THERMAL

60

θJA

Z

IMPEDANCE (

30

0.52 in

0.76 in

1.00 in

2

maximum transient

thermal impedance curve.

Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.

R

The transient thermal impedance (Z varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal imped ance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas.

Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.

-

64

θJA

200

150

C/W)

o

(

θJA

R

100

50

0.001 0.01 0.1 1 10

26

+=

-------------------------------

0.23 Area+

AREA, TOP COPPER AREA (in2)

(EQ. 2)

) is also effected by

θJA

R

= 64 + 26/(0.23+Area)

θJA

Figure 21. Thermal Resistance vs Mounting

Pad Area

FDS8870 N-Channel PowerTrench

-

®

MOSFET

0

-1

10

Figure 22. Thermal Impedance vs Mounting Pad Area

0

10

t, RECTANGULAR PULSE DURATION (s)

1

10

2

10

www.fairchildsemi.com8

3

10

PSPICE Electrical Model

.SUBCKT FDS8870 2 1 3 ; rev March 2004 Ca 12 8 2.8e-9 Cb 15 14 2.8e-9 Cin 6 8 4.3e-9

Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 33.62 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1

It 8 17 1

Lgate 1 9 1e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 7e-11

RLgate 1 9 10 RLdrain 2 5 10 RLsource 3 7 0.7

Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 3.05e-3 Rgate 9 20 2 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 9e-4 Rvthres 22 8 RvthresMOD 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

EVTEMP +

20

S1A

12

S1B

18 22

DPLCAP

10

RSLC2

6

8

EVTHRES

+

19

8

6

-

S2A

13814

13

S2B

13

+

6

EGS EDS

8

-

5

RSLC1

51

+

5

ESLC

51

50

RDRAIN

16

21

-

MSTRO

CIN

15

CB

8

14

+

5 8

-

MMED

8

DBREAK

11

+

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}

.MODEL DbodyMOD D (IS=1E-11 IKF=17 N=1.01 RS=2.8e-3 TRS1=2e-3 TRS2=2e-7 + CJO=1.95e-9 M=0.55 TT=9e-11 XTI=2.6) .MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.42e-9 IS=1e-30 N=10 M=0.38)

.MODEL MmedMOD NMOS (VTO=1.85 KP=15 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2) .MODEL MstroMOD NMOS (VTO=2.2 KP=650 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=1.48 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=20 RS=0.1)

.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-9e-7) .MODEL RdrainMOD RES (TC1=1.8e-3 TC2=5e-6) .MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=8e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-1.8e-3 TC2=-9e-6) .MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=2e-7)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-5) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2)

.ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

17 18

-

7

RVTEMP

19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDS8870 N-Channel PowerTrench

®

MOSFET

www.fairchildsemi.com9

SABER Electrical Model

REV March 2004 template FDS8870 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1e-11,ikf=17,nl=1.01,rs=2.8e-3,trs1=2e-3,trs2=2e-7,cjo=1.95e-9,m=0.55,tt=9e-11,xti=2.6) dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.42e-9,isl=10e-30,nl=10,m=0.38) m..model mmedmod = (type=_n,vto=1.85,kp=15,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.2,kp=650,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.48,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5,voff=-3) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-5) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5) sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2) c.ca n12 n8 = 2.8e-9 c.cb n15 n14 = 2.8e-9 c.cin n6 n8 = 4.3e-9

dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 33.62 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1

GATE

1

spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1

LGATE

9

RLGATE

RGATE

ESG

EVTEMP

+

18 22

20

spe.evtemp n20 n6 n18 n22 = 1

DPLCAP

10

RSLC2

6

8

EVTHRES

+

6

-

5

RSLC1

51

50

RDRAIN

21

-

19

8

MSTRO

CIN

i.it n8 n17 = 1

l.lgate n1 n9 = 1e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 7e-11

res.rlgate n1 n9 = 10 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 0.7

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u

CA

S1A

12

S1B

S2A

13814

13

S2B

13

+

6

EGS EDS

8

-

15

CB

14

+

5 8

-

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-9e-7 res.rdrain n50 n16 = 3.05e-3, tc1=1.8e-3,tc2=5e-6 res.rgate n9 n20 = 2 res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 9e-4, tc1=8e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-1.8e-3,tc2=-9e-6 res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))

} }

ISCL

16

8

MMED

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

-

17 18

7

+

RVTEMP

19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDS8870 N-Channel PowerTrench

®

MOSFET

www.fairchildsemi.com10

FDS8870 N-Channel PowerTrench

SPICE Thermal Model

REV March 2004 FDS8870T Copper Area =1.0 in

2

CTHERM1 TH 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 2e-1 CTHERM7 3 2 1 CTHERM8 2 TL 3

RTHERM1 TH 8 1e-1 RTHERM2 8 7 5e-1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERM8 2 TL 25

SABER Thermal Model

Copper Area = 1.0 in template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 =2.0e-3 ctherm.ctherm2 8 7 =5.0e-3 ctherm.ctherm3 7 6 =1.0e-2 ctherm.ctherm4 6 5 =4.0e-2 ctherm.ctherm5 5 4 =9.0e-2 ctherm.ctherm6 4 3 =2e-1 ctherm.ctherm7 3 2 1 ctherm.ctherm8 2 tl 3

rtherm.rtherm1 th 8 =1e-1 rtherm.rtherm2 8 7 =5e-1 rtherm.rtherm3 7 6 =1 rtherm.rtherm4 6 5 =5 rtherm.rtherm5 5 4 =8 rtherm.rtherm6 4 3 =12 rtherm.rtherm7 3 2 =18 rtherm.rtherm8 2 tl =25 }

2

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

JUNCTION

th

CTHERM1

8

CTHERM2

7

CTHERM3

6

CTHERM4

5

CTHERM5

4

CTHERM6

3

CTHERM7

2

CTHERM8

®

MOSFET

tl

CASE

TABLE 1. THERMAL MODELS

COMPONANT 0.04 in

2

0.28 in

2

0.52 in

2

0.76 in

2

CTHERM6 1.2e-1 1.5e-1 2.0e-1 2.0e-1 2.0e-1

CTHERM7 0.5 1.0 1.0 1.0 1.0

CTHERM8 1.3 2.8 3.0 3.0 3.0

RTHERM6 26 20 15 13 12

RTHERM7 39 24 21 19 18

RTHERM8 55 38.7 31.3 29.7 25

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FDS8870 N-Channel PowerTrench

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As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

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Datasheet Identification

Advance Information

Product Status

Formative or In Design

Preliminary First Production This datasheet contains preliminary data; supplementary data will

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete

Not In Production

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Definition

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

Semiconductor reserves the right to make changes at any time without notice to improve design.

This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor.The datasheet is printed for reference information only.

Rev. I 26

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