Page 1
February 2010
FDS6898AZ_F085
Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET
tm
FDS
6898AZ_F085 Dual N-Channel Logic Level PWM Optimized PowerTrench
General Description
These N-Channel Logic Level MOSFETs are produced
using Fairchild Semiconductor’s advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
D1
D
D1
D
D2
D
D2
D
S2
G1
G
S1
S
G2
S
S
=25oC unless otherwise noted
A
SO-8
SO-8
Pin 1
Absolute Maximum Ratings T
Features
• 9.4 A, 20 V R
• Low gate charge (16 nC typical)
• ESD protection diode (note 3)
• High performance trench technology for extremely
low R
DS(ON)
• High power and current handling capability
• Qualified to AEC Q101
• RoHS Compliant
DS(ON)
R
DS(ON)
Q1
Q2
= 14 mΩ @ V
= 18 mΩ @ V
45
36
27
18
= 4.5 V
GS
= 2.5 V
GS
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
TJ, T
STG
Drain-Source Voltage 20 V
Gate-Source Voltage ± 12 V
Drain Current – Continuous (Note 1a) 9.4 A
– Pulsed 38
Power Dissipation for Dual Operation 2
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b)
(Note 1c)
Operating and Storage Junction Temperature Range –55 to +150 °C
1
0.9
W
®
MOSFET
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS6898AZ FDS6898AZ_F085 13’’ 12mm 2500 units
©2010 Fairchild Semiconductor Corporation
FDS
6898AZ_F085 Rev. A
www.fairchildsemi.com1
Page 2
FDS6898AZ_F085
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
∆BVDSS
∆T
I
DSS
I
GSSF
I
GSSR
Drain–Source Breakdown Voltage VGS = 0 V, I
Breakdown Voltage Temperature
Coefficient
J
I
= 250 µA, Referenced to 25°C
D
= 250 µA 20 V
D
Zero Gate Voltage Drain Current VDS = 16 V, VGS = 0 V 1
Gate–Body Leakage, Forward VGS = 12 V, VDS = 0 V 10
Gate–Body Leakage, Reverse VGS = –12 V, VDS = 0 V –10
21
mV/°C
On Characteristics (Note 2)
V
GS(th)
∆VGS(th)
∆T
R
DS(on)
I
D(on)
g
FS
Gate Threshold Voltage VDS = VGS, I
Gate Threshold Voltage
Temperature Coefficient
J
Static Drain–Source
On–Resistance
I
= 250 µA, Referenced to 25°C
D
VGS = 4.5 V, ID = 9.4 A
VGS = 2.5 V, ID = 8.3 A
VGS = 4.5 V, ID = 9.4 A,T
= 250 µA 0.5 1 1.5 V
D
–3.5
10
13
= 125°C
J
14
On–State Drain Current VGS = 4.5V, VDS = 5 V 19 A
Forward Transconductance VDS = 5 V, ID = 9.4 A 47 S
mV/°C
14
18
21
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance 1821 pF
Output Capacitance 440 pF
Reverse Transfer Capacitance
VDS = 10 V, V
f = 1.0 MHz
GS
= 0 V,
208 pF
Switching Characteristics (Note 2)
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
g
gs
gd
Turn–On Delay Time 10 20 ns
Turn–On Rise Time 15 27 ns
VDD = 10 V, ID = 1 A,
VGS = 4.5 V, R
GEN
= 6 Ω
Turn–Off Delay Time 34 55 ns
Turn–Off Fall Time
Total Gate Charge 16 23 nC
Gate–Source Charge 3 nC
VDS = 10 V, ID = 9.4 A,
VGS = 4.5 V
Gate–Drain Charge
16 29 ns
4 nC
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
Maximum Continuous Drain–Source Diode Forward Current 1.3 A
Drain–Source Diode Forward
VGS = 0 V, IS = 1.3 A (Note 2) 0.7 1.2 V
Voltage
is guaranteed by design while R
θJC
is determined by the user's board design.
θCA
µA
µA
µA
mΩ
Dual N-Channel Logic Level PWM Optimized PowerTrench
®
MOSFET
a) 78°C/W when
mounted on a 0.5in
pad of 2 oz copper
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied
FDS6898AZ_F085 Rev. A www.fairchildsemi.com2
2
b) 125°C/W when
mounted on a 0.02
in2 pad of 2 oz
copper
c) 135°C/W when mounted on a
minimum mounting pad.
Page 3
Typical Characteristics
40
VGS = 4.5V
30
20
, DRAIN CURRENT (A)
10
D
I
0
0 0.5 1 1.5 2
3.0V
2.5V
2.0V
VDS, DRAIN-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
2.2
2
VGS = 2.0V
1.8
1.6
1.4
, NORMALIZED
1.2
DS(ON)
R
1
DRAIN-SOURCE ON-RESISTANCE
0.8
0 10 20 30 40
2.5V
3.0V
ID, DRAIN CURRENT (A)
Drain Current and Gate Voltage.
4.0V
4.5V
FDS6898AZ_F085
Dual N-Channel Logic Level PWM Optimized PowerTrench
1.6
ID = 9.4A
VGS = 4.5V
1.4
1.2
, NORMALIZED
1
DS(ON)
R
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
-50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. On-Resistance Variation with
Temperature.
40
VDS = 5V
30
20
, DRAIN CURRENT (A)
10
D
I
0
0.5 1 1.5 2 2.5
VGS, GATE TO SOURCE VOLTAGE (V)
TA = -55oC
125oC
25oC
0.038
0.03
0.022
, ON-RESISTANCE (OHM)
0.014
DS(ON)
R
0.006
1 2 3 4 5
TA = 25oC
VGS, GATE TO SOURCE VOLTAGE (V)
TA = 125oC
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
100
VGS = 0V
10
1
0.1
0.01
0.001
, REVERSE DRAIN CURRENT (A)
S
I
0.0001
0 0.2 0.4 0.6 0.8 1 1.2
TA = 125oC
25oC
-55oC
VSD, BODY DIODE FORWARD VOLTAGE (V)
ID = 4.7A
®
MOSFET
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation
FDS6898AZ_F085 Rev. A www.fairchildsemi.com3
with Source Current and Temperature.
Page 4
Typical Characteristics
FDS6898AZ_F085
10
ID = 9.4A
8
6
4
2
, GATE-SOURCE VOLTAGE (V)
GS
V
0
0 5 10 15 20 25 30 35
Qg, GATE CHARGE (nC)
VDS = 5V
15V
10V
2500
2000
1500
1000
CAPACITANCE (pF)
500
0
C
OSS
C
RSS
0 5 10 15 20
VDS, DRAIN TO SOURCE VOLTAGE (V)
C
ISS
Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.
100
1s
10ms
100ms
100µs
1ms
R
LIMIT
DS(ON)
10
1
VGS = 10V
, DRAIN CURRENT (A)
D
I
SINGLE PULSE
0.1
R
= 135oC/W
θJA
TA = 25oC
0.01
0.01 0.1 1 10 100
VDS, DRAIN-SOURCE VOLTAGE (V)
10s
DC
40
30
20
10
P(pk), PEAK TRANSIENT POWER (W)
0
0.001 0.01 0.1 1 10 100
t1, TIME (sec)
f = 1MHz
VGS = 0 V
SINGLE PULSE
R
=135°C/W
θJA
TA = 25°C
Dual N-Channel Logic Level PWM Optimized PowerTrench
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
0.2
0.1
0.01
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
0.001
0.1
0.05
0.02
0.01
SINGLE PULSE
0.0001 0.001 0.01 0.1 1 10 100 1000
t , TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
FDS6898AZ_F085 Rev. A www.fairchildsemi.com4
R
(t) = r(t) * R
θJA
R
= 135 °C/W
θ
JA
P(pk)
t
1
t
2
TJ - TA = P * R
Duty Cycle, D = t1 / t
θJA
θJA
®
(t)
2
MOSFET
Page 5
FDS6898AZ_F085
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
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THEREIN, WHICH COVERS THESE PRODUCTS.
Dual N-Channel Logic Level PWM Optimized PowerTrench
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain life,
and (c) whose failure to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
expected to result in a significant injury of the user.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
.
Datasheet Identification Product Status Definition
Advance Information Formative / In Design
Preliminary First Production
No Identification Needed Full Production
Obsolete Not In Production
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Datasheet contains preliminary data; supplementary dat a will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time withou t
notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
FDS6898AZ_F085 Rev. A www.fairchildsemi.com5
®
MOSFET
Rev. I47
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