Page 1
FDS6685
P-Channel Logic Level PowerTrenchTM MOSFET
FDS6685
March 1999
PRELIMINARY
General Description
This P-Channel Logic Level MOSFET is produced using
Fairchild Semiconductor's advanced PowerTrench process
that has been especially tailored to minimize on-state
resistance and yet maintain superior switching
performance.
These devices are well suited for low voltage and battery
powered applications where low in-line power loss and
fast switching are required.
Applications
• Battery protection
• Load switch
• Motor drives
D
D
D
D
G
S
SO-8
Absolute Maximum Ratings
S
S
TA = 25°C unless otherwise noted
Features
• -8.8 A, -30 V. R
R
• Extended V
GSS
= 0.020 Ω @ V
DS(ON)
= 0.035 Ω @ V
DS(ON)
range (±25V) for battery applications.
= -10 V
GS
= -4.5 V
GS
• Low gate charge (19nC typical).
• Fast switching speed.
• High performance trench technology for extremely
low R
DS(ON)
.
• High power and current handling capability.
5
6
7
8
4
3
2
1
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
TJ, T
stg
Drain-Source Voltage -30 V
Gate-Source Voltage
Drain Current - Continuous
- Pulsed -50
Power Dissipation for Single Operation
Operating and Stora ge Junction Temperature Range -55 to +150
(Note 1a)
(Note 1a)
(Note 1b)
(Note 1c)
25
±
-8.8 A
2.5 W
1.2
1
Thermal Characteristics
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Ther mal Resista nce, Junction -to-Ca se
(Note 1a)
(Note 1)
50
25
Package Outlines and Ordering Information
Device Marki ng Device Reel Size Tape Width Quantity
FDS6685 FDS6685 13’’ 12mm 2500 units
1999 Fairchild Semiconductor Corporation
V
C
°
C/W
°
C/W
°
FDS6685 Rev. B
Page 2
FDS6685
Electrical Characteristics
TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteri stics
BV
∆
∆
I
I
I
DSS
BV
T
DSS
GSSF
GSSR
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature
DSS
Coefficient
J
Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V -1
Gate-Body Leakage Current, Forward VGS = 25 V, VDS = 0 V 100 nA
Gate-Body Leakage Current, Reverse VGS = -25 V, VDS = 0 V -100 nA
On Characteri st ics
V
∆
∆
R
I
g
GS(th)
V
DS(on)
D(on)
FS
GS(th)
T
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
J
Static Drain-Source
On-Resistance
On-State Drain Current VGS = -10 V, VDS = -5 V -25 A
Forward Transconductance VDS = -10 V, ID = -8.8 A 20 S
(Note 2)
= 0 V, ID = -250 µA
V
GS
I
= -250 µA,Reference d to 25°C
D
V
= VGS, ID = -250 µA
DS
I
= -250 µA,Reference d to 25°C
D
VGS = -10 V, ID = -8.8 A
V
= -10 V, ID = -8.8 A,TJ=125°C
GS
V
= -4.5 V, ID = -6.7 A
GS
-30 V
-24
mV/°C
µ
-1 -2 -3 V
5
0.015
0.023
0.026
mV/°C
0.020
0.032
0.035
A
Ω
Dynamic Characteri st ics
C
iss
C
oss
C
rss
Input Capacitance 1680 pF
Output Capacitance 545 pF
Reverse Transfer Capacitance
Switch ing Charact eristics
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
g
gs
gd
Turn-On Delay Time 12 22 ns
Turn-On Rise Time 15 27 ns
Turn-Off Delay Time 55 90 ns
Turn-Off Fall Time
Total Gate Charge 19 27 nC
Gate-Source Charge 6.8 nC
Gate -Drain Charge
(Note 2)
V
= -15 V, VGS = 0 V,
DS
f = 1.0 MHz
V
= -15 V, ID = -1 A,
DD
V
= -10 V, R
GS
V
= -10 V, ID = -8.8 A,
DS
V
= -5 V,
GS
GEN
= 6
220 pF
Ω
23 37 ns
7.2 nC
Drain-Source Diode Charact eristics and M aximum Ratin gs
I
S
V
SD
Notes:
1: R
θJA
drain pins. R
Scale 1 : 1 on letter size paper
2: Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Maximum Continuous Drain-Source Diode Forward Current -2.1 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = -2.1 A
is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface of the
is guaranteed by design while R
θJC
a) 50° C/W when
is determined by the user's board design.
θJA
mounted on a 1 in
pad of 2 oz. copper.
2
b) 105° C/W when
mounted on a 0.04 in
pad of 2 oz. copper.
(Note 2)
2
-0.52 -1.2 V
c) 125° C/W on a minimum
mounting pad of 2 oz. copper.
FDS6685 Rev. B
Page 3
T ypical Characteristics
FDS6685
50
VGS = -10V
-7.0V
40
30
20
, DRAIN CURRENT (A)
D
-I
10
0
012345
-6.0V
-5.0V
-4.5V
, DRAIN-SOURCE VOLTAGE (V)
-V
DS
-4.0V
-3.5V
2.6
2.4
VGS = -4.0V
2.2
2
1.8
1.6
, NORMALIZED
1.4
DS(ON)
R
1.2
1
DRAIN-SOURCE ON-RESISTANCE
0.8
0 1020304050
-4.5V
-5.0V
, DIRAIN CURRENT (A)
-I
D
-6.0V
Figure 1. On-Region Characteristics Figure 2. On-Resistance V ariation
with Drain Current and Gate V oltage
1.6
ID = -8.8A
= -10V
V
GS
1.4
1.2
, NORMALIZED
1
DS(ON)
R
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
-50 -25 0 25 50 75 100 125 150
T
, JUNCTION TEMPERATURE (oC)
J
0.06
0.05
0.04
0.03
0.02
, ON-RESISTANCE (OHM)
DS(ON)
0.01
R
0
345678910
-V
, GATE TO SOURCE VOLTAGE (V)
GS
TA = 125oC
-7.0V
TA = 25oC
-8.0V
-10V
ID = -4.4A
Figure 3. On-Resistance Variation
with Temperature
50
VDS = -5V
40
30
20
, DRAIN CURRENT (A)
D
-I
10
0
123456
, GATE TO SO U RCE VOLTAGE (V)
-V
GS
TA = -55oC
25oC
125oC
Figure 4. On-Resistance Variation
with Gate-to-Source V oltage
100
VGS = 0V
10
1
0.1
0.01
0.001
, REVERSE DRAIN CURRENT (A)
S
-I
0.0001
0 0.2 0.4 0.6 0.8 1 1.2 1.4
TA = 125oC
25oC
-55oC
BODY DIODE FORWARD VOLTAGE (V)
-V
SD,
Figure 5. Transfer Characteristics Figure 6. Body Diode Forward V oltage
Variation with Source Current
and Temperature
FDS6685 Rev. B
Page 4
Typical Characteristics (continued)
)
FDS6685
10
ID = -8.8A
8
VDS = -5V
-15V
6
4
2
, GATE-SOURCE VOLTAGE (V)
GS
-V
0
0 5 10 15 20 25 30 35
Q
, GATE CHARGE (nC)
g
Figure 7. Gate-Charge Characteristics
100
R
LIMIT
DS(ON)
10
1
VGS = -10V
SINGLE PULSE
, DRAIN CURRENT (A)
D
0.1
-I
0.01
= 125oC/W
R
JA
θ
= 25oC
T
A
0.1 1 10 100
, DRAIN-SOURCE VOLTAGE (V)
-V
DS
1s
10s
DC
100µs
1ms
10ms
100ms
-10V
2500
2000
1500
C
ISS
f = 1 MHz
V
GS
1000
CAPACITANCE (pF)
500
0
0 5 10 15 20 25 30
-V
, DRAIN TO SOURCE VOLTAGE (V)
DS
C
OSS
C
RSS
Figure 8. Capacitance Characteristics
50
40
30
20
POWER (W)
10
0
0.001 0.01 0.1 1 10 100 1000
SINGLE PULSE TIME (SEC)
SINGLE PULSE
R
= 125oC/W
JA
θ
T
= 25oC
A
= 0 V
Figure 9. Maximum Safe Operating Area Figure 10. Single Pulse Maximum
Power Dissipation
1
D = 0.5
0.5
0.2
0.2
0.1
0. 0 5
0. 0 2
0. 0 1
0.005
r(t), NORMALIZED EFFECTIVE
0.002
TR ANSI ENT TH ER MAL RES I ST A NC E
0.001
0.0001 0.001 0.01 0.1 1 10 100 300
0. 1
0.05
0.02
0. 0 1
S i n g l e P u l s e
t , TI ME (s e c)
1
R (t) = r(t) * R
JA
θ
R = 12 5°C/ W
JA
θ
P(pk
t
1
t
2
T - T = P * R (t)
J
D u t y C y c l e, D = t /t
JA
θ
A
JA
θ
2
1
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient themal response will change depending on the circuit board design.
FDS6685 Rev. B
Page 5
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging
Configuration: Figure 1.0
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC
ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS
TNR DATE
PT NUMBER
PEEL STRENGTH MIN ______________gms
Customized
Label
Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Reel Size
Box Dimension (mm)
Max qty per Box
Weight per unit (gm)
Weight per Reel (kg)
Note/Comments
MAX _____________ gms
ESD Label
SOIC (8lds) Packaging Information
Standard
(no flow code)
2,500 95 4,000
13" Dia
343x64x343 530x130x83 343x64x343
5,000 30,000 8,000
0.0774 0.0774 0.0774 0.0774
0.6060 - 0.9696 0.1182
TNR
L86Z F011
Rail/Tube-TNR
13" Dia
Embossed Car rier Tape
Antistatic Cover Tape
Static Dissipative
F63TNR
Label
D84Z
TNR
500
7" Dia
184x18 7x47
1,000
F
NDS
9959
9959
852
SOIC-8 Unit Orientation
343mm x 342mm x 64mm
Stand a r d In t e rm ed iate bo x
Packaging Description:
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped w ith
2,500 uni t s pe r 13" o r 33 0c m d ia met er reel . Th e reel s ar e
dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or
177cm di ameter reel. This and some o ther options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in di ff ere nt siz es depe nd in g on th e num be r of pa rts
shippe d.
F
NDS
9959
F
NDS
9959
F
NDS
852
852
852
F
NDS
9959
852
Pin 1
F63TNR Label sample
LOT: CBVK741B019
FSID: FDS9953A
D/C1: D9842 QTY1: SPEC REV:
D/C2: QTY2: CPN:
QTY: 2500
SPEC:
N/F: F (F63TNR)3
SOIC(8lds) Tape Leader and Trailer
Configuration: Figure 2.0
Carrier Tape
Cover Tape
Trailer Tape
640mm minimum or
80 empty pockets
F63TNLab el
ESD Label
Components
ESD Label
F63TNLabel
Leader Tape
1680mm minimum or
210 empty pockets
July 1999, Rev. B
Page 6
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0
T
K0
Wc
B0
P0
D0
E1
F
W
E2
Tc
A0
D1
P1
User Direction of Feed
Dimensions are in millimeter
Pkg type
SOIC
(12mm)
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
SOIC(8lds) Reel Configuration: Figure 4.0
A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc
(8lds)
6.50
5.30
12.0
1.55
1.60
1.75
10.25
+/-0.10
+/-0.10
+/-0.3
+/-0.05
+/-0.10
+/-0.10
rotational and lateral movement requirements (see sketches A, B, and C).
B0
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
5.50
min
+/-0.05
20 deg maximum
A0
Sketch B (Top View)
Component Rotation
W1 Measured at Hub
8.0
+/-0.1
Typical
component
cavity
center line
Typical
component
center line
Dim A
Max
4.0
+/-0.1
0.450
2.1
+/-0.10
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
+/-
0.150
9.2
+/-0.3
0.5mm
maximum
0.06
+/-0.02
Dim A
max
Tape Size
12mm 7" Dia
12mm 13" Dia
1998 Fairchild Semiconductor Corporation
Reel
Option
Dim N
Diameter Option
7"
See detail AA
B Min
Dim C
13" Diameter Option
See detail AA
W2 max Measured at Hub
Dim D
W3
min
DETAIL AA
Dimensions are in inches and millimeters
Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
7.00
0.059
177.8
13.00
330
1.5
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
512 +0.020/-0.008
13 +0.5/-0.2
0.795
2.165550.488 +0.078/-0.000
20.2
0.795
7.00
20.2
178
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.724
18.4
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
July 1999, Rev. B
Page 7
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1 : 1
Scale 1:1 on letter size paper
Dimensions show n below are in:
inches [m illimet ers]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A
Page 8
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
CROSSVOLT™
2
E
CMOS
TM
FACT™
FACT Quiet Series™
®
FAST
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
TinyLogic™
UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STA TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or
In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
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