Datasheet FDS6680 Datasheet (Fairchild Semiconductor)

Page 1
April 1998
FDS6680 Single N-Channel Logic Level PWM Optimized PowerTrenchTM MOSFET
This N-Channel Logic Level MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers.
The MOSFET features faster switching and lower gate charge than other MOSFETs with comparable R specifications.
The result is a MOSFET that is easy and safer to drive (even at very high frequencies), and DC/DC power supply designs with higher overall efficiency.
DS(ON)
11.5 A, 30 V. R R
= 0.010 Ω @ VGS = 10 V
DS(ON)
= 0.015 Ω @ VGS = 4.5 V.
DS(ON)
Optimized for use in switching DC/DC converters with PWM controllers.
Very fast switching. Low gate charge (typical Qg = 19 nC).
SOT-23
SuperSOTTM-8
SO-8 SOT-223SuperSOTTM-6
5
6
7 8
Absolute Maximum Ratings T
Symbol Parameter FDS6680 Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V Gate-Source Voltage ±20 V Drain Current - Continuous (Note 1a) 11.5 A
= 25oC unless other wise noted
A
SOIC-16
4
3 2
1
- Pulsed 50
P
D
Power Dissipation for Single Operation (Note 1a) 2.5 W (Note 1b) 1.2
(Note 1c) 1
TJ,T
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
Operating and Storage Temperature Range -55 to 150 °C
STG
Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W Thermal Resistance, Junction-to-Case (Note 1) 25 °C/W
© 1998 Fairchild Semiconductor Corporation
FDS6680 Rev.E1
Page 2
Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS
BV
∆BV
I
DSS
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, I D = 250 µA 30 V Breakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC 23 mV/ oC
/∆T
J
Zero Gate Voltage Drain Current VDS = 24 V, V
= 0 V 1 µA
GS
TJ = 55°C 10 µA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA
ON CHARACTERISTICS (Note 2)
V
∆V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.7 3 V Gate Threshold Voltage Temp.Coefficient ID = 250 µA, Referenced to 25 oC -5 mV/oC
/∆T
J
Static Drain-Source On-Resistance VGS = 10 V, ID = 11.5 A 0.0085 0.01
TJ =125°C 0.014 0.017
VGS = 4.5 V, ID = 9.5 A 0.0125 0.015
I
D(ON)
g
FS
On-State Drain Current VGS = 10 V, VDS = 5 V 50 A Forward Transconductance VDS = 15 V, ID = 11.5 A 40 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 15 V, VGS = 0 V, Output Capacitance 510 pF
f = 1.0 MHz
2070 pF
Reverse Transfer Capacitance 235 pF
SWITCHING CHARACTERISTICS (Note 2)
t t
t t Q Q Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDS= 15 V, I D = 1 A 13 21 ns Turn - On Rise Time
VGS = 10 V , R
GEN
= 6 Ω
10 18 ns
Turn - Off Delay Time 36 58 ns Turn - Off Fall Time 13 23 ns Total Gate Charge VDS = 15 V, ID = 11.5 A, 19 27 nC Gate-Source Charge V
= 5 V 7 nC
GS
Gate-Drain Charge 6 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
design while R
Maximum Continuous Drain-Source Diode Forward Current 2.1 A Drain-Source Diode Forward Voltage VGS = 0 V, IS = 2.1 A
is determined by the user's board design.
CA
θ
(Note 2) 1.2 V
Ω
is guaranteed by
JC
θ
a. 50OC/W on a 1 in2 pad
of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
b. 105OC/W on a 0.04 in
pad of 2oz copper.
2
c. 125OC/W on a 0.006 in2 pad
of 2oz copper.
FDS6680 Rev.E1
Page 3
Typical Electrical Characteristics
50
V = 10V
GS
6.0
40
5.0
30
20
10
D
I , DRAIN-SOURCE CURRENT (A)
0
0 0.5 1 1.5 2 2.5
4.5
4.0
3.5
V , DRAIN-SOURCE VOLTAGE (V)
DS
3.0
Figure 1. On-Region Characteristics.
1.8
I = 11.5A
D
V =10V
GS
1.6
1.4
1.2
1
DS(ON)
R , NORMALIZED
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)
J
2.5
1.5
DS(ON)
R , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
0.5
) OHM
DS(ON)
R ,(
3
V = 3.5V
GS
2
4.0
4.5
5.0
6.0
1
0 10 20 30 40 50
I , DRAIN CURRENT (A)
D
10
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.04
0.03
0.02
0.01
DRAIN-SOURCE ON-RESISTANCE
0
2 4 6 8 10
T = 25 C
A
V ,GATE-SOURCE VOLTAGE (V)
GS
T = 125 C
A
o
o
I = 11.5A
D
Figure 3. On-Resistance Variation with
Temperature.
50
V = 10V
DS
40
30
20
D
I , DRAIN CURRENT (A)
10
0
0 1 2 3 4 5
V , GATE TO SOURCE VOLTAGE (V)
GS
Figure 5. Transfer Characteristics.
T = -55°C
J
125°C
25°C
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
50
V =0V
GS
10
T = 125°C
1
0.1
0.01
0.001
S
I , REVERSE DRAIN CURRENT (A)
0.0001
0.2 0.4 0.6 0.8 1 1.2
J
25°C
-55°C
V , BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 6. Body Diode Forward Voltage
Variation with Source Current and Temperature.
FDS6680 Rev.E1
Page 4
Typical Electrical And Thermal Characteristics
10
I = 11.5A
D
8
6
4
2
GS
V , GATE-SOURCE VOLTAGE (V)
0
0 10 20 30 40
Q , GATE CHARGE (nC)
g
V = 10V
DS
20V
Figure 7. Gate Charge Characteristics.
100
50
RDS(ON) LIMIT
20 10
3 1
V = 10V
GS
SINGLE PULSE
0.1
D
I , DRAIN CURRENT (A)
R = See Note 1c
JA
θ
T = 25°C
0.01
0.1 0.2 0.5 1 2 5 10 30 50
A
V , DRAIN-SOURCE VOLTAGE (V)
DS
DC
100us
1ms
10ms
100ms
1s
10s
15V
3000 2000
1000
500
CAPACITANCE (pF)
200
100
f = 1 MHz V = 0V
GS
0.1 0.2 0.5 1 2 5 10 20 30 V , DRAIN TO SOURCE VOLTAGE (V)
DS
C
C
C
iss
oss
rss
Figure 8. Capacitance Characteristics.
50
SINGLE PULSE
40
30
20
POWER (W)
10
0
0.001 0.01 0.1 1 10 100 300 SINGLE PULSE TIME (SEC)
R =See Note 1c
JA
θ
T = 25°C
A
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
1
D = 0.5
0.5
0.2
0.1
0.05
0.02
0.01
0.005
r(t), NORMALIZED EFFECTIVE
0.002
TRANSIENT THERMAL RESISTANCE
0.001
0.2
0.1
0.05
0.02
0.01 Single Pulse
0.0001 0.001 0.01 0.1 1 10 100 300 t , TIME (sec)
1
R (t) = r(t) * R
JA
θ
R =See Note 1c
JA
θ
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t /t
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design.
JA
θ
JA
θ
1
2
FDS6680 Rev.E1
Page 5
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging Configuration: Figure 1.0
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS
TNR DATE PT NUMBER PEEL STRENGTH MIN ______________gms
Customized Label
Packaging Option Packaging type
Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg)
Note/Comments
MAX _____________ gms
ESD Label
SOIC (8lds) Packaging Information
Standard
(no flow code)
2,500 95 4,000
13" Dia
343x64x343 530x130x83 343x64x343
5,000 30,000 8,000
0.0774 0.0774 0.0774 0.0774
0.6060 - 0.9696 0.1182
TNR
L86Z F011
Rail/Tube-TNR
13" Dia
Embossed Car rier Tape
Antistatic Cover Tape
Static Dissipative
F63TNR Label
D84Z
TNR
500
7" Dia
184x18 7x47
1,000
F
NDS
9959
9959
852
SOIC-8 Unit Orientation
343mm x 342mm x 64mm
Stand a r d In t e rm ed iate box
Packaging Description:
SOIC-8 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 2,500 uni t s pe r 13" o r 33 0c m d ia met er reel . Th e reel s ar e dark blue in color and is made of polystyrene plastic (anti­static coated). Other option comes in 500 units per 7" or 177cm di ameter reel. This and some o ther options are further described in the Packaging Information table.
These full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. One box contains two reels maximum. And these boxes are placed inside a barcode labeled shipping box which comes in di ff ere nt siz es depe nd in g on th e num be r of pa rts shippe d.
F
NDS
9959
F
NDS
9959
F
NDS
852
852
852
F
NDS 9959
852
Pin 1
F63TNR Label sample
LOT: CBVK741B019
FSID: FDS9953A
D/C1: D9842 QTY1: SPEC REV: D/C2: QTY2: CPN:
QTY: 2500
SPEC:
N/F: F (F63TNR)3
SOIC(8lds) Tape Leader and Trailer Configuration: Figure 2.0
Carrier Tape
Cover Tape
Trailer Tape 640mm minimum or 80 empty pockets
F63TNLab el
ESD Label
Components
ESD Label
F63TNLabel
Leader Tape 1680mm minimum or 210 empty pockets
July 1999, Rev. B
Page 6
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape Configuration: Figure 3.0
T
K0
Wc
B0
P0
D0
E1
F
W
E2
Tc
A0
P1
D1
User Direction of Feed
Dimensions are in millimeter
Pkg type
(8lds)
SOIC
(12mm)
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
SOIC(8lds) Reel Configuration: Figure 4.0
A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc
6.50
5.30
12.0
1.55
1.60
1.75
10.25
+/-0.10
+/-0.10
+/-0.3
+/-0.05
+/-0.10
+/-0.10
rotational and lateral movement requirements (see sketches A, B, and C).
B0
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
5.50
min
+/-0.05
20 deg maximum
A0
Sketch B (Top View)
Component Rotation
W1 Measured at Hub
8.0 +/-0.1
Typical component cavity center line
Typical component center line
Dim A
Max
4.0 +/-0.1
0.450
2.1 +/-0.10
0.5mm maximum
Sketch C (Top View)
Component lateral movement
+/-
0.150
9.2 +/-0.3
0.5mm maximum
0.06 +/-0.02
Dim A
max
Tape Size
12mm 7" Dia
12mm 13" Dia
1998 Fairchild Semiconductor Corporation
Reel
Option
Dim N
Diameter Option
7"
See detail AA
B Min
Dim C
13" Diameter Option
See detail AA
W2 max Measured at Hub
Dim D
W3
min
DETAIL AA
Dimensions are in inches and millimeters
Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
7.00
0.059
177.8
13.00 330
1.5
0.059
1.5
512 +0.020/-0.008 13 +0.5/-0.2
512 +0.020/-0.008 13 +0.5/-0.2
0.795
2.165550.488 +0.078/-0.000
20.2
0.795
7.00
20.2
178
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.724
18.4
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
July 1999, Rev. B
Page 7
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1 : 1
Scale 1:1 on letter size paper
Dimensions s hown bel ow are in:
inches [millimeters]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A
Page 8
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ CoolFET™ CROSSVOLT™
2
E
CMOS
TM
FACT™ FACT Quiet Series™
®
FAST FASTr™ GTO™ HiSeC™
ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QFET™ QS™
Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8
TinyLogic™ UHC™ VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
PRODUCT STA TUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
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