Datasheet FDS5672 Datasheet (Fairchild)

FDS5672
N-Channel PowerTrench® MOSFET

60V, 12A, 10mΩ

FDS5672 N-Channel PowerTrench

July 2005

Features

 r
 r
 High performance trench technology for extremely low

r

 Low gate charge
 High power and current handling capability

DS(ON)

DS(ON)

DS(ON)

= 10mΩ, V
= 14mΩ, V

= 10V, ID = 12A

GS

= 6V, ID = 10A

GS

Applications

 DC/DC converters

General Description

This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
r

and fast switching speed.

DS(ON)

®

MOSFET

Branding Dash

1

2

3

4

©2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A

SO-8

5

5

6

7

8

1

4

3

2

1

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FDS5672 N-Channel PowerTrench

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

C

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Source Voltage 60 V
Gate to Source Voltage ±20 V
Drain Current

I

D

Continuous (TC = 25 oC, VGS = 10V, R
Continuous (TC = 25 oC, VGS = 6V, R

= 50oC/W)

θJA

= 50oC/W) 10

θJA

12 A

Pulsed Figure 4 A

E

AS

P

D

TJ, T

STG

Single Pulse Avalanche Energy (Note 1) 245 mJ
Power dissipation 2.5 W
Derate above 25oC 20 mW/oC
Operating and Storage Temperature -55 to 150

Thermal Characteristics

R

θJC

R

θJA

R

θJA

Thermal Resistance Junction to Case (Note 2) 25
Thermal Resistance Junction to Ambient at 10 seconds (Note 3) 50
Thermal Resistance Junction to Ambient at 1000 seconds (Note 3) 85

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDS5672 FDS5672 SO-8 330mm 12mm 2500 units

Electrical Characteristics T

Symbol Parameter Test Conditions Min Typ Max Units

= 25°C unless otherwise noted

C

o

C/W

o

C/W

o

C/W

o

C

®

MOSFET

Off Characteristics

B
I

DSS

I

GSS

VDSS

Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 60 - - V
Zero Gate Voltage Drain Current
Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 2 - 4 V

Drain to Source On Resistance

Dynamic Characteristics

C
C
C
R
Q
Q
Q
Q
Q

ISS
OSS
RSS
G

g(TOT)
g(TH)
gs
gs2
gd

Input Capacitance
Output Capacitance - 410 - pF
Reverse Transfer Capacitance - 130 - pF
Gate Resistance VGS = 0.5V, f = 1MHz - 1.4 - Ω
Total Gate Charge at 10V VGS = 0V to 10V
Threshold Gate Charge VGS = 0V to 2V - 4.2 5.5 nC
Gate to Source Gate Charge - 9.4 - nC
Gate Charge Threshold to Plateau - 5.2 - nC
Gate to Drain “Miller” Charge - 9.3 - nC

VDS = 50V - - 1
VGS = 0V TC = 150oC - - 250

ID = 12A, V

= 10V - 0.0088 0.010

GS

ID = 10A, VGS = 6V, - 0.012 0.014
ID = 12A, V

T

= 150oC

C

VDS = 25V, VGS = 0V,

= 10V,

GS

- 0.016 0.023

- 2200 - pF

f = 1MHz

- 34 45 nC

VDD = 30V
ID = 12A
Ig = 1.0mA

µA

Ω

©2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A

2

www.fairchildsemi.com

Resistive Switching Characteristic s (V

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 13 - ns
Rise Time - 20 - ns
Turn-Off Delay Time - 35 - ns
Fall Time - 14 - ns
Turn-Off Time - - 64 ns

= 10V)

GS

VDD = 30V, ID = 12A
VGS = 10V, RGS = 9.1Ω

- - 50 ns

Drain-Source Diode Characteristics

I

= 12A - - 1.25 V

V

SD

t

rr

Q

RR

Notes:
1: Starting TJ = 25°C, L = 1mH, IAS = 22A, VDD = 60V, VGS = 10V.
2: R

θJA

drain pins. R

3: R

θJA

Source to Drain Diode Voltage
Reverse Recovery Time ISD=12A, dISD/dt = 100A/µs - - 39 ns

Reverse Recovered Charge ISD=12A, dISD/dt = 100A/µs - - 40 nC

is the sum of the junction-to-cas e and cas e-to-am bient th ermal r esistance whe re the case therm al refer ence is defined a s the solder mounti ng surface of the
is measured with 1.0 in2 copper on FR-4 board.

is guaranteed by design while R

θJC

is determined by the user’s board design.

θJA

SD

ISD = 6A - - 1.0 V

FDS5672 N-Channel PowerTrench

®

MOSFET

©2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A

3

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FDS5672 N-Channel PowerTrench

Typical Characteristics T

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 150

TA, AMBIENT TEMPERATURE (oC)

Figure 1.

Normalized Power Dissipation vs

= 25°C unless otherwise noted

C

125

Ambient Temperature

2
1

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.02

0.01

0.1

15

12

9

6

, DRAIN CURRENT (A)

D

I

3

0

25 50 75 100 125 150

TA, AMBIENT TEMPERATURE (oC)

Figure 2.

Maximum Continuous Drain Current vs

V

= 10V

GS

Ambient Temperature

®

MOSFET

, NORMALIZED

θJA

Z

0.01

THERMAL IMPEDANCE

0.001
10

1100

100

, PEAK CURRENT (A)

DM

I

10

-5

10

-5

VGS = 10V

-4

10

Figure 3.

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-4

10

SINGLE PULSE

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-3

10

-2

10

t, RECTANGULAR PULSE DURATION (s)

-1

10

10

0

1

10

Normalized Maximum Transient Thermal Impedance

TA = 25oC

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

I = I

-3

10

Figure 4.

-2

10

t, PULSE WIDTH (s)

-1

10

Peak Current Capability

0

10

1

10

P

DM

1/t2

x R

θJA

θJA

o

C DERATE PEAK

25

t

1

t

+ T

2

10

150 - T

125

2

10

2

A

3

10

A

3

10

©2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A

4

www.fairchildsemi.com

FDS5672 N-Channel PowerTrench

Typical Characteristics T

400

100

10

OPERATION IN THIS

AREA MAY BE

, DRAIN CURRENT (A)
I

LIMITED BY r

1

D

SINGLE PULSE
TJ = MAX RAT E D

T

= 25oC

A

0.1

0.1 1 10 70

Figure 5.

25

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

20

V

= 15V

DD

15

10

, DRAIN CURRENT (A)

D

I

5

0

3.03.54.04.55.05.5

DS(ON)

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

Forward Bias Safe Operating Area

TJ = 150oC

TJ = 25oC

VGS, GATE TO SOURCE VOLTAGE (V)

= 25°C unless otherwise noted

C

100µs

1ms

10ms

TJ = -55oC

50

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

10

, AVALANCHE CURRENT (A)

AS

I

1

STARTING TJ = 150oC

tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

1010.1 100

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6.

Unclamped Inductive Switching

Capability

25

, DRAIN CURRENT (A)

D

I

VGS = 6V

20

15

10

5

0

0.20 0.4 0.6 0.8 1.0
VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 10V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

TA = 25oC

VGS = 5V

VGS = 4.5V

®

MOSFET

Figure 7.

15.0

12.5

10.0

7.5

DRAIN TO SOURCE ON RESISTANCE (m Ω)

5.0
036912

Figure 9.

Drain to Source On Resistance vs Drain

Transfer Characteristics Figure 8. Saturation Characteristics

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

I

, DRAIN CURRENT (A)

D

Current

©2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A

VGS = 6V

VGS = 10V

5

2.0
PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

1.5

1.0

ON RESISTANCE

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

Figure 10.

Normalized Drain to Source On

VGS = 10V, ID = 12A

Resistance vs Junction Temperature

www.fairchildsemi.com

FDS5672 N-Channel PowerTrench

Typical Characteristics T

1.2

1.1

1.0

0.9

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.7

0.6

-80 -40 0 40 80 120 160

Figure 11.

TJ, JUNCTION TEMPERATURE (oC)

Normalized Gate Threshold Voltage vs

C

VGS = VDS, ID = 250µA

Junction Temperature

6000

C

= CGS + C

1000

ISS

C

OSS

≅ C

DS

+ C

GD

GD

= 25°C unless otherwise noted

1.10

1.05

1.00

BREAKDOWN VOLTAGE

0.95

NORMALIZED DRAIN TO SOURCE

0.90

Figure 12.

Breakdown Voltage vs Junction Temperature

10

8

6

ID = 250µA

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

Normalized Drain to Source

VDD = 50V

®

MOSFET

C

= C

RSS

GD

C, CAPACITANCE (pF)

100

V

= 0V, f = 1MHz

GS

40

0.1 11060
VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13.

Capacitance vs Drain to Source

Voltage

4

, GATE TO SOURCE VOLTAGE (V)

2

GS

V

0

0 5 10 15 20 25 30 35

Figure 14.

Gate Charge Waveforms for Constant

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 12A
I

= 1A

D

Gate Currents

©2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A

6

www.fairchildsemi.com

Test Circuits and Waveforms

FDS5672 N-Channel PowerTrench

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

t

0V

P

Figure 15.

I

g(REF)

V

DS

L

0.01Ω

+

V

DD

-

0

R

AS

G

DUT

I

AS

Unclamped Energy Test Circuit Figure 16.

V

DS

L

V

GS

DUT

+

V

DD

-

V

DD

V

GS

V

= 2V

GS

0

Q

g(TH)

I

g(REF)

0

BV

DSS

t

P

I

AS

t

AV

Unclamped Energy Waveforms

Q

g(TOT)

V

DS

Q

gs2

Q

gs

Q

gd

V

DS

V

DD

®

MOSFET

V

= 10V

GS

Figure 17.

V

GS

Figure 19.

©2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A

Gate Charge Test Circuit Figure 18.

V

GS

R

GS

Switching Time Test Circuit Figure 20.

Gate Charge Waveforms

V

DS

R

DUT

L

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

Switching Time Waveforms

7

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Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and

(oC), and thermal resistance R

A

is never exceeded.

JM

serves as the basis for establishing the rating of the part.

P

TJMTA–()

------------------------------ -=

DM

R

θJA

In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
and influenced by many factors:

1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized

150

COPPER BOARD AREA - DESCENDING ORDER

2

0.04 in

2

0.28 in

120

C/W)

o

90

, THERMAL

60

θJA

Z

IMPEDANCE (

30

0.52 in

0.76 in

1.00 in

2
2
2

DM

(oC/W)

θJA

(EQ. 1)

is complex

DM

, in an

maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.

θJA

64

R

The transient thermal impedance (Z
varied top copper board area. Figure 22 shows the effect of

26

+=

-------------------------------

0.23 Area+

(EQ. 2)

) is also effected by

θJA

copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.

Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.

200

R

= 64 + 26/(0.23+Area)

θJA

150

C/W)

o

(

θJA

R

100

50

0.001 0.01 0.1 1 10

AREA, TOP COPPER AREA (in2)

Figure 21. Thermal Resistance vs Mounting

Pad Area

FDS5672 N-Channel PowerTrench

®

MOSFET

0

-1

10

Figure 22. Thermal Impedance vs Mounting Pad Area

©2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A

0

10

t, RECTANGULAR PULSE DURATION (s)

1

10

8

2

10

www.fairchildsemi.com

3

10

PSPICE Electrical Model

E

.SUBCKT FDS5672 2 1 3 ; rev June 2005
Ca 12 8 7e-10
Cb 15 14 7e-10
Cin 6 8 2.2e-10

Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 67
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1
Lgate 1 9 1.23e-9

Ldrain 2 5 1.0e-9
Lsource 3 7 0.18e-9

RLgate 1 9 12.3
RLdrain 2 5 10
RLsource 3 7 1.8

Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1e-3
Rgate 9 20 1.4
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 3.2e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),2.5))}
.MODEL DbodyMOD D (IS=4.5E-12 RS=4.7e-3 TRS1=1.5e-3 TRS2=2e-5

+ CJO=1.6e-9 M=0.55 TT=1.8e-8 XTI=3.0)
.MODEL DbreakMOD D (RS=2.5 TRS1=1.0e-3 TRS2=1e-6)
.MODEL DplcapMOD D (CJO=6.0e-10 IS=1.0e-30 N=10 M=0.45 )

.MODEL MmedMOD NMOS (VTO=3.35 KP=4 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.4)
.MODEL MstroMOD NMOS (VTO=3.93 KP=50 IS=1e-30 N=10 TOX=1 L=1u W= 1u)
.MODEL MweakMOD NMOS (VTO=2.82 KP=0.04 IS=1 e-30 N=10 TOX=1 L=1u W=1u RG=14 RS=0.1)

.MODEL RbreakMOD RES (TC1=7e-4 TC2=-1.3e-7)
.MODEL RdrainMOD RES (TC1=1.0e-4 TC2=1e-5)
.MODEL RSLCMOD RES (TC1=1.0e-2 TC2=1e-7)
.MODEL RsourceMOD RES (TC1=1.0e-2 TC2=1.0e-6)
.MODEL RvthresMOD RES (TC1=-3.9e-3 TC2=-1.4e-5)
.MODEL RvtempMOD RES (TC1=-4e-3 TC2=2e-7)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-2.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-4.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0 VOFF=-0.5)

.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

17
18

7

RLSOURCE

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURC

3

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP
+

18
22

20

S1A

12

13

8

S1B

EGS EDS

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

6

-

S2A

14
13

S2B

13

+

+

6
8

-

-

5

RSLC1

51

+

5

ESLC

51

­50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5
8

-

MMED

8

DBREAK

11

+

EBREAK

-

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

FDS5672 N-Channel PowerTrench

®

MOSFET

©2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A

9

www.fairchildsemi.com

SABER Electrical Model

REV June 2005
ttemplate FDS5672 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=4.5e-12,rs=4.7e-3,trs1=1.5e-3,trs2=2e-5,cjo=1.6e-9,m=0.55,tt=1.8e-8,xti=3.0)
dp..model dbreakmod = (rs=2.5,trs1=1e-4,trs2=1e-6)
dp..model dplcapmod = (cjo=6.0e-10,isl=10.0e-30,nl=10,m=0.45)
m..model mmedmod = (type=_n,vto=3.35,kp=4,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=3.93,kp=50,is=1e-30 , tox=1)
m..model mweakmod = (type=_n,vto=2.82,kp=0.04,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.0,voff=-2.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-4.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0,voff=-0.5)
c.ca n12 n8 = 7e-10
c.cb n15 n14 = 7e-10
c.cin n6 n8 = 2.2e-9

dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 67
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1

GATE

1

spe.evthres n6 n21 n19 n8 = 1

LGATE

9

RLGATE

RGATE

ESG

EVTEMP
+

18
22

20

spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1

CA

S1A

12

S1B

l.lgate n1 n9 = 1.23e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 0.18e-9

res.rlgate n1 n9 = 12.3
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 1.8

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=7e-4,tc2=-1.3e-7
res.rdrain n50 n16 = 1e-3, tc1=1e-4,tc2=1e-5
res.rgate n9 n20 = 1.4
res.rslc1 n5 n51 = 1e-6, tc1=1e-2,tc2=1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.2e-3, tc1=1e-2,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-3.9e-3,tc2=-1.4e-5
res.rvtemp n18 n19 = 1, tc1=-4e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 2.5))
}
}

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

+

19

8

6

-

S2A

14

13

13

8

S2B

13

+

+

6

EGS EDS

8

-

-

15

CIN

CB

-

+

5
8

-

5

RSLC1

51

50
RDRAIN

21

MSTRO

14

ISCL

16

8

MMED

8

DBREAK

11

MWEAK

EBREAK

+

RSOURCE

RBREAK

17 18

IT

RVTHRES

-

17
18

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDS5672 N-Channel PowerTrench

®

MOSFET

©2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A

10

www.fairchildsemi.com

SPICE Thermal Model

REV June 2005
FDS5672_JA Junction Ambient

Copper Area = 1sq.in
CTHERM1 TH 8 2e-3

CTHERM2 8 7 5e-3
CTHERM3 7 6 1e-2
CTHERM4 6 5 4e-2
CTHERM5 5 4 9e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
CTHERM8 2 TL 3

RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25

SABER Thermal Model

SABER thermal model FDS5672
Copper Area = 1sq.in
template thermal_ model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2e-3
ctherm.ctherm2 8 7 =5e-3
ctherm.ctherm3 7 6 =1e-2
ctherm.ctherm4 6 5 =4e-2
ctherm.ctherm5 5 4 =9e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 =1
ctherm.ctherm8 2 tl =3

rrtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

th

8

7

6

5

4

3

2

JUNCTION

CTHERM1

CTHERM2

CTHERM3

CTHERM4

CTHERM5

CTHERM6

CTHERM7

CTHERM8

FDS5672 N-Channel PowerTrench

®

MOSFET

tl

AMBIENT

T ABLE 1. THERMAL MODELS

COMPONANT 0.04 in

2

0.28 in

2

0.52 in

2

0.76 in

2

1.0 in

2

CTHERM6 1.2e-1 1.5e-1 2.0e-1 2.0e-1 2.0e-1

CTHERM7 0.5 1.0 1.0 1.0 1.0

CTHERM8 1.3 2.8 3.0 3.0 3.0

RTHERM62620151312

RTHERM73924211918

RTHERM8 55 38.7 31.3 29.7 25

©2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A

11

www.fairchildsemi.com

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DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

®

MOSFET

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

©2005 Fairchild Semiconductor Corporation
FDS5672 Rev. A

www.fairchildsemi.com12