This P-Channel Logic Level MOSFET is produced using
Fairchild Semiconductors advanced PowerTrench process
that has been especially tailored to minimize the on-state
resistance and yet maintain low gate charge for superior
switching performance.
These devices are well suited for notebook computer applications: load switching and power management, battery
charging circuits, and DC/DC conversion.
D
D
D
D
G
S
SO-8
Absolute Maximum Ratings T
S
S
= 25°C unless otherwise noted
A
Features
-9 A, -30 V. R
R
DS(ON)
DS(ON)
= 0.0175 Ω@ V
= 0.0250 Ω@ V
= -10 V
GS
= -4.5 V
GS
Low gate charge (21nC typical).
High performance trench technology for extremely
low R
DS(ON)
.
High power and current handling capability.
5
6
7
8
4
3
2
1
SymbolParameterRatingsUnits
V
DSS
V
GSS
I
D
P
D
TJ, T
stg
Drain-Source Voltage-30V
Gate-Source Voltage
Drain Current - Continuous (Note 1a)-9A
- Pulsed-50
Power Dissipation for Single Operation(Note 1a)2.5W
(Note 1b)
(Note 1c)
Operating and Storage Junct i on Temperature Range-55 to +150
Input Capacitance2010pF
Output Capacitance590pF
Reverse Transfer Capacitance
V
= -15 V, VGS = 0 V
DS
f = 1.0 MHz
260pF
Switching Characteristics (Note 2)
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
g
gs
gd
Turn-On Delay Time1222ns
Turn-On Rise Time1527ns
= -15 V, ID = -1 A
V
DD
V
= -10 V, R
GS
GEN
= 6 Ω
Turn-Off Delay Time100140ns
Turn-Off Fall Tim e
Total Gate Charge2130nC
Gate-Source Charge6nC
V
= -15 V, ID = -9 A
DS
= -5 V,
V
GS
Gate-Drain Char ge
5580ns
8nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
V
SD
t
rr
Notes:
1: R
θJA
drain pins. R
Scale 1 : 1 on letter size paper
2: Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Maximum Cont i nuous Drain-Sou rce Diode Forward Current-2.1A
Drain-Sourc e Diode Forward Volta geVGS = 0 V, IS = -2.1 A (Note 2)0.75-1.2V
Source-Drain Reverse Recovery Time
is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface of the
Figure 5. Transfer CharacteristicsFigure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature
FDS4435A Rev. C
Page 4
Typical Characteristics (continued)
FDS4435A
10
ID = -8.8A
8
VDS = -5V
-15V
6
4
2
, GATE-SOURCE VOLTAGE (V)
GS
-V
0
05101520253035
, GATE CHARGE (nC)
Q
g
Figure 7. Gate-Charge Characteristics
100
R
LIMIT
DS(ON)
10
1
VGS = -10V
SINGLE PULSE
, DRAIN CURRENT (A)
D
0.1
-I
0.01
= 125oC/W
R
JA
θ
= 25oC
T
A
0.1110100
, DRAIN-SOURCE VOLTAGE (V)
-V
DS
1s
10s
DC
100µs
1ms
10ms
100ms
-10V
2500
2000
1500
C
ISS
f = 1 MHz
= 0 V
V
GS
1000
CAPACITANCE (pF)
500
0
051015202530
, DRAIN TO SOURCE VOLTAGE (V )
-V
DS
C
OSS
C
RSS
Figure 8. Capacitance Characteristics
50
40
30
20
POWER (W)
10
0
0.0010.010.1110100 300
SINGLE PULSE TIME (SEC)
SINGLE PULSE
R =125°C/W
θJA
T = 25°C
A
Figure 9. Maximum Safe Operating AreaFigure 10. Single Pulse Maximum
Power Dissipation
1
D = 0.5
0.5
0.2
0.2
0.1
0.05
0.02
0.01
0.005
r(t), NORM ALIZED EFF ECT I VE
0.002
TR ANSI ENT TH ER MAL RESISTANC E
0.001
0.00010.0010.010.1110100300
0. 1
0.05
0.02
0. 0 1
S i n g l e P u l s e
t , TI ME (s e c)
1
R (t) = r(t) * R
JA
θ
R = 125°C/ W
JA
θ
P(pk )
t
1
t
2
T- T = P * R (t)
J
D u t y C y c l e, D = t /t
JA
A
θ
JA
θ
2
1
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient themal response will change depending on the circuit board design.
FDS4435A Rev. C
Page 5
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging
Configuration: Figure 1.0
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC
ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS
TNR DATE
PT NUMBER
PEEL STRENGTH MIN ______________gms
Customized
Label
Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Reel Size
Box Dimension (mm)
Max qty per Box
Weight per unit (gm)
Weight per Reel (kg)
Note/Comments
MAX _____________ gms
ESD Label
SOIC (8lds) Packaging Information
Standard
(no flow code)
TNR
2,500954,000
13" Dia
343x64x343 530x130x83 343x64x343
5,00030,0008,000
0.07740.07740.07740.0774
0.6060-0.96960.1182
L86ZF011
Rail/Tube-TNR
13" Dia
Embossed Car rier Tape
Antistatic Cover Tape
Static Dissipative
F63TNR
Label
D84Z
TNR
500
7" Dia
184x18 7x47
1,000
F
NDS
9959
9959
852
SOIC-8 Unit Orientation
343mm x 342mm x 64mm
Stand a r d In t e rm ed iate box
Packaging Description:
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 uni t s pe r 13" o r 33 0c m d ia met er reel . Th e reel s ar e
dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or
177cm di ameter reel. This and some o ther options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in di ff ere nt siz es depe nd in g on th e num be r of pa rts
shippe d.
F
NDS
9959
F
NDS
9959
F
NDS
852
852
852
F
NDS
9959
852
Pin 1
F63TNR Label sample
LOT: CBVK741B019
FSID: FDS9953A
D/C1: D9842 QTY1: SPEC REV:
D/C2: QTY2: CPN:
QTY: 2500
SPEC:
N/F: F (F63TNR)3
SOIC(8lds) Tape Leader and Trailer
Configuration: Figure 2.0
Carrier Tape
Cover Tape
Trailer Tape
640mm minimum or
80 empty pockets
F63TNLab el
ESD Label
Components
ESD Label
F63TNLabel
Leader Tape
1680mm minimum or
210 empty pockets
July 1999, Rev. B
Page 6
SO-8 Tape and Reel Data and Package Dimensions, continued
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
SOIC(8lds) Reel Configuration: Figure 4.0
A0B0WD0D1E1E2FP1P0K0TWcTc
(8lds)
6.50
5.30
12.0
1.55
1.60
1.75
10.25
+/-0.10
+/-0.10
+/-0.3
+/-0.05
+/-0.10
+/-0.10
rotational and lateral movement requirements (see sketches A, B, and C).
B0
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
5.50
min
+/-0.05
20 deg maximum
A0
Sketch B (Top View)
Component Rotation
W1 Measured at Hub
8.0
+/-0.1
Typical
component
cavity
center line
Typical
component
center line
Dim A
Max
4.0
+/-0.1
0.450
2.1
+/-0.10
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
+/-
0.150
9.2
+/-0.3
0.5mm
maximum
0.06
+/-0.02
Dim A
max
Tape Size
12mm7" Dia
12mm13" Dia
1998 Fairchild Semiconductor Corporation
Reel
Option
Dim N
Diameter Option
7"
See detail AA
B Min
Dim C
13" Diameter Option
See detail AA
W2 max Measured at Hub
Dim D
W3
min
DETAIL AA
Dimensions are in inches and millimeters
Dim ADim BDim CDim DDim NDim W1Dim W2Dim W3 (LSL-USL)
7.00
0.059
177.8
13.00
330
1.5
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
512 +0.020/-0.008
13 +0.5/-0.2
0.795
2.165550.488 +0.078/-0.000
20.2
0.795
7.00
20.2
178
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.724
18.4
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
July 1999, Rev. B
Page 7
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1 : 1
Scale 1:1 on letter size paper
Dimen sions s hown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A
Page 8
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STA TUS DEFINITIONS
Definition of Terms
Datasheet IdentificationProduct StatusDefinition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or
In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
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