Datasheet FDS3692 Datasheet (Fairchild)

FDS3692

N-Channel PowerTrench® MOSFET
100V, 4.5A, 60mΩ

FDS3692

September 2002

Features

•r

•Q

• Low Miller Charge

•Low Q

• Optimized eff iciency at high frequ encies

• UIS Capability (Single Pulse and Repetitive Pulse)

= 50mΩ (Typ.), V

DS(ON)

(tot) = 11nC (Typ.), V

g

Body Diode

RR

= 10V, ID = 4.5A

GS

= 10V

GS

Applications

• DC/DC converters and Off-Line UPS

• Distributed Power Architectures and VRMs

• PrimarySwitch for 24V and 48V Systems

• High Voltage Synchronous R ectifier

• Direct Injection / Diesel Injection Systems

• 42V Automotive Load Control

Formerly developmental type 82745

Branding Dash

1

2

3

4

5

• Electronic Valve Train Systems

5
6
7
8

SO-8

MOSFET Maximum Ratings T

Symbol Parameter Ratings Units

V

DSS

V

GS

I

D

E

AS

P

D

T

, T

J

STG

Drain to Source Voltage 100 V
Gate to Source Voltage ±20 V
Drain Curr e nt
Continuous (T
Continuous (T

= 25oC, VGS = 10V, R

A

= 100oC, VGS = 10V, R

A

Pulsed Figure 4 A
Single Pulse Avalanche Energy (Note 1) 171 mJ
Power dissipation 2.5 W

o

Derate above 25

C20mW/

Operating and Storage Temperature -55 to 150

= 25°C unless otherwise noted

A

= 50oC/W)

θJA

= 50oC/W) 2.8 A

θJA

4.5 A

4
3
2
1

o

C

o

C

Thermal Characteristi cs

R

θJA

R

θJA

R

θJC

ThermalResistance,Junction to Ambientat 10 seconds (Note 3) 50
ThermalResistance,Junction to Ambientat 1000 seconds (Note 3) 85
ThermalResistance,Junctionto Case (Note 2) 25

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDS369 2 FDS3692 SO-8 330mm 12mm 2500 un its

©2002 Fairchild Semiconductor Corporation

o

C/W

o

C/W

o

C/W

FDS3692 Rev. B

FDS3692

Electrical Characteristics T

= 25°C unl ess otherwise noted

A

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B
I

DSS

I

GSS

VDSS

Drain t o Source Breakdown Volta ge ID = 250µA, VGS = 0V 100 - - V

V

= 80V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- - 250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

Drain to Source On Resistance

= 4.5A, V

I

D

I

= 2A, VGS = 6V - 0.064 0.096

D

I

= 4.5A, V

D

T

= 150oC

C

= 10V - 0.050 0.060

GS

= 10V,

GS

- 0.101 0.122

Dynamic Characteristics

C
C
C
Q
Q
Q
Q
Q

ISS
OSS
RSS

g(TOT)
g(TH)
gs
gs2
gd

Input Capacitance
Output Capacitance - 115 - pF
Reverse Transfer Capacitance - 27 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total G ate Ch arg e at 10 V VGS = 0V to 10V
Threshold Gate Charge VGS = 0V to 2V - 1.4 1.9 nC
Gate to Source Gate Charge - 3.5 - nC
Gate Charge Threshold to Plateau - 2.1 - nC

V

DD

I

= 4.5A

D

I

= 1.0m A

g

= 50V

Gate to Drain “Miller” Charge - 2.8 - nC

-746- pF

-1115nC

µA

Ω

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 9.8 - ns
Rise Time - 26 - ns
T u rn-Off Delay Time - 34 - ns
Fall Time - 26 - ns
Turn-Off Time - - 90 ns

(VGS = 10V)

V

= 50V, ID = 4.5A

DD

V

= 10V, RGS = 26Ω

GS

--54ns

Drain-Source Diode Characteristics

I

= 4.5A - - 1.25 V

V

SD

t

rr

Q

RR

Notes:
1: Starting T
2: R

θJA

drain pins. R

3: R

θJA

Source to Drain Di ode Voltage
Reverse Recovery Time ISD= 4.5A, dISD/dt= 100A/µs- - 47ns

Reverse Recovered Charge ISD= 4.5A, dISD/dt= 100A/µs- - 64nC

= 25°C, L = 38mH, IAS = 3A.

J

is the sum of the junction-to-case and cas e-to-a mbient thermal r esistance wher e the case thermal reference is defined as the solder mounting su rface of the
is measured with 1.0 in2 copper on FR-4 board

is guaranteed by design while R

θJC

is determined by the user’s board design.

θCA

SD

I

= 2A - - 1.0 V

SD

©2002 Fairchild Semiconductor Corporation FDS3692 Rev . B

FDS3692

Typical Characteristics T

= 25°C unl ess otherwise noted

A

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

1

0.5

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

0.01

θJA

Z

THERMAL IMPEDANCE

0.001

-5

10

SINGLE PULSE

-4

10

-3

10

5

4

3

2

, DRAIN CURRENT (A)

D

I

1

0

125

25 50 75 100 125 150

Figure 2. Maximum Continuous Drain Curr ent vs

-2

10

t, RECTANGULAR PULSE DURATION (s)

-1

10

10

TC, CASE TEMPERATURE (oC)

Case Temperature

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

0

1

10

V

= 10V

GS

R

=50oC/W

θJA

P

DM

t

1

t

2

1/t2

x R

+ T

θJA

θJA

A

2

10

3

10

Figure 3. Normalized Maximum Transient Thermal Impedance

200

100

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

VGS = 10V

10

, PEAK CURRENT (A)

DM

I

1

-5

10

-4

10

-3

10

-2

10

t, PULSE WIDTH (s)

-1

10

0

10

TA = 25oC
FOR TEMPERATURES

o

ABOVE 25
CURRENT AS FOLLOWS:

I = I

25

1

10

10

C DERATE PEAK

150 - T

C

125

2

3

10

Figure 4. Peak Current Capability

©2002 Fairchild Semiconductor Corporation FDS3692 Rev . B

Typical Characteristics T

= 25°C unl ess otherwise noted

A

FDS3692

200

, DRAIN CURRENT (A)
I

D

0.01

100

10

1

0.1
SINGLE PULSE

TJ = MAX R ATED
T

OPERATION IN THIS

AREA MAY BE

LIMITED BY r

= 25oC

C

DS(ON)

110100

VDS, DRAIN TO SOURCE VOLTAGE (V)

10µs

100µs

1ms
10ms

100ms

1s

Figure 5. Forward Bias Safe Operating Area

30

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= 15V

DD

25

20

15

10

, DRAIN CURRENT (A)

D

I

5

0

TJ = 25oC

3.5 4.0 4.5 5.0 5.5 6.0 6.5

TJ = 150oC

TJ = -55oC

VGS, GATE TO SOURCE VOLTAGE (V)

7

STARTING TJ = 25oC

STARTING TJ = 150oC

1

, AVALANCHE CURRENT (A)

If R = 0

AS

I

tAV = (L)(IAS)/(1.3*RATED BV
If R ≠ 0

t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

3000.1

0.1

0.01 0.1 1 10 100
tAV, TIME IN AVALANCHE (ms)

DSS

- VDD)

- VDD) +1]

DSS

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

30

TA = 25oC

25

20

15

10

, DRAIN CURRENT (A)

D

I

5

0

0 0.5 1.0 1.5 2.0

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 10V

VGS = 6V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = 7V

VGS = 5V

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

70

VGS = 6V

65

60

55

VGS = 10V

50

45

DRAIN TO SOURCE ON RESISTANCE (m Ω)

1.01.52.02.53.03.54.04.5
I

, DRAIN CURRENT (A)

D

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

©2002 Fairchild Semiconductor Corporation FDS3692 Rev . B

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 4.5A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDS3692

Typical Characteristics T

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)

= 25°C unl ess otherwise noted

A

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperatur e

2000

C

= CGS + C

1000

ISS

C

OSS

≅ C

DS

+ C

GD

GD

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160
T

, JUNCTION TEMPERATURE (oC)

J

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 50V

8

6

100

C

= C

RSS

GD

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

10

0.1 1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Sour ce

Voltage

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

024681012

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 4.5A
ID = 2A

Figure 14. Gat e Charge Waveforms for Constant

Gate Currents

©2002 Fairchild Semiconductor Corporation FDS3692 Rev . B

Test Circuits and Waveforms

FDS3692

BV

DSS

t

P

V

DS

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

V

DS

L

I

AS

R

AS

G

+

V

DD

-

DUT

t

0V

P

I

AS

0.01Ω

0

t

AV

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

I

g(REF)

DS

L

V

GS

+

V

DD

-

DUT

Q

V

0

g(TH)

I

g(REF)

0

DD

V

GS

V

= 2V

GS

Q

gs2

Q

gs

Q

g(TOT)

V

DS

Q

gd

V

DD

V

= 10V

GS

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

10%

90%

PULSE WIDTH

50%50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2002 Fairchild Semiconductor Corporation FDS3692 Rev . B

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maxi mum al lowab le de vice p ower di ssip ation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

DM

θJA

, in an

(oC/W)

serve s as the basis for establ ishing the rating of the part.

P

TJMTA–()

---------------- -------------- -=

DM

R

θJA

(EQ. 1)

In usin g surf ace m o unt d evic es s uch a s the SO8 pa ckag e,
the env ironment in which it is ap plied wi ll ha ve a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
and influenced by many factors:

is complex

DM

1. Mou nting pad area ont o which the device is attached and
whet her the re is copp er on one s ide or both side s of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For no n steady state applic ations, th e pulse widt h, the
duty cycle and the transient thermal response of the part,
the boa rd and the environment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 board w i th 1 oz c opper af ter 100 0 se c on ds
of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides
the necessary inf ormation for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice t hermal model or manually u tilizing the normalized

150

COPPER BOARD AREA - DESCENDING ORDER

2

0.04 in

2

0.28 in

, THERMAL

θJA

Z

120

C/W)

o

90

60

IMPEDANCE (

30

0.52 in

0.76 in

1.00 in

2
2
2

maximum transient thermal impedance curve.
Therma l resistan ces corre sponding to other co pper areas

can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.

R

The tr ansi ent t her mal i mp eda nce (Z
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.

Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RT HER M 5 re main co ns ta nt fo r ea ch of th e th erm al
models . A li sti ng of th e m od el comp one nt v alue s i s ava i labl e
in Table 1.

64

θJA

200

150

C/W)

o

(

θJA

R

100

50

0.001 0.01 0.1 1 10

26

-------------------------------+=

0.23 Area+

θJA

R

θJA

AREA, TOP COPPER AREA (in2)

(EQ. 2)

) is also ef fect ed by

= 64 + 26/(0.23+Area)

Figure 21. Thermal Resistance vs Mounting

Pad Area

FDS3692

0

-1

10

0

10

t, RECTANGULAR PULSE DURATION (s)

1

10

2

10

3

10

Figure 22. Thermal Impedance vs Mount ing Pad Area

©2002 Fairchild Semiconductor Corporation FDS3692 Rev . B

PSPICE Electrical Model

.SUBCKT FDS 3692 2 1 3 ; rev Aug 2002
Ca 12 8 2.82e-10
Cb 15 14 2.82e-10
Cin 6 8 7.0e-10

Dbod y 7 5 DbodyMOD
Dbreak 5 11 Db reakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 109.7
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1
Lgat e 1 9 5.61e-9

Ldrain 2 5 1e-9
Lsource 3 7 1.98e-9

RLgate 1 9 56.1
RLdr ai n 2 5 10
RLsource 3 7 19.8

Mmed 16 6 8 8 M m edMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 28.0e-3
Rgate 9 20 3.7
RSLC1 5 51 RSL CM OD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 14.0e-3
Rvthres 22 8 Rvthresmo d 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BM OD
S2a 6 15 14 13 S2AM OD
S2b 13 15 14 13 S2BM OD

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

-

13

10

6
8

RSLC2

6

14
13

+

+

6
8

-

-

DPLCAP

EVTHRES

+

19

S2A

S2B

FDS3692

17
18

-

7

+

RVTEMP
19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

5

RSLC1

51

+

5

ESLC

51

­50

RDRAIN

16

21

-

8

MSTRO

CIN

15

CB

8

14

+

5
8

-

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

+

DRAIN

2

SOURCE

3

Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51))) *(PWR(V(5,51)/(1e-6 *40),2.5)) }
.MODEL DbodyMOD D (IS=2.4E-12 N=1.03 RS=8.2e-3 TRS1=2.1e-3 TRS2=4.7e-7

+ CJO=5.5e-10 M=0.57 TT=3.25e-8 XTI=4.6)
.MODEL DbreakMOD D (RS=1.6 TRS1=2.4 e-3 TRS2=-1.0e-5)
.MODEL Dpl capMOD D (CJO=1.55e-10 IS=1e-3 0 N=10 M=0.54)

.MODEL MmedM OD NMOS (VTO=3.8 KP=2.1 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3. 7)
.MODEL MstroMOD NMOS (VTO =4.3 KP=26 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL Mwe akMOD NMOS (VTO =3.26 KP=0. 04 IS=1e-30 N= 10 T OX=1 L=1u W=1u RG=37 RS=0.1)

.MODEL Rb reakMOD RES (T C1=1.1e-3 TC2=-1.0e-8)
.MODEL Rd rai nMOD RES (TC1=9.0e-3 TC 2=2.9e-5)
.MODEL RSLCMOD RES (TC1=2.5e-3 TC2=2.2e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-4.8e -3 T C2=-1.1e-5 )
.MODEL RvtempMOD RES (T C1=-3.0e-3 TC2=1.5e-6)

.MODEL S1AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 3. 0 VOFF =-2 .0 )
.MODEL S1BMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 2. 0 VOFF =-3 .0 )
.MODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 1.5 VO FF=1.0)
.MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= 1 .0 VOFF= -1.5)

.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electroni cs Specialist Conference Records, 1991, written by Wil liam J. Hepp and C. F rank
Wheatley.

©2002 Fairchild Semiconductor Corporation FDS3692 Rev . B

SABER Electrical Model

REV Aug 2002
template FDS3692 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.4e-12,nl=1.03,rs=8.2e-3,trs1=2.1e-3,trs2=4.7e-7,cjo=5.5e-10,m=0.57,tt=3.25e-8,xti=4.6)
dp..model dbreakmod = (rs=1.6,trs1=2.4e-3,trs2=-1.0e-5)
dp..model dplcapmod = (cjo=1.55e-10,isl=10e-30,nl=10,m=0.54)
m..model mmedmod = (type=_n,vto=3.8,kp=2.1,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.3,kp=26,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.26,kp=0.04,is=1e-30, tox=1,rs=0.1)
sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0. 1, von=-3.0,voff=-2.0)
sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0. 1, von=-2.0,voff=-3.0)
sw_vcsp.. mo del s2amod = (ron=1e-5,roff=0.1,von=-1.5, vof f = 1. 0)
sw_vcsp.. mo del s2bmod = (ron=1e-5,roff=0.1,von=1.0,voff=-1.5)
c.ca n12 n8 = 2.82e-10
c.cb n15 n14 = 2.82e-10
c.cin n6 n8 = 7.0e -10

dp.dbody n7 n5 = model=dbodym od
dp.dbreak n5 n11 = model=dbr eakmod
dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 109.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1

GATE

spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1

LGATE

1

RLGATE

9

RGATE

ESG

EVTEMP

+

18
22

20

spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 5.61e-9

l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 1.98e-9

res.rlgate n1 n9 = 56.1
res.rldrai n n2 n5 = 10
res.rlsource n3 n7 = 19.8

12

CA

S1A

13

S1B

EGS EDS

m.mmed n16 n6 n8 n8 = m odel=mmedm od, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l= 1u, w=1u
m.mweak n16 n21 n8 n8 = model=mwea kmod, l=1u, w=1u

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

+

6

-

S2A

14

8

13

S2B

13

+

+

6
8

-

-

5

RSLC1

51

ISCL

8

MMED

8

DBREAK

11

MWEAK

EBREAK

+

RSOURCE

RBREAK

17 18

IT

RVTHRES

50
RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

14

+

5
8

-

17
18

­7

RLSOURCE

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

FDS3692

res.rbreak n17 n18 = 1, tc1=1.1e- 3,tc2=-1.0e -8
res.rdrain n50 n16 = 28.0e-3, tc 1=9.0e-3,tc 2=2.9e-5
res.rgate n9 n20 = 3.7
res.rslc1 n5 n51 = 1e-6, tc1=2.5e-3,tc2=2. 2e-6
res.rslc2 n5 n50 = 1e3
res.rsour ce n8 n7 = 14.0e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-4.8e-3,tc2=-1. 1e-5
res.rvtemp n18 n19 = 1, tc1=-3.0e-3,tc2=1.5e-6
sw_vcsp.s1 a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1 b n13 n12 n13 n8 = mode l= s1bmod
sw_vcsp.s2 a n6 n15 n14 n13 = mode l= s2amod
sw_vcsp.s2 b n13 n15 n14 n13 = model = s2bmod

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5 ,n51))))*(( abs(v(n5,n51)*1e6/40) )** 2. 5))
}

©2002 Fairchild Semiconductor Corporation FDS3692 Rev . B

FDS3692

SPICE Thermal Model

REV Aug 2002
FDS3692
Copper Area =1.0 in

2

CTHERM1 TH 8 4e-4
CTHERM2 8 7 5e-3
CTHERM3 7 6 6e-2
CTHERM4 6 5 9e-2
CTHERM5 5 4 3e-1
CTHERM6 4 3 4e-1
CTHERM7 3 2 9e-1
CTHERM8 2 T L 2

RTHERM1 TH 8 5e-1
RTHERM2 8 7 6e-1
RTHERM3 7 6 4
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 9
RTHERM7 3 2 15
RTHERM8 2 TL 23

SABER Thermal Model

Copper Area = 1. 0 i n
template thermal_model th tl
thermal_ c th , tl
{
CTHERM1 TH 8 4e-4
CTHERM2 8 7 5e-3
CTHERM3 7 6 6e-2
CTHERM4 6 5 9e-2
CTHERM5 5 4 3e-1
CTHERM6 4 3 4e-1
CTHERM7 3 2 9e-1
CTHERM8 2 T L 2

RTHERM1 TH 8 5e-1
RTHERM2 8 7 6e-1
RTHERM3 7 6 4
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 9
RTHERM7 3 2 15
RTHERM8 2 TL 23
}

2

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

JUNCTION

th

CTHERM1

8

CTHERM2

7

CTHERM3

6

CTHERM4

5

CTHERM5

4

CTHERM6

3

CTHERM7

2

CTHERM8

CASE

tl

TABLE 1. THERMAL MODELS

COMPONANT 0.04 in

2

0.28 in

2

0.52 in

2

0.76 in

2

1.0 in

2

CTHERM6 3.2e-1 3.5e-1 4.0e-1 4.0e-1 4.0e-1
CTHERM7 8.5e-1 9.0e-1 9.0e-1 9.0e-1 9.0e-1
CTHERM8 0.3 1.8 2.0 2.0 2.0
RTHERM624181210 9
RTHERM73621181615
RTHERM85337302823

©2002 Fairchild Semiconductor Corporation FDS3692 Rev . B

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Definition of Terms

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Adva nce Information Formative or I n

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Production This datasheet contains specifications on a product

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Rev. I1