Datasheet FDS3672 Datasheet (Fairchild Semiconductor)

FDS3672

N-Channel PowerTrench® MOSFET 100V, 7.5A, 22mΩ

FDS3672

March 2003

Features

•r

•Q

• Low Miller Charge

•Low Q

• Optimized eff iciency at high frequ encies

• UIS Capability (Single Pulse and Repetitive Pulse)

= 19mΩ (Typ.), V

DS(ON)

(tot) = 28nC (Typ.), V

g

Body Diode

RR

= 10V, ID = 7.5A

GS

= 10V

GS

Applications

• DC/DC converters and Off-Line UPS

• Distributed Pow er Architectures and VRMs

• Primary Switch for 24V and 48V Systems

• High Voltage Synchronous Re ctifier

• Direct Injection / Diesel Injection Systems

• 42V Automotive Lo ad Control

Formerly developmental type 82763

Branding Dash

1

2

3

4

5

• Electronic Valve T rain System s

5 6 7 8

SO-8

MOSFET Maximum Ratings T

Symbol Parameter Ratings Units

V

DSS

V

GS

I

D

E

AS

P

D

, T

T

J

STG

Drain to Source Voltage 100 V Gate to Source Voltage ±20 V Drain Curr e nt Continuous (T Continuous (T

= 25oC, VGS = 10V, R

A

= 100oC, VGS = 10V, R

A

Pulsed Figure 4 A Single Pulse Avalanche Energy (Note 1) 416 mJ Power dissipation 2.5 W

o

Derate above 25

C20mW/

Operating and Storage Temperature -55 to 150

= 25°C unless otherwise noted

A

= 50oC/W)

θJA

= 50oC/W) 4.8 A

θJA

7.5 A

4 3 2 1

o

C

o

C

Thermal Characteristics

R

θJA

R

θJA

R

θJC

Thermal Resis tan ce , Ju nc tion to Ambi en t at 10 se co nds (Note 3) 50 Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3) 85 Thermal Resis tan ce , Ju nc tio n t o Cas e (Note 2) 25

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDS367 2 FDS3672 SO-8 330mm 12mm 2500 un its

o

C/W

o

C/W

o

C/W

FDS3672 Rev. B

FDS3672

Electrical Characteristics T

= 25°C unless otherwise noted

A

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B I

DSS

I

GSS

VDSS

Drain t o Source Breakdown Volta ge ID = 250µA, VGS = 0V 100 - - V

V

= 80V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- - 250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

Drain to Source On Resistance

= 7.5A, V

I

D

I

= 6.8A, VGS = 6V - 0.023 0.028

D

= 7.5A, V

I

D

T

= 150oC

C

= 10V - 0.019 0.023

GS

= 10V,

GS

- 0.035 0.043

Dynamic Characteristics

C C C Q Q Q Q Q

ISS OSS RSS

g(TOT) g(TH) gs gs2 gd

Input Capacitance Output Capacitance - 285 - pF Reverse Transfer Capacitance - 70 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total G ate Ch arg e at 10 V VGS = 0V to 10V Threshold Gate Charge VGS = 0V to 2V - 4 6 nC Gate to Source Gate Charge - 10 - nC Gate Charge Threshold to Plateau - 6.8 - nC

V

DD

I

= 7.5A

D

I

= 1.0m A

g

= 50V

Gate to Drain “Miller” Charge - 6 - nC

-2015- pF

-2837nC

µA

Ω

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time T urn-On Delay Time - 14 - ns Rise Time - 20 - ns T u rn-Off Delay Time - 37 - ns Fall Time - 27 - ns Turn-Off Time - - 96 ns

(VGS = 10V)

V

= 50V, ID = 4A

DD

V

= 10V, RGS = 10Ω

GS

--51ns

Drain-Source Diode Characteristics

I

= 7.5A - - 1.25 V

V

SD

t

rr

Q

RR

Notes: 1: Starting TJ = 25°C, L = 13mH, IAS = 8A. 2: R

θJA

drain pins. R

3: R

θJA

Source to Drain Di ode Voltage Reverse Recovery Time ISD= 7.5A, dISD/dt= 100A/µs- - 55ns

Reverse Recovered Charge ISD= 7.5A, dISD/dt= 100A/µs- - 90nC

is the sum of the junction-to-case and cas e-to-a mbient thermal r esistance wher e the case thermal reference is defined as the solder mounting su rface of the is measured with 1.0 in2 copper on FR-4 board

is guaranteed by design while R

θJC

is determined by the user’s board design.

θCA

SD

I

= 4A - - 1.0 V

SD

FDS3672

Typical Characteristics T

= 25°C unless otherwise noted

A

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

1

0.5

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

0.01

θJA

Z

THERMAL IMPEDANCE

0.001

-5

10

SINGLE PULSE

-4

10

-3

10

8

6

4

, DRAIN CURRENT (A)

D

2

I

0

125

25 50 75 100 125 150

Figure 2. Maximum Continuous Drain Curr ent vs

-2

10

t, RECTANGULAR PULSE DURATION (s)

-1

10

TC, CASE TEMPERATURE (oC)

Case Temperature

NOTES: DUTY FACTOR: D = t1/t

PEAK TJ = PDM x Z

0

1

10

V

= 10V

GS

R

=50oC/W

θJA

P

DM

t

1

t

2

x R

+ T

θJA

A

2

10

3

10

Figure 3. Normalized Maximum Transient Thermal Impedance

1000

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

VGS = 10V

100

, PEAK CURRENT (A)

DM

I

10

5

-5

10

-4

10

-3

10

-2

10

-1

10

0

10

t, PULSE WIDTH (s)

TA = 25oC FOR TEMPERATURES

ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:

150 - T

I = I

25

1

10

2

10

125

C

3

10

Figure 4. Peak Current Capability

Typical Characteristics T

= 25°C unless otherwise noted

A

FDS3672

300 100

10

1

, DRAIN CURRENT (A)

D

I

0.1

0.01

OPERATION IN THIS

AREA MAY BE

LIMITED BY r

SINGLE PULSE TJ = MAX R ATED

TC = 25oC

DS(ON)

1.0 10.0 100

VDS, DRAIN TO SOURCE VOLTAGE (V)

10µs

100µs

1ms 10ms

100ms

1s

Figure 5. Forward Bias Safe Operating Area

30

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

V

= 15V

DD

20

TJ = 150oC

30

If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

10

, AVALANCHE CURRENT (A)

AS

I

STARTING TJ = 150oC

1

3000.1

0.01 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms)

DSS

- VDD)

DSS

- VDD) +1]

ST ARTING TJ = 25oC

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

30

VGS = 10V

20

VGS = 6V

VGS = 5V

10

, DRAIN CURRENT (A)

D

I

0

2.53.03.54.04.55.05.5

TJ = 25oC

TJ = -55oC

VGS, GATE TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

24

VGS = 6V

22

20

VGS = 10V

DRAIN TO SOURCE ON RESISTANCE (m Ω)

18

02468

ID, DRAIN CURRENT (A)

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

10

, DRAIN CURRENT (A)

D

I

0

0 0.5 1.0 1.5 2.0

2.0

1.5

1.0

ON RESISTANCE

NORMALIZED DRAIN TO SOURCE

0.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

TA = 25oC

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

VGS = 4.5V

VGS = 10V, ID = 7.5A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDS3672

Typical Characteristics T

1.4

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

A

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperatur e

5000

C

= CGS + C

ISS

1000

C

OSS

C

RSS

100

C, CAPACITANCE (pF)

V

GS

10

0.1 1 10 100

GD

≅ C

+ C

DS

GD

= C

GD

= 0V, f = 1MHz

VDS, DRAIN TO SOURCE VOLTAGE (V)

1.10 ID = 250µA

1.05

1.00

0.95

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.90

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 50V

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 5 10 15 20 25 30

Qg, GATE CHARGE (nC)

WAVEFORMS IN DESCENDING ORDER:

ID = 7.5A ID = 4A

Figure 13. Capacitance vs Drain to Sour ce

Voltage

Figure 14. Gat e Charge Waveforms for Constant

Gate Currents

Test Circuits and Waveforms

FDS3672

VARY tP TO OBTAIN REQUIRED PEAK I

V

GS

V

DS

L

I

AS

R

AS

G

+

V

DD

-

BV

DSS

t

P

V

DS

DUT

t

0V

P

I

AS

0.01Ω

0

t

AV

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

I

g(REF)

DS

L

V

GS

+

V

DD

-

DUT

V

DD

V

GS

V

= 2V

GS

Q

0

Q

g(TH)

I

g(REF)

gs2

Q

gs

Q

g(TOT)

V

DS

Q

gd

0

V

DD

V

= 10V

GS

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

90%

PULSE WIDTH

50%50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, P application. Therefore the application’s ambient temperature, T must be reviewed to ensure that T Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

DM

θJA

, in an

(oC/W)

serve s as the basis for establ ishing the rating of the part.

P

TJMTA–()

---------------- -------------- -=

DM

R

θJA

(EQ. 1)

In usin g surf ace m o unt d evic es s uch a s the SO8 pa ckag e, the env ironment in w hi ch it is appl ied will ha ve a significa nt influence on the part’s current and maximum power dissipation ratings. Precise determination of P and influenced by many factors:

is complex

DM

1. Mou nting pad area ont o which the device is attached and whet her the re is copp er on one s ide or both side s of the board.

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For no n steady state applic ations, th e pulse widt h, the duty cycle and the transient thermal response of the part, the boa rd and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 board w it h 1 oz c o pper af ter 1000 seconds of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice t hermal model or manually u tilizing the normaliz ed

150

COPPER BOARD AREA - DESCENDING ORDER

2

0.04 in

2

0.28 in

, THERMAL

θJA

Z

120

C/W)

o

90

60

IMPEDANCE (

30

0.52 in

0.76 in

1.00 in

2 2 2

maximum transient thermal impedance curve. Therma l resistan ces corres ponding to other co pper areas

can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.

R

The tr ansi ent t her mal i mp eda nce (Z varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas.

Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RT HER M 5 re main co ns ta nt fo r ea ch of th e th erm al models . A li sti ng of th e m od el comp one nt v alue s i s ava i labl e in Table 1.

64

θJA

200

150

C/W)

o

(

θJA

R

100

50

0.001 0.01 0.1 1 10

26

-------------------------------+=

0.23 Area+

θJA

R

θJA

AREA, TOP COPPER AREA (in2)

(EQ. 2)

) is also e ffect ed by

= 64 + 26/(0.23+Area)

Figure 21. Thermal Resistance vs Mounting

Pad Area

FDS3672

0

-1

10

0

10

t, RECTANGULAR PULSE DURATION (s)

1

10

2

10

3

10

Figure 22. Thermal Impedance vs Mount ing Pad Area

PSPICE Electrical Mod el

.SUBCKT FDS 3672 2 1 3 ; rev October 2002 Ca 12 8 6.0e-10 Cb 15 14 7.4e-10 Cin 6 8 2.0e-9

Dbod y 7 5 DbodyMOD Dbreak 5 11 Db reakMOD Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 107 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1

It 8 17 1 Lgat e 1 9 5.61e-9

Ldrain 2 5 1.0e -9 Lsource 3 7 1.98e-9

RLgate 1 9 56.1 RLdr ai n 2 5 10 RLsource 3 7 19.8

Mmed 16 6 8 8 M m edMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 0.4e-2 Rgate 9 20 1.40 RSLC1 5 51 RSL CM OD 1.0e-6 RSLC2 5 50 1.0e 3 Rsource 8 7 RsourceMOD 1.3e-2 Rvthres 22 8 RvthresMO D 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BM OD S2a 6 15 14 13 S2AM OD S2b 13 15 14 13 S2BM OD

Vbat 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

-

18 22

20

S1A

12

13814

S1B

EGS EDS

FDS3672

17 18

-

7

+

RVTEMP 19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

DPLCAP

10

RSLC2

6

8

EVTHRES

+

6

S2A

13

S2B

13

+

6 8

-

5

RSLC1

51

+

5

ESLC

51

50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5 8

-

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

+

ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5, 51)))*(PWR (V(5,51)/(1e-6*110), 3))} .MODEL DbodyMOD D (IS=5.0E-11 N=1.13 RS=4.4e-3 TRS1=2.0e-3 TRS2=1.0e-6

+ CJO=1.4e-9 M= 0.58 TT=4.0e- 8 X T I=4.2) .MODEL DbreakMOD D (RS=0.38 TRS1=2. 0e-3 TRS2=-8. 9e-6) .MODEL DplcapMOD D (CJO=4.9e-10 IS=1.0e-30 N=10 M=0.6)

.MODEL Mstro M OD NMOS (VTO=4.05 K P=90 lambda=0.02 IS=1e-30 N=1 0 T OX = 1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=3.35 KP=6.0 IS=1e-30 N=10 TOX =1 L=1u W=1u RG=1.40) .MODEL Mwe akMOD NMOS (VTO=2.76 KP=0. 05 IS=1e-30 N= 10 T OX = 1 L=1u W=1u RG=1.40e+1 RS=0.1 )

.MODEL RbreakMOD RES (TC1=8.5e-4 TC2=-25.0e-7) .MODEL Rd rai nMOD RES (TC1=1.5e-2 TC 2=5. 5e-5) .MODEL RSLCMOD RES (TC1=1.0e-3 TC2=1.0e-6) .MODEL RsourceMOD RES (TC1=4e-3 TC2=1 e-6) .MODEL RvthresMOD RES (TC1=-3.4e -3 T C2=-1.7e-5) .MODEL RvtempMOD RES (T C1=-4.4e-3 TC2=2.2e-6)

.MODEL S1AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 4 VOFF =-1 .5 ) .MODEL S1BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 1.5 VO FF=- 4) .MODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 1 VOFF =0.5) .MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= 0 .5 VOFF= -1)

.ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by Wil liam J. Hepp and C. F rank Wheatley.

SABER Electrical Model

REV October 2002 template FDS3672 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=5.0e-11,nl=1.13,rs=4.4e-3,trs1=2.0e-3,trs2=1.0e-6,cjo=1.4e-9,m=0.58,tt=4.0e-8,xti=4.2) dp..model dbreakmod = (rs=0. 38,trs1=2.0 e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=4.9e-10,isl=10.0e-30,nl=10,m=0.6) m..model mstrongmod = (type=_n,vto=4.05,kp=90,lambda=0.02,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=3.35,kp=6.0,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.76,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0.1,von=-4,voff = -1.5) sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0.1,von=-1.5,vof f=-4) sw_vcsp.. mo del s2amod = (ron=1e-5,roff=0.1,von=-1,voff =0.5) sw_vcsp.. mo del s2bmod = (ron=1e-5,roff=0.1,von=0.5,vof f=-1) c.ca n12 n8 = 6.0e -10 c.cb n15 n14 = 7.4e-10 c.cin n6 n8 = 2.0e -9

dp.dbody n7 n5 = model=dbodym od dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplca pm od

spe.ebreak n11 n7 n17 n18 = 107 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1

GATE

spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1

LGATE

1

RLGATE

9

RGATE

ESG

EVTEMP

+

18 22

20

spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1

CA

S1A

12

S1B

l.lgate n1 n9 = 5.61e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 1.98e-9

res.rlgate n1 n9 = 56.1 res.rldrai n n2 n5 = 10 res.rlsource n3 n7 = 19.8

m.mmed n16 n6 n8 n8 = m odel=mmedm od, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l= 1u, w=1u m.mweak n16 n21 n8 n8 = model=mwea kmod, l=1u, w=1u

DPLCAP

10

RSLC2

6

8

EVTHRES

+

19

6

-

S2A

13814

13

S2B

13

+

6

EGS EDS

8

-

5

RSLC1

51

ISCL

8

MMED

8

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

50 RDRAIN

16

21

-

8

MSTRO

CIN

15

CB

14

+

5 8

-

RLDRAIN

DBODY

+

17 18

LSOURCE

7

RLSOURCE

RVTEMP 19

VBAT

+

22

LDRAIN

DRAIN

2

SOURCE

3

FDS3672

res.rbreak n17 n18 = 1, tc1=8.5e- 4,tc2=-25.0 e-7 res.rdrain n50 n16 = 0.4e-2, tc1=1.5e-2,tc2 =5.5e-5 res.rgate n9 n20 = 1.40 res.rslc1 n5 n51 = 1.0e-6, tc1=1. 0e-3,tc2=1. 0e-6 res.rslc2 n5 n50 = 1.0e3 res.rsour ce n8 n7 = 1.3e-2, tc1= 4e-3,tc2=1e- 6 res.rvthres n22 n8 = 1, tc1=-3.4e-3,tc2=-1. 7e-5 res.rvtemp n18 n19 = 1, tc1=-4.4e-3,tc2=2.2e-6 sw_vcsp.s1 a n6 n12 n13 n8 = model= s1amod sw_vcsp.s1 b n13 n12 n13 n8 = model = s1 bm od sw_vcsp.s2 a n6 n15 n14 n13 = model = s2 am od sw_vcsp.s2 b n13 n15 n14 n13 = model =s2bmod

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*(( abs(v(n5,n51)*1e6/110 ))** 3)) }

FDS3672

SPICE Thermal Model

REV Aug 2002 FDS3692 Copper Area =1.0 in

2

CTHERM1 TH 8 2e-3 CTHERM2 8 7 5e-3 CTHERM3 7 6 1e-2 CTHERM4 6 5 4e-2 CTHERM5 5 4 9e-2 CTHERM6 4 3 2e-1 CTHERM7 3 2 1 CTHERM8 2 T L 3

RTHERM1 TH 8 1e-1 RTHERM2 8 7 5e-1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 13 RTHERM7 3 2 19 RTHERM8 2 TL 29.7

SABER Thermal Model

Copper Area = 1. 0 i n template thermal_model th tl thermal_ c th , tl { ctherm.c th erm 1 th 8 =2e-3 ctherm.ctherm2 8 7 =5e-3 ctherm.ctherm3 7 6 =1e-2 ctherm.ctherm4 6 5 =4e-2 ctherm.ctherm5 5 4 =9e-2 ctherm.ctherm6 4 3 =2e-1 ctherm7 3 2 1 ctherm8 2 tl 3

rtherm.rtherm1 th 8 =1e-1 rtherm.rt he rm2 8 7 =5e-1 rtherm.rt herm3 7 6 =1 rtherm.rt herm4 6 5 =5 rtherm.rt herm5 5 4 =8 rtherm.rt herm6 4 3 =13 }

2

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

JUNCTION

th

CTHERM1

8

CTHERM2

7

CTHERM3

6

CTHERM4

5

CTHERM5

4

CTHERM6

3

CTHERM7

2

CTHERM8

tl

CASE

TABLE 1. THERMAL MODELS

COMPONANT 0.04 in

2

0.28 in

2

0.52 in

2

0.76 in

2

1.0 in

2

CTHERM6 3.2e-1 3.5e-1 4.0e-1 4.0e-1 4.0e-1 CTHERM7 8.5e-1 9.0e-1 9.0e-1 9.0e-1 9.0e-1 CTHERM8 0.3 1.8 2.0 2.0 2.0 RTHERM6 24 18 12 10 9 RTHERM7 36 21 18 16 15 RTHERM8 53 37 30 28 23

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2

E

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2

I

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PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Adva nce Information Formative or I n

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Production This datasheet contains specifications on a product

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

supple m entary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Semiconductor reserves the righ t to make chan ges at any time without notice in order to improve design.

that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. I2