Datasheet FDS3572 Datasheet (Fairchild)

FDS3572

N-Channel PowerTrench® MOSFET
80V, 8.9A, 16mΩ

FDS3572

November 2003

Features

•r

•Q

• Low Miller Charge

•Low Q

= 14mΩ (Typ.), V

DS(ON)

= 31nC (Typ.), V

g(tot)

Body Diode

RR

= 10V, ID = 8.9A

GS

= 10V

GS

Applications

• Primary switch for Isolated DC/DC converters

• Distributed Power and Intermediate Bus Architectures

• High Voltage Synchronous Rectifier for DC Bus
Converters

• Optimized efficiency at high frequencies

• UIS Capability (Single Pulse and Repetitive Pulse)

Formerly developmental type 82663

Branding Dash

5

1

2

3

4

5

6

7

8

SO-8

MOSFET Maximum Ratings T

Symbol Parameter Ratings Units

V

DSS

V

GS

I

D

E

AS

P

D

, T

T

J

STG

Drain to Source Voltage 80 V

Gate to Source Voltage ±20 V

Drain Current

Continuous (T

Continuous (T

= 25oC, VGS = 10V, R

A

= 100oC, VGS = 10V, R

A

Pulsed Figure 4 A

Single Pulse Avalanche Energy (Note 1) 515 mJ

Power dissipation 2.5 W

o

Derate above 25

C20mW/

Operating and Storage Temperature -55 to 150

= 25°C unless otherwise noted

A

= 50oC/W)

θJA

= 50oC/W) 5.6 A

θJA

8.9 A

4

3

2

1

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

Thermal Resistance, Junction to Case (Note 2) 25

Thermal Resistance, Junction to Ambient at 10 seconds (Note 3) 50

Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3) 85

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDS3572 FDS3572 SO-8 330mm 12mm 2500 units

©2003 Fairchild Semiconductor Corporation

o

C/W

o

C/W

o

C/W

FDS3572 Rev. A

FDS3572

Electrical Characteristics T

= 25°C unless otherwise noted

A

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B

I

DSS

I

GSS

VDSS

Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 80 - - V

V

= 60V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TA = 150oC- - 250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

Drain to Source On Resistance

= 8.9A, V

I

D

I

= 5.6A, VGS = 6V - 0.019 0.029

D

I

= 8.9A, V

D

T

= 150oC

A

= 10V - 0.014 0.016

GS

= 10V,

GS

- 0.027 0.032

Dynamic Characteristics

C

C

C

Q

Q

Q

Q

Q

ISS

OSS

RSS

g(tot)

g(TH)

gs

gs2

gd

Input Capacitance

Output Capacitance - 320 - pF

Reverse Transfer Capacitance - 85 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total Gate Charge at 10V VGS = 0V to 10V

Threshold Gate Charge VGS = 0V to 2V - 4 5.2 nC

Gate to Source Gate Charge - 9 - nC

Gate Charge Threshold to Plateau - 5 - nC

V

DD

= 8.9A

I

D

= 1.0mA

I

g

= 40V

Gate to Drain “Miller” Charge - 7.5 - nC

- 1990 - pF

-3141nC

µA

Ω

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time

Turn-On Delay Time - 13 - ns

Rise Time - 14 - ns

Turn-Off Delay Time - 31 - ns

Fall Time - 13 - ns

Turn-Off Time - - 67 ns

(VGS = 10V)

= 40V, ID = 8.9A

V

DD

= 10V, RGS = 10Ω

V

GS

- - 40 ns

Drain-Source Diode Characteristics

I

= 8.9A - - 1.25 V

V

SD

t

rr

Q

RR

Notes:
1: Starting TJ = 25°C, L = 21mH, IAS = 7A.
2: R

θJA

drain pins . R

3: R

θJA

Source to Drain Diode Voltage

Reverse Recovery Time ISD= 8.9A, dISD/dt= 100A/µs- - 50 ns

Reverse Recovered Charge ISD= 8.9A, dISD/dt= 100A/µs- - 70nC

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the

is measured with 1.0 in2 copper on FR-4 board

is guaranteed by design while R

θJC

is determined by the user’s board design.

θJA

SD

= 4.3A - - 1.0 V

I

SD

©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A

FDS3572

Typical Characteristics T

= 25°C unless otherwise noted

A

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

1

0.5

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

0.01

θJA

Z

THERMAL IMPEDANCE

0.001

-5

10

SINGLE PULSE

-4

10

-3

10

10

8

6

4

, DRAIN CURRENT (A)

D

I

2

R

=50oC/W

θJA

125

0

25 50 75 100 125 150

Figure 2. Maximum Continuous Drain Current vs

-2

10

t, RECTANGULAR PULSE DURATION (s)

-1

10

10

TA, AMBIENT TEMPERATURE (oC)

Ambient Temperature

P

DM

NOTES:
DUTY FACTOR: D = t1/t

0

PEAK TJ = PDM x Z

1

10

θJA

V

= 10V

GS

R

=50oC/W

θJA

t

1

t

2

2

x R

+ T

θJA

A

2

10

3

10

Figure 3. Normalized Maximum Transient Thermal Impedance

1000

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

VGS = 10V

100

, PEAK CURRENT (A)

DM

I

10

5

-5

10

-4

10

-3

10

-2

10

t, PULSE WIDTH (s)

-1

10

0

10

TA = 25oC

FOR TEMPERATURES

o

ABOVE 25
CURRENT AS FOLLOWS:

1

10

I = I

25

C DERATE PEAK

150 - T

A

125

2

10

3

10

Figure 4. Peak Current Capability

©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A

Typical Characteristics T

= 25°C unless otherwise noted

A

FDS3572

50

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

10

, AVALANCHE CURRENT (A)

AS

I

STARTING TJ = 150oC

1

0.1

1 10 100

tAV, TIME IN AVALANCHE (ms)

DSS

- VDD)

DSS

- VDD) +1]

STARTING TJ = 25oC

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 5. Unclamped Inductive Switching

Capability

20

VGS = 10V

15

10

VGS = 6V

VGS = 5V

VGS = 4.5V

20

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 15V

V

DD

15

TJ = 150oC

10

, DRAIN CURRENT (A)

D

I

TJ = 25oC

5

0

3.0 3.5 4.0 4.5 5.0 5.5

VGS, GATE TO SOURCE VOLTAGE (V)

TJ = -55oC

Figure 6. Transfer Characteristics

20

18

16

VGS = 6V

, DRAIN CURRENT (A)

D

I

5

0

0 0.25 0.5 0.75 1.0

VDS, DRAIN TO SOURCE VOLTAGE (V)

TA = 25oC

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

14

DRAIN TO SOURCE ON RESISTANCE (m Ω)

12

0246810

VGS = 10V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

ID, DRAIN CURRENT (A)

Figure 7. Saturation Characteristics Figure 8. Drain to Source On Resistance vs Drain

Current

2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160

TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 8.9A

Figure 9. Normalized Drain to Source On

Resistance vs Junction Temperature

1.2

1.1

1.0

0.9

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.7

0.6

-80 -40 0 40 80 120 160

TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

Figure 10. Normalized Gate Threshold Voltage vs

Junction Temperature

©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A

FDS3572

Typical Characteristics T

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160

TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

A

Figure 11. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 40V

8

6

5000

C

= CGS + C

ISS

1000

C

OSS

C

RSS

100

C, CAPACITANCE (pF)

V

GS

10

0.1 1 10

GD

≅ C

+ C

DS

GD

= C

GD

= 0V, f = 1MHz

VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 12. Capacitance vs Drain to Source

Voltage

80

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 102030

Qg, GATE CHARGE (nC)

WAVEFO RM S I N
DESCENDING ORDER:

ID = 8.9A
ID = 1A

40

Figure 13. Gate Charge Waveforms for Constant Gate Currents

©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A

Test Circuits and Waveforms

FDS3572

VAR Y tP TO OBTAIN

REQUIRED PEAK I

V

GS

V

DS

L

I

AS

R

AS

G

+

V

DD

-

BV

DSS

t

P

V

DS

DUT

t

0V

P

I

AS

0.01Ω

0

t

AV

Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Waveforms

V

DS

I

g(REF)

V

DD

L

V

GS

DUT

+

V

DD

-

V

GS

0

I

g(REF)

= 2V

Q

gs2

Q

g(TH)

Q

gs

Q

g(TOT)

V

DS

Q

gd

V

GS

0

Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms

V

DD

V

= 10V

GS

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

t

d(OFF)

90%

t

OFF

t

f

90%

10%

50%

Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms

©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and

(oC), and thermal resistance R

A

is never exceeded.

JM

DM

θJA

, in an

(oC/W)

serves as the basis for establishing the rating of the part.

P

-------------------------------=

DM

TJMTA–()

R

θJA

(EQ. 1)

In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
and influenced by many factors:

is complex

DM

1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized

150

COPPER BOARD AREA - DESCENDING ORDER

2

0.04 in

2

0.28 in

, THERMAL

θJA

Z

120

C/W)

o

90

60

IMPEDANCE (

30

0.52 in

0.76 in

1.00 in

2

2

2

maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.

R

The transient thermal impedance (Z
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.

Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.

64

θ JA

200

150

C/W)

o

(

θJA

R

100

50

0.001 0.01 0.1 1 10

26

+=

------------- ------------------

0.23 Area+

AREA, TOP COPPER AREA (in2)

) is also effected by

θJA

R

= 64 + 26/(0.23+Area)

θJA

(EQ. 2)

Figure 21. Thermal Resistance vs Mounting

Pad Area

FDS3572

0

-1

10

0

10

t, RECTANGULAR PULSE DURATION (s)

1

10

2

10

3

10

Figure 22. Thermal Impedance vs Mounting Pad Area

©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A

PSPICE Electrical Model

.SUBCKT FDS3572 2 1 3 ; rev November 2003
Ca 12 8 7e-10
Cb 15 14 7e-10
Cin 6 8 1.9e-9

Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 86.6
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1

Lgate 1 9 1e-9
Ldrain 2 5 1e-9
Lsource 3 7 0.1e-9

RLgate 1 9 10
RLdrain 2 5 10
RLsource 3 7 1

Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 5.5e-3
Rgate 9 20 1.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 5.5e-3
Rvthres 22 8 Rvthresmod 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP
+

-

18
22

20

S1A

12

13814

S1B

EGS EDS

-

13

10

6
8

+

+

RSLC2

6

S2A

13

S2B

6
8

-

-

DPLCAP

EVTHRES

+

19

8

CIN

15

CB

-

+

-

5

RSLC1

51

5

51

­50

RDRAIN

21

MSTRO

14

5
8

+

ESLC

16

8

MMED

8

DBREAK

11

+

17

EBREAK

18

-

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHR ES

7

+

RVT EMP

19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDS3572

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),2.5))}

.MODEL DbodyMOD D (IS=4.5E-12 RS=4.7e-3 TRS1=1.5e-3 TRS2=2e-5 XTI=3 CJO=1.4e-9 TT=3e-08 M=0.55)
.MODEL DbreakMOD D (RS=2.5 TRS1=1e-4 TRS2=1e-6)
.MODEL DplcapMOD D (CJO=4.6e-10 IS=1e-30 N=10 M=0.5)

.MODEL MmedMOD NMOS (VTO=3.35 KP=3 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.3 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=3.9 KP=60 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=2.88 kp=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13 RS=0.1 T_ABS=25)

.MODEL RbreakMOD RES (TC1=1e-3 TC2=-7.5e-7)
.MODEL RdrainMOD RES (TC1=4.8e-3 TC2=3e-5)
.MODEL RSLCMOD RES (TC1=2.4e-2 TC2=1e-7)
.MODEL RsourceMOD RES (TC1=1e-2 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-4.4e-3 TC2=-1.4e-5)
.MODEL RvtempMOD RES (TC1=-4e-3 TC2=2e-7)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-2.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-4.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0 VOFF=-0.5)

.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A

SABER Electrical Model

REV November 2003
template FDS3572 n2,n1,n3 =m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod = (isl=4.5e-12,rs=4.7e-3,trs1=1.5e-3,trs2=2e-5,xti=3,cjo=1.4e-9,tt=3e-08,m=0.55)
dp..model dbreakmod = (rs=2.5,trs1=1e-4,trs2=1e-6)
dp..model dplcapmod = (cjo=4.6e-10,isl=10e-30,nl=10,m=0.5)
m..model mmedmod = (type=_n,vto=3.35,kp=3,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=3.9,kp=60,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.88,kp=0.04,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.0,voff=-2.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-4.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0,voff=-0.5)
c.ca n12 n8 = 7e-10
c.cb n15 n14 = 7e-10
c.cin n6 n8 = 1.9e-9

dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 86.6
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1

GATE

1

spe.esg n6 n10 n6 n8 = 1

LGATE

9

RLGATE

RGATE

ESG

EVTEMP

+

18
22

20

spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1

l.lgate n1 n9 = 1e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 0.1e-9

res.rlgate n1 n9 = 10

CA

S1A

12

S1B

res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 1

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

+

19

8

6

-

S2A

13814

13

S2B

13

+

+

6

EGS EDS

8

-

-

5

RSLC1

51

ISCL

MMED

DBREAK

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHR ES

50

RDRAIN

16

21

-

MSTRO

CIN

15

CB

8

14

+

5
8

-

FDS3572

LDRAIN

RLDRAIN

11

+

17
18

­7

RVT EMP

19

-

+

22

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

res.rbreak n17 n18 = 1, tc1=1e-3,tc2=-7.5e-7
res.rdrain n50 n16 = 5.5e-3, tc1=4.8e-3,tc2=3e-5
res.rgate n9 n20 = 1.3
res.rslc1 n5 n51 = 1e-6, tc1=2.4e-2,tc2=1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 5.5e-3, tc1=1e-2,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-4.4e-3,tc2=-1.4e-5
res.rvtemp n18 n19 = 1, tc1=-4e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 2.5))

}
}

©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A

FDS3572

SPICE Thermal Model

REV Nov 2003
FDS3572
Copper Area =1.0 in

2

CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
CTHERM8 2 TL 3

RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25

SABER Thermal Model

Copper Area = 1.0 in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3

rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}

2

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

JUNCTION

th

CTHERM1

8

CTHERM2

7

CTHERM3

6

CTHERM4

5

CTHERM5

4

CTHERM6

3

CTHERM7

2

CTHERM8

tl

CASE

TABLE 1. THERMAL MODELS

COMPONANT 0.04 in

2

0.28 in

2

0.52 in

2

0.76 in

2

1.0 in

2

CTHERM6 1.2e-1 1.5e-1 2.0e-1 2.0e-1 2.0e-1

CTHERM7 0.5 1.0 1.0 1.0 1.0

CTHERM8 1.3 2.8 3.0 3.0 3.0

RTHERM6 26 20 15 13 12

RTHERM7 39 24 21 19 18

RTHERM8 55 38.7 31.3 29.7 25

©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx™
ActiveArray™
Bottomless™
CoolFET™
CROSSVOL T™
DOME™
EcoSPARK™
E2CMOS
EnSigna

TM

TM

FACT™

FACT Quiet Series™



FAST
FASTr™

FPS™

FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
I2C™
ImpliedDisconnect™

Across the board. Around the world.™
The Power Franchise™
Programmable Active Droop™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE T O ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY , FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT

CONVEY ANY LICENSE UNDER ITS PA TENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

ISOPLANAR™

LittleFET™

MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC
OPTOPLANAR™
P ACMAN™



POP™

Power247™

PowerTrench



QFET
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
SILENT SWITCHER
SMART ST ART™
SPM™
Stealth™



SuperFET™

SuperSOT™-3

SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic



TINYOPTO™
TruTranslation™
UHC™



UltraFET



VCX™

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.

PRODUCT STA TUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Formative or
In Design

First Production

Full Production

2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or

effectiveness.

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. I7