Datasheet FDS2572 Datasheet (Fairchild Semiconductor)

G

FDS2572

150V, 0.047 Ohms, 4.9A, N-Channel UltraFET® Trench MOSFET

FDS2572

October 2001

General Description

UltraFET® devices combine characteristics that enable benchmark efficiency in power conversion applications. Optimized for Rds(on), low ESR, low total and Miller gate charge, these devices are ideal for high frequency DC to DC converters.

Applications

• DC/DC converters

• Telecom and Data-Com Distributed Power Architectures

• 48-volt I/P Half-Bridge/Full-Bridge

• 24-volt Forward and Push-Pull topologies

D

SO-8

S

SO-8

Pin 1

MOSFET Maximum Ratings T

Symbol Parameter Ratings Units

V

DSS

V

GS

I

D

P

D

TJ, T

STG

Drain to Source Voltage 150 V Gate to Source Voltage ±20 V Drain Current Continuous (TC = 25oC, VGS = 10V, R Continuous (TC = 100oC, VGS = 10V, R Pulsed Figure 4 A Power dissipation

Derate above 25oC Operating and Storage Temperature -55 to 150

S

=25°C unless otherwise noted

A

θJA

Features

• R

• Q

• Low QRR Body Diode

• Maximized efficiency at high frequencies

• UIS Rated

G

= 0.040Ω (Typ.), V

DS(ON)

= 29nC (Typ.), V

g(TOT)

= 10V

GS

= 10V

GS

5 6 7

4 3 2

S

8

= 50 oC/W)

= 50 oC/W) 3.1 A

θJA

4.9 A

2.5 20

1

W

mW/oC

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

Thermal Resistance Junction to Case (NOTE1) 25 Thermal Resistance Junction to Case at 10 seconds (NOTE2) 50 Thermal Resistance Junction to Case at steady state (NOTE2) 85

o

C/W

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Reel Size Tape Width Quantity

FDS2572 FDS2572 330mm 12mm 2500units

FDS2572 Rev. B, October 2001

FDS2572

Electrical Characteristics T

= 25°C unless otherwise noted

A

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B I

DSS

I

GSS

VDSS

Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 150 - - V Zero Gate Voltage Drain Current

VDS = 120V - - 1 VGS = 0V TC = 150

o

- - 250

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 2 - 4 V Drain to Source On Resistance ID = 4.9A, VGS = 10V - 0.040 0.047 Ω Drain to Source On Resistance ID = 4.9A, VGS = 6V - 0.044 0.053 Ω

Dynamic Characteristics

C

ISS

C

OSS

C

RSS

Q

g(TOT)

Q

g(TH)

Q

gs

Q

gd

Q

gs2

Input Capacitance Output Capacitance - 220 - pF Reverse Transfer Capacitance - 48 - pF

VDS = 25V, VGS = 0V, f = 1MHz

Total Gate Charge at 10V VGS= 0V to 10V Threshold Gate Charge VGS = 0V to 2V - 4 6 nC Gate to Source Gate Charge - 8 - nC Gate to Drain “Miller” Charge - 6 - nC

VDD = 75V ID = 4.9A Ig = 1.0mA

- 2050 - pF

- 29 38 nC

Gate Charge Threshold to Plateau - 4 - nC

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time

- - 27 ns Turn-On Delay Time - 14 - ns Rise Time - 4 - ns Turn-Off Delay Time - 44 - ns

VDD = 75V, ID = 4.9A

VGS = 10V, RG = 10Ω Fall Time - 22 - ns Turn-Off Time - - 100 ns

µA

Drain-Source Diode Characteristics

I

= 4.9A - - 1.25 V

V

SD

t

rr

Q

RR

Notes:

1. R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal referance is defined as the solder mounting surface of the

θJA

drain pins. R

2. R

is measured with 1.0in2 copper on FR-4 board

θJA

Source to Drain Diode Voltage Reverse Recovery Time ISD = 4.9A, dISD/dt =100A/µs - - 72 ns

Reverse Recovered Charge ISD = 4.9, dISD/dt =100A/µs - - 158 nC

is guaranteed by design while R

θJC

is determined by the user’s board design.

θCA

SD

ISD = 3.1A - - 1.0 V

Typical Characteristic

FDS2572

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

125

TA, AMBIENT TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

1

0.5

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJA

0.01

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.001

-5

10

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

6

VGS = 10V

4

2

, DRAIN CURRENT (A)

D

I

0

25 50 75 100 125 150

TC, CASE TEMPERATURE (oC)

Figure 2. Maximum Continous Drain Current vs

Case Temperature

P

DM

t

1

t

x R

2

+ T

θJA

A

2

10

3

10

NOTES: DUTY FACTOR: D = t1/t

PEAK TJ = PDM x Z

-2

-1

10

0

10

θJA

1

Figure 3. Normalized Maximum Transient Thermal Impedance

600

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

100

VGS = 10V

10

, PEAK CURRENT (A)

DM

I

1

-5

10

-4

10

-3

10

-2

10

-1

10

0

10

t, PULSE WIDTH (s)

TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:

I = I

1

10

150 - T

25

125

2

10

C

3

10

Figure 4. Peak Current Capability

Typical Characteristic (Continued)

FDS2572

10

STARTING TJ = 25oC

STARTING TJ = 150oC

1

, AVALANCHE CURRENT (A)

If R = 0

AS

I

tAV = (L)(IAS)/(1.3*RATED BV If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BV

0.1

0.001 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms)

DSS

- VDD)

DSS

- VDD) +1]

Figure 5. Unclamped Inductive Switching

Capability

30

VGS = 10V

VGS = 6V

20

10

, DRAIN CURRENT (A)

D

I

0

0 0.5 1.0 1.5 2.0

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 4.5V

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

TC = 25oC

VGS = 5V

30

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

V

= 15V

DD

20

TJ = 25oC

10

, DRAIN CURRENT (A)

D

I

TJ = 150oC

TJ = -55oC

0

3 4 5 6

VGS, GATE TO SOURCE VOLTAGE (V)

Figure 6. Transfer Characteristics

2.5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 4.9A

Figure 7. Saturation Characteristics Figure 8. Normalized Drain to Source On

Resistance vs Junction Temperature

1.4

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

Figure 9. Normalized Gate Threshold Voltage vs

Junction Temperature

1.2 ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)

Figure 10. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

Typical Characteristic (Continued)

C

, CAPACITANCE (pF

)

FDS2572

5000

C

ISS

= CGS + C

1000

C

≅ C

OSS

C

= C

RSS

GD

100

V

= 0V, f = 1MHz

GS

10

0.1 1 10 150 VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 11. Capacitance vs Drain to Source

Voltage

Test Circuits and Waveforms

V

DS

L

VARY tP TO OBTAIN REQUIRED PEAK I

V

GS

AS

R

G

DUT

GD

VDD = 75V

8

10

+ C

DS

GD

6

4

WAVEFORMS IN

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 5 10 15 20 25 30 35

DESCENDING ORDER:

ID = 4.9A ID = 1A

Qg, GATE CHARGE (nC)

Figure 12. Gate Charge Waveforms for Constant

Gate Currents

BV

DSS

t

P

I

AS

+

V

DD

-

V

DS

V

DD

t

0V

P

I

AS

0.01Ω

0

t

AV

Figure 13. Unclamped Energy Test Circuit Figure 14. Unclamped Energy Waveforms

D1

V

I

g(REF)

DS

L

V

GS

+

V

DD

-

DUT

V

DD

Q

g(TOT)

V

DS

V

GS

V

= 2V

GS

Q

0

Q

g(TH)

I

g(REF)

gs2

Q

gs

Q

gd

0

Figure 15. Gate Charge Test Circuit Figure 16. Gate Charge Waveforms

GS

= 10V

Test Circuits and Waveforms (Continued)

FDS2572

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

t

Figure 17. Switching Time Test Circuit Figure 18. Switching Time Waveforms

d(OFF)

90%

t

OFF

t

f

90%

10%

50%

Thermal Resistance vs. Mounting Pad Area

150

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA (oC), and thermal resistance R TJM is never exceeded. Equation 1 mathematically

(oC/W) must be reviewed to ensure that

θJA

represents the relationship and serves as the basis for establishing the rating of the part.

P

TJMTA–()

-----------------------------=

DM

R

θJA

(EQ. 1)

In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of P is complex and influenced by many factors:

DM

1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board.

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 19 defines the R copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually

COPPER BOARD AREA - DESCENDING ORDER

2

0.04 in

2

0.28 in

120

C/W)

o

90

0.52 in

0.76 in

1.00 in

2 2 2

utilizing the normalized maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas can be obtained from Figure 19 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.

R

The transient thermal impedance (Z by varied top copper board area. Figure 20 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas.

Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.

64

θJA

200

150

C/W)

o

(

θJA

R

100

50

0.001 0.01 0.1 1 10

26

-----------------------------+=

0.23 Area+

θJA

R

= 64 + 26/(0.23+Area)

θJA

AREA, TOP COPPER AREA (in2)

(EQ. 2)

) is also effected

Figure 19. Thermal Resistance vs Mounting

Pad Area

FDS2572

, THERMAL

60

θJA

Z

IMPEDANCE (

30

0

-1

10

0

10

t, RECTANGULAR PULSE DURATION (s)

1

10

2

10

3

10

Figure 20. Thermal Impedance vs Mounting Pad Area

PSPICE Electrical Model

.SUBCKT FDS2572 2 1 3 ;rev August 2001 CA 12 8 8e-10 Cb 15 14 8e-10 Cin 6 8 2e-9

Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 157.4 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1

It 8 17 1 Lgate 1 9 5.61e-9

Ldrain 2 5 1.0e-9 Lsource 3 7 1.98e-9

RLgate 1 9 56.1 RLdrain 2 5 10 RLsource 3 7 19.8

Mstro 16 6 8 8 MstroMOD Mmed 16 6 8 8 MmedMOD Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.1e-2 Rgate 9 20 1.47 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 1.5e-2 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

EVTEMP +

18 22

20

S1A

12

13814

S1B

EGS EDS

FDS2572

7

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

RVTEMP 19

VBAT

DRAIN

2

SOURCE

3

DPLCAP

10

RSLC2

6

8

EVTHRES

+

6

-

S2A

13

S2B

13

+

6 8

-

5

RSLC1

51

+

5

ESLC

51

50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5 8

-

MMED

8

DBREAK

11

+

17

EBREAK

IT

18

-

MWEAK

RSOURCE

RBREAK

17 18

RVTHRES

Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*65),3))} .MODEL DbodyMOD D (IS=4e-11 N=1.131 RS=4.4e-3 TRS1=2e-3 TRS2=1e-6

+ CJO=1.44e-9 M=0.67 TT=7.4e-8 XTI=4.2) .MODEL DbreakMOD D (RS=0.38 TRS1=2e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=5e-10 IS=1e-30 N=10 M=0.7)

.MODEL MstroMOD NMOS (VTO=4.05 KP=85 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=3.35 KP=5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.47) .MODEL MweakMOD NMOS (VTO=2.76 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=14.7 RS=0.1)

.MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-3e-7) .MODEL RdrainMOD RES (TC1=1e-2 TC2=3e-5) .MODEL RSLCMOD RES (TC1=3e-3 TC2=1e-6) .MODEL RsourceMOD RES (TC1=4.5e-3 TC2=1e-6) .MODEL RvtempMOD RES (TC1=-5e-3 TC2=2e-6) .MODEL RvthresMOD RES (TC1=-3e-3 TC2=-1.4e-5)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-10 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-10) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=0.3) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.8) .ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

SABER Electrical Model

SOURCE

REV August 2001 template FDS2572 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=4e-11,nl=1.131,rs=4.4e-3,trs1=2e-3,trs2=1e-6,cjo=1.44e-9,m=0.67,tt=7.4e-8,xti=4.2) dp..model dbreakmod = (rs=0.38,trs1=2e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=5e-10,isl=10e-30,nl=10,m=0.7) m..model mstrongmod = (type=_n,vto=4.05,kp=85,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=3.35,kp=5,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.76,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-10,voff=-2) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-10) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.8,voff=0.3) sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.8) c.ca n12 n8 = 8e-10 c.cb n15 n14 = 8e-10 c.cin n6 n8 = 2e-9

dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 157.4

ESG

spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1

GATE

1

LGATE

RLGATE

RGATE

9

EVTEMP

+

20

i.it n8 n17 = 1 l.lgate n1 n9 = 5.61e-9

l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 1.98e-9

res.rlgate n1 n9 = 56.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 19.8

CA

S1A

12

S1B

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-3e-7 res.rdrain n50 n16 = 2.1e-2, tc1=1e-2,tc2=3e-5 res.rgate n9 n20 = 1.47 res.rslc1 n5 n51 = 1e-6, tc1=3e-3,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.5e-2, tc1=4.5e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-3e-3,tc2=-1.4e-5 res.rvtemp n18 n19 = 1, tc1=-5e-3,tc2=2e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/65))** 3)) }

DPLCAP

10

RSLC2

6

8

EVTHRES

+

6

-

18 22

S2A

13814

13

S2B

13

+

6

EGS EDS

8

-

5

RSLC1

51

ISCL

16

8

MMED

8

DBREAK

11

MWEAK

EBREAK

+

RSOURCE

RBREAK

17 18

IT

RVTHRES

17 18

7

50 RDRAIN

21

-

19

8

MSTRO

CIN

15

CB

14

+

5 8

-

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

RVTEMP 19

VBAT

+

22

DRAIN

2

3

FDS2572

SPICE Thermal Model

REV August 2001 FDS2572 Copper Area = 1 in

2

CTHERM1 TH 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 2.0e-1 CTHERM7 3 2 1 CTHERM8 2 TL 3

RTHERM1 TH 8 1.0e-1 RTHERM2 8 7 5.0e-1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERM8 2 TL 25

SABER Thermal Model

Copper Area = 1 in template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th c2 =2.0e-3 ctherm.ctherm2 c2 c3 =5.0e-3 ctherm.ctherm3 c3 c4 =1.0e-2 ctherm.ctherm4 c4 c5 =4.0e-2 ctherm.ctherm5 c5 c6 =9.0e-2 ctherm.ctherm6 c6 c7 =2.0e-1 ctherm.ctherm7 c7 c8 =1 ctherm.ctherm8 c8 tl =3

rtherm.rtherm1 th c2 =1.0e-1 rtherm.rtherm2 c2 c3 =5.0e-1 rtherm.rtherm3 c3 c4 =1 rtherm.rtherm4 c4 c5 =5 rtherm.rtherm5 c5 c6 =8 rtherm.rtherm6 c6 c7 =12 rtherm.rtherm7 c7 c8 =18 rtherm.rtherm8 c8 tl =25 }

2

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

RTHERM7

RTHERM8

JUNCTION

th

CTHERM1

8

CTHERM2

7

CTHERM3

6

CTHERM4

5

CTHERM5

4

CTHERM6

3

CTHERM7

2

CTHERM8

tl

CASE

TABLE 1. THERMAL MODELS

COMPONANT 0.04 in

2

0.28 in

2

0.52 in

2

0.76 in

2

1.0 in

2

CTHERM6 1.2e-1 1.5e-1 2.0e-1 2.0e-1 2.0e-1 CTHERM7 0.5 1.0 1.0 1.0 1.0 CTHERM8 1.3 2.8 3.0 3.0 3.0 RTHERM6 26 20 15 13 12 RTHERM7 39 24 21 19 18 RTHERM8 55 38.7 31.3 29.7 25

MS-012AA

8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE

FDS2572

E E

1

2

D

o

h x 45

L

0.060

1.52

0.155

4.0

0.275

7.0

MINIMUM RECOMMENDED FOOTPRINT FOR

SURFACE-MOUNTED APPLICATIONS

e

5 6

c

b

0o-8

0.050

0.024

0.6

1.27

A

1

SYMBOL

INCHES MILLIMETERS

MIN MAX MIN MAX

NOTES

A 0.0532 0.0688 1.35 1.75 -

A

0.004 0.0098 0.10 0.25 -

1

b 0.013 0.020 0.33 0.51 -

c 0.0075 0.0098 0.19 0.25 D 0.189 0.1968 4.80 5.00 2 E 0.2284 0.244 5.80 6.20 -

E

0.1497 0.1574 3.80 4.00 3

1

0.004 IN

0.10 mm

o

e 0.050 BSC 1.27 BSC H 0.0099 0.0196 0.25 0.50 L 0.016 0.050 0.40 1.27 4

NOTES:

1.All dimensions are within allowable dimensions of Rev. C of JEDEC MS-012AA outline dated 5-90.

2.Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.006 inches (0.15mm) per side.

3. Dimension “E1” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.010 inches (0.25mm) per side.

4.“L” is the length of terminal for soldering.

5.The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6.Controlling dimension:Millimeter.

7.Revision 8 dated 5-99.

MS-012AA

12mm TAPE AND REEL

COVER TAPE

GENERAL INFORMATION

1. 2500 PIECES PER REEL.

2. ORDER IN MULTIPLES OF FULL REELS ONLY.

3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.

1.5mm

DIA. HOLE

12mm

USER DIRECTION OF FEED

4.0mm

8.0mm

2.0mm

1.75mm

C

L

40mm MIN. ACCESS HOLE

330mm 50mm

18.4mm

13mm

12.4mm

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS EnSigna

TM

FACT™ FACT Quiet Series™

STAR*POWER is used under license

FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™



OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench



QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER

SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™



UltraFET

VCX™



DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Formative or In Design

First Production

Full Production

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. H4