Datasheet FDP2552 Datasheet (Fairchild)

FDB2552 / FDP2552

N-Channel PowerTrench® MOSFET 150V, 37A, 36mΩ

FDB25 52 / FDP2552

February 2012

Features

•r

•Q

• Low Miller Charge

•Low Q

= 32mΩ (Typ.), V

DS(ON)

(tot) = 39nC (Typ.), V

g

Body Diode

RR

= 10V, ID = 16A

GS

= 10V

GS

Applications

• DC/D C C onverters an d Of f- li ne UPS

• Distributed P ower Arc hitectures and VRMs

• Primary Switch for 24V and 48V Syst ems

• High Voltage Synchronous Rectifier

• UIS Capability (Single Pulse and Repetitive Pulse)

Formerly developmental type 82869

DRAIN

(FLANGE)

SOURCE

DRAIN

GA TE

TO-220AB

FDP SERIES

MOSFET Maximum Ratings T

GATE

SOURCE

TO-263AB

FDB SERIES

= 25°C unless otherwise not ed

C

DRAIN

(FLANGE)

D

G

S

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Source Voltage 150 V Gate to Source Voltage ±20 V Drain Curr e nt Continuous (T

I

D

Continuous (T Continuous (T

= 25oC, VGS = 10V)

C

= 100oC, VGS = 10V) 26 A

C

= 25oC, VGS = 10V) with R

amb

= 43oC/W 5 A

θJA

37 A

Pulsed Figure 4 A

E

AS

P

D

, T

T

J

STG

Single Pulse Avalanche Energy (Note 1) 390 mJ Power dissipation 150 W

o

Derate above 25

C1.0W/

Operating and Storage Temperature -55 to 175

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

Thermal Resistance Junction to Case TO-220, TO-263 1.0 Thermal Resistance Junction t o Ambient TO- 220, TO-263 (Note 2) 62 Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad ar ea 43

o

C/W

o

C/W

o

C/W

Rev. C

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDB2552 FDB2552 TO-263AB 330mm 24mm 800 units FDP2552 FDP2552 TO-220AB Tube N/A 50 units

FDB25 52 / FDP2552

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Con ditions Min Typ Max Units

Off Characteristics

B I

DSS

I

GSS

VDSS

Drain to Sou r c e Br ea k down Voltag e ID = 250µA, VGS = 0V 150 - - V

V

= 120V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- -250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

= 16A, VGS = 10V - 0.032 0.036

I

D

I

= 8A, VGS = 6V - 0.036 0.054

Drain to S ou r c e On Re si st ance

D

= 16A, VGS = 10V,

I

D

T

= 175oC

J

- 0.084 0.097

Dynamic Characteristics

C C C Q Q Q Q Q

ISS OSS RSS

g(TOT) g(TH) gs gs2 gd

Input Capacitance Output Capacitanc e - 285 - pF Reverse Transfer Capacitance - 55 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total Gate Charge at 10V VGS = 0V to 10V Threshold Gate Charge VGS = 0V to 2V - 5.2 6.8 nC Gate to Source Gate Charg e - 13.5 - nC Gate Charge Threshold to Plateau - 8.4 - nC

V

DD

I

= 16A

D

I

= 1.0m A

g

= 75V

Gate to Drain “Miller” Charge - 8.3 - nC

- 2800 - pF

39 51 nC

µA

Ω

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time Turn-On Delay Time - 12 - ns Rise Time - 29 - ns Turn-Off D elay Time - 36 - ns Fall Time - 29 - ns Turn-Off Time - - 97 ns

(VGS = 10V)

V

= 75V, ID = 16A

DD

V

= 10V, RGS = 8.2Ω

GS

- - 62 ns

Drain-Source Diode Characteristics

I

= 16A - - 1.25 V

V

SD

t

rr

Q

RR

Notes: 1: Starting TJ = 25°C, L = 7.8mH, IAS = 10A. 2: Pulse Width = 100s

Source to Drain Diode Voltage Reverse Recovery Time ISD = 16A, dISD/dt = 100A/µs- -90ns

Reverse Recovered Charge ISD = 16A, dISD/dt = 100A/µs - - 242 nC

SD

= 8A - - 1.0 V

I

SD

FDB25 52 / FDP2552

Typical Characteristics T

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

TC, CASE TEMPERATURE (oC)

= 25°C unless otherwise noted

C

125

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

40

30

20

, DRAIN CURRENT (A)

D

I

10

150

0

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Curr ent vs

-3

t, RECTANGULAR PULSE DURATION (s)

-2

10

TC, CASE TEMPERATURE (oC)

Case Temperature

P

DM

NOTES: DUTY FACTOR: D = t1/t PEAK TJ = PDM x Z

-1

10

θJC

10

0

x R

t

1

t

2

+ T

θJC

C

1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

700

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

VGS = 10V

100

, PEAK CURRENT (A)

DM

I

30

-5

10

-4

10

-3

10

-2

10

t, PULSE WIDTH (s)

-1

10

TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:

175 - T

I = I

25

10

C

150

0

1

10

Figure 4. Peak Current Capability

Typical Characteristics T

= 25°C unless otherwise noted

C

FDB25 52 / FDP2552

300

100

10

OPERATION IN THIS

AREA MAY BE

, DRAIN CURRENT (A)

D

I

LIMITED BY r

1

SINGLE PULSE TJ = MAX RATED

TC = 25oC

0.1 1 10 100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

10µs

100µs

1ms

10ms

DC

Figure 5. Forward Bias Safe Operating Area

80

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX V

= 15V

DD

60

40

TJ = 25oC

, DRAIN CURRENT (A)

D

I

20

TJ = 175oC

0

3.0 3.5 4.0 4.5 5.0 5.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V)

TJ = -55oC

100

If R = 0

300

tAV = (L)(IAS)/(1.3*RATED BV If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

10

, AVALANCHE CURRENT (A)

AS

I

1

STARTING TJ = 150oC

0.1 1 100.01

tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

80

VGS = 10V

60

VGS = 6V

40

VGS = 5V

, DRAIN CURRENT (A)

D

I

20

PULSE DURATION = 80µs

0

012345

VDS, DRAIN TO SOURCE VOLTAGE (V)

DUTY CYCLE = 0.5% MAX

TC = 25oC

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

42

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

40

38

36

34

32

DRAIN TO SOURCE ON RESISTANCE(mΩ)

30

0 10203040

VGS = 6V

VGS = 10V

ID, DRAIN CURRENT (A)

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

3.0

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

2.5

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 16A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDB25 52 / FDP2552

Typical Characteristics T

1.4

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

C

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperatur e

4000

C

= CGS + C

ISS

C

≅ C

+ C

OSS

DS

1000

C

RSS

C, CAPACITANCE (pF)

100

V

GS

10

0.1 1 10 150

GD

= C

GD

= 0V, f = 1MHz

VDS, DRAIN TO SOURCE VOLTAGE (V)

GD

1.2 ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

0.9

NORMALIZED DRAIN TO SOURCE

0.8

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 75V

8

6

4

, GATE TO SOURCE VOLTAGE (V)

2

GS

V

0

0 10203040

Qg, GATE CHARGE (nC)

WAVEFORMS IN DESCENDING ORDER:

ID = 37A ID = 16A

Figure 13. Capacitance vs Drain to Sour ce

Voltage

Figure 14. Gat e Charge Waveforms for Constant

Gate Currents

Test Circuits and Waveforms

V

DS

L

VARY tP TO OBTAIN REQUIRED PEAK I

V

GS

R

AS

G

+

V

DD

-

I

AS

DUT

t

0V

P

I

AS

0.01Ω

0

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

BV

DSS

t

P

t

AV

FDB25 52 / FDP2552

V

DS

V

DD

V

DS

I

g(REF)

V

DD

L

V

GS

DUT

+

V

DD

-

V

GS

0

I

g(REF)

= 2V

Q

gs2

Q

g(TH)

Q

gs

Q

g(TOT)

V

DS

Q

gd

V

0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

10%

PULSE WIDTH

GS

t

d(OFF)

V

= 10V

GS

t

OFF

t

f

90%

10%

90%

50%50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

80

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, P application. Therefore the application’s ambient temperature, T must be reviewed to ensure that T Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

serve s as the basis for establ ishing the rating of the part.

TJMTA–()

P

----------------- ------------=

DM

R

θJA

In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power d issipati on rating s. Precise d etermin ation of P comple x and influenced by many factors:

1. Mou nting pad area ont o which the device is attached and whet her the re is copp er on one s ide or both side s of the board.

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For no n steady state applic ations, th e pulse widt h, the duty cycle and the transient thermal response of the part, the boa rd and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 bo ar d with 1oz c opper af t er 1000 se c on ds of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice t hermal model or manu ally utilizin g the normal ized maximum transient thermal impedance curve.

DM

(oC/W)

θJA

(EQ. 1)

, in an

is

DM

60

C/W)

o

(

θJA

R

40

20

Figure 21. Thermal Resistance vs Mounting

R

= 26.51+ 19.84/(0.262+Area) EQ.2

θJA

R

= 26.51+ 128/(1.69+Area) EQ.3

θJA

(0.645) (6.45) (64.5)

AREA, TOP COPPER AREA in2 (cm2)

1100.1

Pad Area

FDB25 52 / FDP2552

Therma l resi stances correspondi ng to other copper are as can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inch es squ are and equ ation 3 is for area in cent imeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads.

19.84

26.51

=

R

θJA

=

θJA

26.51

R

-------------------------------------+

0.262 Area+()

Area in Inches Squared

128

----------------------------------+

1.69 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

PSPICE Electrical Model

.SUBCKT FDP 2552 2 1 3 ; rev May 20 02 Ca 12 8 1e-9 Cb 15 14 1e-9 Cin 6 8 2.65e-9

Dbod y 7 5 DbodyMOD Dbreak 5 11 Db reakMOD Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 178 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1

It 8 17 1 Lgat e 1 9 7.15e-9

Ldrain 2 5 1.0e -9 Lsou rce 3 7 2.3e-9

RLgate 1 9 71.5 RLdr ai n 2 5 10 RLsource 3 7 23

Mmed 16 6 8 8 M m edMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.5e-2 Rgate 9 20 1.04 RSLC1 5 51 RSL CM OD 1.0e-6 RSLC2 5 50 1.0e 3 Rsource 8 7 RsourceMOD 4.6e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BM OD S2a 6 15 14 13 S2AM OD S2b 13 15 14 13 S2BM OD Vbat 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

-

18 22

20

S1A

12

13814

S1B

EGS EDS

6

8

13

10

RSLC2

6

13

+

6 8

-

DPLCAP

EVTHRES

+

S2A

S2B

5

RSLC1

51

+

5

51

50

RDRAIN

21

-

19

8

MSTRO

CIN

15

CB

14

+

5 8

-

ESLC

16

8

MMED

8

DBREAK

11

+

17

EBREAK

IT

18

-

MWEAK

RSOURCE

RBREAK

17 18

RVTHRES

7

+

RVTEMP 19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB25 52 / FDP2552

ESLC 51 50 VALUE={(V(5,5 1)/ABS(V(5,51)))*(PWR (V (5,51)/(1e-6*75),3))} .MODEL DbodyMOD D (IS=2.6E-11 N=1.09 RS=2.6e-3 TRS1=3.0e-3 TRS2=1.5e-6

+ CJO=1.9e-9 M= 0.62 TT=5.1e-8 X T I=4.2) .MODEL DbreakMOD D (RS=0.3 TRS1=3.0e-3 TR S 2=-8.9e-6) .MODEL DplcapMOD D (CJO=5.7e-10 IS=1.0e-30 N=10 M=0.58)

.MODEL MmedMOD NMOS (VTO=3.5 KP=6 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.04) .MODEL Mstro M OD NMOS (VTO=4.15 KP=80 IS=1e-30 N=10 T OX = 1 L=1u W=1u) .MODEL Mwe akMOD NMOS (VTO=2.91 KP=0.03 IS=1e-30 N=10 TO X = 1 L=1u W=1u RG=10. 4 RS=0.1)

.MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-2e-6) .MODEL Rd rai nMOD RES (TC 1=8. 5 e-3 TC2=2.5e-5) .MODEL RSLCMOD RES (TC1=3.4e-3 TC2=1.5e-6) .MODEL RsourceMOD RES (TC 1=4.0e-3 TC2=1.0e-6) .MODEL RvthresMOD RES (TC1=-4.3e-3 TC 2=-1.6e-5) .MODEL RvtempMOD RES (T C1=-4.1e-3 TC 2=1. 5e-6)

.MODEL S1AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 6. 0 VOFF =-4 .0 ) .MODEL S1BMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 4. 0 VOFF =-6 .0 ) .MODEL S2AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 2 VOFF =-0 .5 ) .MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 0.5 VO FF=- 2)

.ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronic s S pecialist Conf erence Records, 1991, written by Wi l liam J. Hepp and C. Frank Wheatley.

SABER Electrical Model

REV May 2002 template FDP2552 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.6e-11,nl=1.09,rs=2.6e-3,trs1=3.0e-3,trs2=1.5e-6,cjo=1.9e-9,m=0.62,tt=5.1e-8,xti=4.2) dp..model dbreakmod = (rs=0.3, t rs1=3.0e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=5.7e-10,isl=10.0e-30,nl=10,m=0.58) m..model mmedmod = (type=_n,vto=3.5,kp=6,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.15,kp=80,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.91,kp=0.03,is=1e-30, tox=1,rs=0.1) sw_vcsp.. mo del s1amod = (ron=1e- 5,roff=0.1,vo n=-6.0,voff=-4 .0) sw_vcsp.. mo del s1bmod = (ron=1e- 5,roff=0.1,vo n=-4.0,voff=-6 .0) sw_vcsp.. mo del s2amod = (ron=1e- 5,roff=0.1,vo n=-2,voff=-0.5 ) sw_vcsp.. mo del s2bmod = (ron=1e- 5,roff=0.1,vo n=-0.5,voff=-2 ) c.ca n12 n8 = 1e- 9 c.cb n15 n14 = 1e- 9 c.cin n6 n8 = 2.65 e-9

dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreak m od dp.dplcap n10 n5 = model=dplca pm od

spe.ebreak n11 n7 n17 n18 = 178 spe.eds n14 n8 n5 n8 = 1

GATE

spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1

LGATE

1

RLGATE

9

RGATE

ESG

EVTEMP +

20

18 22

spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1 l.lgate n1 n9 = 7.15e-9

l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.3e-9

S1A

12

S1B

CA

res.rlgate n1 n9 = 71.5 res.rldrai n n2 n5 = 10 res.rlsource n3 n7 = 23

m.mmed n16 n6 n8 n8 = m odel=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=ms tr ongmod, l=1u, w=1 u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

DPLCAP

10

RSLC2

6

8

EVTHRES

+

19

8

6

-

S2A

14

13

8

S2B

13

+

6

EGS EDS

8

-

5

RSLC1

51

ISCL

8

MMED

8

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

50 RDRAIN

16

21

-

MSTRO

CIN

15

CB

14

+

5 8

-

RLDRAIN

DBODY

+

17 18

LSOURCE

7

RLSOURCE

RVTEMP 19

VBAT

+

22

LDRAIN

DRAIN

2

SOURCE

3

FDB25 52 / FDP2552

res.rbreak n17 n18 = 1, tc1=1.1e-3, tc 2=-2e-6 res.rdrain n50 n16 = 2.5e-2, tc1=8. 5e-3,tc2=2.5e-5 res.rgate n9 n20 = 1.04 res.rslc1 n5 n51 = 1.0e-6, tc1=3.4e-3,tc2=1.5e-6 res.rslc2 n5 n50 = 1.0e3 res.rsour ce n8 n7 = 4.6e-3, tc1=4. 0e-3,tc2=1.0e-6 res.rvthres n22 n8 = 1, tc1=-4.3e-3,tc2=-1.6e-5 res.rvtemp n18 n19 = 1, tc1=-4.1e-3,tc2=1.5e-6 sw_vcsp.s1 a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1 b n13 n12 n13 n8 = model= s1 bmod sw_vcsp.s2 a n6 n15 n14 n13 = model= s2 amod sw_vcsp.s2 b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5, n51)/(1e-9+abs (v(n5,n51))))*((abs(v(n5,n51)*1e6/ 75))** 3)) }

FDB25 52 / FDP2552

SPICE Thermal Model

REV 23 May 2002 FDP2552T CTHERM1 TH 6 1e-2

CTHERM2 6 5 1. 5e-2 CTHERM3 5 4 2e-2 CTHERM4 4 3 2. 1e-2 CTHERM5 3 2 2. 2e-2 CTHERM6 2 TL 9e-2

RTHERM1 TH 6 2.7e-2 RTHERM2 6 5 2. 8e-2 RTHERM3 5 4 7. 8e-2 RTHERM4 4 3 9e-2 RTHERM5 3 2 2. 7e-1 RTHERM6 2 TL 2.87e-1

SABER Thermal Model

SABER therm al m odel F DP2552T template thermal_model th tl thermal_ c th , tl { ctherm.c th erm 1 th 6 =1e-2 ctherm.ctherm2 6 5 =1.5e-2 ctherm.ctherm3 5 4 =2e-2 ctherm.ctherm4 4 3 =2.1e-2 ctherm.ctherm5 3 2 =2.2e-2 ctherm.ctherm6 2 tl =9e-2

rtherm.rtherm1 th 6 =2.7e-2 rtherm.rt herm2 6 5 =2.8e-2 rtherm.rt herm3 5 4 =7.8e-2 rtherm.rt he rm4 4 3 =9e-2 rtherm.rt herm5 3 2 =2.7e-1 rthe r m.rtherm6 2 tl =2.8 7e-1 }

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

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CTHERM1

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CTHERM3

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TRADEMARKS

The following includes registered and unregistered trademarks a nd service marks, owned by Fairch ild Semiconductor and/ or its global subsidiaries, and is n ot intended to be an exhaustive list of all such trademarks.

2Cool™ AccuPower™ AX-CAP™*

®

BitSiC Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ DEUXPEED Dual Cool™ EcoSPARK EfficentMax™

®

ESBC™

®

Fairchild Fairchild Semiconductor FACT Quiet Series™

®

FACT

®

FAST FastvCore™ FETBench™ FlashWriter

®

*

FPS™

®

F-PFS™

®

FRFET Global Power Resource Green Bridge™ Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ Marking Small Speakers Sound Louder and Better™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MicroPak2™ MillerDrive™ MotionMax™ Motion-SPM™ mWSaver™ OptoHiT™ OPTOLOGIC OPTOPLANAR

®

SM

PowerTrench PowerXS™ Programmable Active Droop™ QFET QS™ Quiet Series™ RapidConfigure™

Saving our world, 1mW/W/kW at a time™ SignalWise™ SmartMax™ SMART START™ Solutions for Your Success™ SPM STEALTH™ SuperFET SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS SyncFET™ Sync-Lock™

®

®*

The Power Franchise

TinyBoost™ TinyBuck™ TinyCalc™

®

TinyLogic TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™

®

TranSiC TriFault Detect™ TRUECURRENT μSerDes™

®

UHC Ultra FRFET™ UniFET™ VCX™ VisualMax™ VoltagePlus™ XS™

®

*

*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

FDB25 52 / FDP2552

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used here in:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the bo dy or (b ) support or su stain life, and (c) whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling, can be reasonably

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

expected to result in a significant injury of the user.

ANTI-COUNTERFEITING POLICY

Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are exper iencing counterfeiting of their

parts. Customers who inadvertently purchase counterfeit part s expe rience many problems such as loss of brand repu tation, substa ndar d pe rformance, fail ed application, and increased cost of production and manufacturing delays. Fairchild is taki ng st ron g measures to prote ct ourselves and our custo mers from the proliferation of counterfeit parts. Fairchild strongl y encourages customers t o purchase Fairchil d parts either d irectly from Fairchild o r from Authorized Fairchil d Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practi ce by buying direct or fr om authorized distributors.

PRODUCT STATUS DEFINITIONS Definition of Terms

.

Datasheet Identification Product Status Definition

Advance Information Formative / In Design

Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

Datasheet contains preliminary data; supplementa ry data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.

Rev. I61

FDB2552 / FDP2552 Rev. C