Datasheet FDB14AN06LA0, FDP14AN06LA0 Datasheet (Fairchild)

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FDB14AN06LA0 / FDP14AN06LA0

N-Channel PowerTrench® MOSFET 60V, 60A, 14.6mΩ

FDB14AN06LA0 / FDP14AN06LA0

January 2004

Features

•r

•Q

• Low Miller Charge

•Low Q

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

Formerly developmental type 83557

MOSFET Maximum Ratings T

= 12.8mΩ (Typ.), V

DS(ON)

(tot) = 24nC (Typ.), V

g

Body Diode

RR

DRAIN

(FLANGE)

= 5V, ID = 60A

GS

= 5V

GS

TO-220AB

FDP SERIES

SOURCE

DRAIN

GATE

= 25°C unless otherwise not ed

C

Applications

• Motor / Body Load Control

• ABS Systems

• Powertrain Management

• Injection Systems

• DC-DC converter s and Off-line UPS

• Distributed P ower Arc hitectures and VRMs

• Primary Switch for 12V and 24V systems

GATE

SOURCE

TO-263AB

FDB SERIES

DRAIN

(FLANGE)

D

G

S

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Sou r c e Voltage 60 V Gate to Source Voltage ±20 V Drain Curr e nt Continuous (T

I

D

Continuous (T Continuous (T

= 25oC, VGS = 10V)

C

= 25oC, VGS = 5V) 60 A

C

= 25oC, VGS = 5V, R

A

= 43oC/W) 10 A

θJA

67 A

Pulsed Figure 4 A

E

AS

P

D

, T

T

J

STG

Single Pulse Avalanche Energy (Note 1) 46 mJ Power dissipation 125 W

o

Derate above 25

C0.83W/

Operating and Storage T emperature -55 to 175

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

This product has been designed to meet the extreme test conditions an d environment dem anded by the au tomotive industry. For a

All Fairchild Semiconductor products are manufactu red, assembled and tested under ISO9000 and QS9000 quality systems

Thermal Resistance Junction to Case TO-220,TO-263 1.2 Thermal Resistance Junction to Ambient TO-220, TO-263 ( Note 2) 62 Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad ar ea 43

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be fou nd a t: http://ww w.f airc hilds e m i.co m /pr oduc ts/dis c rete/reliab ility/ind ex.html.

certification.

FDB14AN06LA0 / FDP14AN06LA0 Rev. B

o

C/W

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDB14AN06LA0 FDB14AN06LA0 TO-263AB 330mm 24mm 800 uni ts FDP14AN06LA0 FDP14A N06LA0 TO- 220AB Tube N/A 50 unit s

FDB14AN06LA0 / FDP14AN06LA0

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Con ditions Min Typ Max Units

Off Characteristics

B I

DSS

I

GSS

VDSS

Drain to Sou r c e Br ea k down Volt ag e ID = 250µA, VGS = 0V 60 - - V

V

= 50V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- -250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA1-3V

= 67A, VGS = 10V - 0.0102 0.0116

I

D

I

= 60A, VGS = 5V - 0.0128 0.0146

Drain to S ou r c e On Re si st ance

D

= 60A, VGS = 5V,

I

D

T

= 175oC

J

- 0.028 0.033

Dynamic Characteristics

C C C Q Q Q Q Q

ISS OSS RSS

g(TOT) g(TH) gs gs2 gd

Input Capacitance Output Capacitanc e - 270 - pF Reverse Transfer Capacitance - 115 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total Gate Charge at 5V VGS = 0V to 5V Threshold Gate Charge VGS = 0V to 1V - 3.0 3.9 nC Gate to Source Gate Charg e - 1 2 - nC Gate Charge Threshold to Plateau - 9.1 - nC

V

DD

I

= 60A

D

I

= 1.0m A

g

= 30V

Gate to Drain “Miller” Charge - 7.9 - nC

- 2900 - pF

24 31 nC

µA

Ω

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time Turn-On Delay Time - 15 - ns Rise Time - 169 - ns Turn-Off D elay Time - 24 - ns Fall Time - 50 - ns Turn-Off Time - - 109 ns

(VGS = 5V)

V

= 30V, ID = 60A

DD

V

= 5V, RGS = 5.1Ω

GS

--276ns

Drain-Source Diode Characteristics

I

= 60A - - 1.25 V

V

SD

t

rr

Q

RR

Notes: 1: Starting TJ = 25°C, L = 40µH, IAS = 48A. 2: Pulse width = 100s.

Source to Drain Diode Voltage Reverse Recovery Time ISD = 60A, dISD/dt = 100A/µs- -33ns

Reverse Recovered Charge ISD = 60A, dISD/dt = 100A/µs- -29nC

SD

= 30A - - 1.0 V

I

SD

FDB14AN06LA0 / FDP14AN06LA0

Typical Characteristics T

= 25°C unless otherwise noted

C

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

80

60

VGS = 5V

40

, DRAIN CURRENT (A)

D

20

I

150

0

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Curr ent vs

-3

t, RECTANGULAR PULSE DURATION (s)

-2

10

VGS = 10V

TC, CASE TEMPERATURE (oC)

Case Temperature

P

DM

NOTES: DUTY FACTOR: D = t1/t PEAK TJ = PDM x Z

-1

10

θJC

10

x R

0

t

1

t

2

+ T

θJC

C

1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

1000

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

VGS = 10V

100

VGS = 5V

50

-5

10

-4

10

-3

10

-2

10

-1

10

, PEAK CURRENT (A)

DM

I

t, PUL SE WIDTH (s)

TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:

175 - T

I = I

25

10

C

150

0

1

10

Figure 4. Peak Current Capability

Typical Characteristics T

= 25°C unless otherwise noted

C

FDB14AN06LA0 / FDP14AN06LA0

1000

10µs

100

10

OPERATION IN THIS

AREA MAY BE

, DRAIN CURRENT (A)

D

I

LIMITED BY r

1

SINGLE PULSE TJ = MAX R ATED

TC = 25oC

0.1 110100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

100µs

1ms

10ms

DC

Figure 5. Forward Bias Safe Operating Area

500

100

10

, AVALANCHE CURRENT (A)

AS

I

1

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

150

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

125

V

= 15V

DD

100

75

50

, DRAIN CURRENT (A)

D

I

25

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0

TJ = 25oC

TJ = 175oC

TJ = -55oC

VGS, GATE TO SOURCE VOLTAGE (V)

150

125

100

, DRAIN CURRENT (A)

D

I

If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BV

STARTING TJ = 150oC

0.001 0.01 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

ST ARTING TJ = 25oC

Capability

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

TC = 25oC

VGS = 10V

75

50

25

0

0 0.5 1.0 1.5 2.0 2.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 5V

VGS = 4V

VGS = 3V

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

13

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

12

VGS = 5V

11

10

DRAIN TO SOURCE ON RESISTANCE(mΩ)

9

0 20406080

VGS = 10V

ID, DRAIN CURRENT (A)

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

2.5

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

VGS = 5V, ID = 60A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDB14AN06LA0 / FDP14AN06LA0

Typical Characteristics T

1.4

1.2

1.0

0.8

0.6

NORMALIZED GATE

THRESHOLD VOLTAGE

0.4

0.2

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

C

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperatur e

5000

C

= CGS + C

1000

C

= C

RSS

GD

C, CAPACITANCE (pF)

100

V

= 0V, f = 1MHz

GS

50

0.1 1 10

VDS, DRAIN TO SOURCE VOLTAGE (V)

ISS

C

OSS

≅ C

DS

+ C

GD

60

1.2 ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 30V

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 1020304050

Qg, GATE CHARGE (nC)

WAVEFORMS IN DESCENDING ORDER:

ID = 60A ID = 10A

Figure 13. Capacitance vs Drain to Sour ce

Voltage

Figure 14. Gat e Charge Waveforms for Constant

Gate Currents

Test Circuits and Waveforms

V

DS

L

VARY tP TO OBTAIN REQUIRED PEAK I

V

GS

R

AS

G

+

V

DD

-

I

AS

DUT

t

0V

P

I

AS

0.01Ω

0

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Wavef orm s

V

DS

V

DD

V

Q

I

g(REF)

L

V

GS

DUT

+

V

DD

-

V

GS

0

I

g(REF)

= 1V

Q

gs2

Q

g(TH)

Q

gs

0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

BV

DSS

t

P

t

AV

Q

g(TOT)

DS

gd

V

GS

FDB14AN06LA0 / FDP14AN06LA0

V

DS

V

DD

V

= 5V

GS

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

90%

PULSE WIDTH

50%50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, P application. Therefore the application’s ambient temperature, T must be reviewed to ensure that T Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

DM

θJA

, in an

(oC/W)

serve s as the basis for establ ishing the rating of the part.

P

DM

TJMTA–()

----------------- ------------=

R

θJA

(EQ. 1)

In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power d issipati on rating s. Precise d etermin ation of P comple x and influenced by many factors:

DM

is

1. Mou nting pad area ont o which the device is attached and whet her the re is copp er on one s ide or both side s of the board.

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For no n steady state applic ations, th e pulse widt h, the duty cycle and the transient thermal response of the part, the boa rd and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR- 4 bo ar d with 1 oz c o pp er after 1 00 0 secon ds of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice t hermal model or ma nually utiliz ing the normalized maximum transient thermal impedance curve.

80

60

C/W)

o

(

θJA

R

40

20

Figure 21. Thermal Resistance vs Mounting

R

= 26.51+ 19.84/(0.262+Area) EQ.2

θJA

R

= 26.51+ 128/(1.69+Area) EQ.3

θJA

(0.645) (6.45) (64.5)

AREA, TOP COPPER AREA in2 (cm2)

1100.1

Pad Area

FDB14AN06LA0 / FDP14AN06LA0

Therma l resi stances correspondi ng to other copper ar eas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inch es squ are and equ ation 3 is for area in cent imeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads.

19.84

-------------------------------------+

26.51

=

R

θJA

26.51

=

R

θJA

0.262 Area+()

Area in Inches Squared

128

----------------------------------+

1.69 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

PSPICE Electrical Model

.SUBCKT FDP14AN06LA0 2 1 3 ; rev January 2004 Ca 12 8 1.8e-9 Cb 15 14 1.8e-9 Cin 6 8 3e-9

Dbod y 7 5 DbodyMOD Dbreak 5 11 Db reakMOD Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 64.8 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1

ESG

Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1

It 8 17 1 Lgat e 1 9 7.4e-9

GATE

1

LGATE

RLGATE

RGATE

9

EVTEMP

+

18 22

20

Ldrain 2 5 1.00 e-9 Lsou rce 3 7 3e-9

RLgate 1 9 74 RLdr ai n 2 5 10

S1A

12

RLsource 3 7 30 Mmed 16 6 8 8 M m edMOD

Mstro 16 6 8 8 MstroMOD

S1B

CA

Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1

Rdrain 50 16 RdrainMOD 4.1e-3 Rgate 9 20 2.7 RSLC1 5 51 RSL CM OD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 4e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BM OD S2a 6 15 14 13 S2AM OD S2b 13 15 14 13 S2BM OD

Vbat 22 19 DC 1 ESLC 51 50 VALUE = {(V(5,5 1)/ ABS(V(5,5 1)))*(PWR (V(5,51)/(1e-6*200 ),3))}

.MODEL DbodyMOD D (IS=1 .7 e-11 RS=2.8e -3 N=1.05 TRS1=1.5e-3 TRS2 =1e-6 + CJO=1e-9 TT=1.9e-8 M=0.58 IKF=15.00 X T I = 3) .mod e l dbreakmod d (RS=1e -1 TRS1=1.12e- 3 T RS 2=1.25 e -6) .MODEL DplcapMOD D (CJO=8e-10 IS=1e-30 N=10 M=0.57)

.MODEL MmedMOD NMOS (VTO=1.96 KP=8 IS=1e-30 N=10 TOX =1 L=1u W=1u RG=2.7 ) .MODEL Mstro M OD NMOS (VTO=2.42 KP=105 IS=1e -30 N=10 TOX=1 L=1 u W=1u) .MODEL MweakMOD NMOS (VTO=1.6 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=27 RS=0.1)

DPLCAP

10

RSLC2

6

8

EVTHRES

+

19

6

-

S2A

13814

13

S2B

13

+

6

EGS EDS

8

-

5

RSLC1

51

+

5

ESLC

51

50

RDRAIN

16

21

-

8

MSTRO

CIN

15

CB

8

14

+

5 8

-

MMED

8

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

FDB14AN06LA0 / FDP14AN06LA0

LDRAIN

RLDRAIN

11

+

17

DBODY

18

-

LSOURCE

7

RLSOURCE

RVTEMP 19

VBAT

+

22

DRAIN

2

SOURCE

3

.MODEL RbreakMOD RES (TC1=9.2e-4 TC2=-3.55e-7) .MODEL Rd rai nMOD RES (TC1=1e-2 TC2=3e-5) .MODEL RSLCMOD RES (TC1=2.8e-3 TC2=1e-7) .MODEL RsourceMOD RES (TC1=4.0e-3 TC 2=1e-6) .MODEL RvthresMOD RE S (T C1=-2.7e-3 TC2=-9.5e-6) .MODEL RvtempMOD RES (TC1=-2.3e-3 TC2=1.5e -6)

.MODEL S1AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 4 VOFF =-3 ) .MODEL S1BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 3 VOFF =-4 ) .MODEL S2AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 2. 5 VOFF =-0 .5 ) .MODEL S2BMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 0. 5 VOFF =-2 .5 ) .ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electroni cs Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

SABER Electrical Model

REV January 2004 template FDP14AN06LA0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.7e-11,rs=2.8e-3,nl=1.05,trs1=1.5e-3,trs2=1e-6,cjo=1e-9,tt=1.9e-8,m=0.58,ikf=15.00,xti=3) dp..model dbreakmod = (rs=1e-1,trs1=1 .12e-3,trs2= 1.25e-6) dp..m odel dpl capmod = (cjo=8e-10,isl=10e-30,nl=10,m=0. 5 7) m..model mmedmod = (type=_n,vto=1.96,kp=8,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.42,kp=105,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.6,kp=0.04,is=1e-30, tox=1,rs=0.1) sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0.1,von=-4, vof f=-3) sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0.1,von=-3, vof f=-4) sw_vcsp.. mo del s2amod = (ron=1e-5,roff=0.1,von=-2. 5,voff=-0.5 )

10

sw_vcsp.. mo del s2bmod = (ron=1e-5,roff=0.1,von=-0. 5,voff=-2.5 ) c.ca n12 n8 = 1.8e -9 c.cb n15 n14 = 1.8e-9

RSLC2

c.cin n6 n8 = 3e-9 dp.dbody n7 n5 = model=dbodym od

dp.dbreak n5 n11 = model=dbr eakmod dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 64.8 spe.eds n14 n8 n5 n8 = 1

GATE

spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1

LGATE

1

RLGATE

RGATE

9

ESG

EVTEMP +

20

6

8

+

6

-

18 22

spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1 l.lgate n1 n9 = 7.4e-9

l.ldrain n2 n5 = 1.00e-9 l.lsource n3 n7 = 3e-9

res.rlgate n1 n9 = 74 res.rldrai n n2 n5 = 10 res.rlsource n3 n7 = 30

CA

S1A

12

13

8

S1B

EGS EDS

S2A

14 13

S2B

13

+

6 8

-

m.mmed n16 n6 n8 n8 = m odel=mmed m od, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=m s trongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

DPLCAP

EVTHRES

+

19

8

15

CB

CIN

-

+

-

5

MSTRO

14

5 8

RSLC1

51

ISCL

50 RDRAIN

16

21

8

MMED

DBREAK

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

+

17 18

7

RVTEMP 19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDB14AN06LA0 / FDP14AN06LA0

res.rbreak n17 n18 = 1, tc1=9.2e-4,tc2=-3. 5e-7 res.rdrain n50 n16 = 4.1e-3, tc 1=1e-2,tc2=3e-5 res.rgate n9 n20 = 2.7 res.rslc1 n5 n51 = 1e-6, tc1=2.8e-3,tc2= 1e-7 res.rslc2 n5 n50 = 1e3 res.rsour ce n8 n7 = 4e-3, tc1=4. 0e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-2. 7e-3,tc2=-9. 5e-6 res.rvtemp n18 n19 = 1, tc1=-2.3e-3,tc2=1.5e-6 sw_vcsp.s1 a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1 b n13 n12 n13 n8 = mode l =s1bmod sw_vcsp.s2 a n6 n15 n14 n13 = mode l =s2amod sw_vcsp.s2 b n13 n15 n14 n13 = mod el =s2bmod

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n 5,n51)/(1e-9+abs(v(n5,n51))))* ((abs(v(n5,n51)*1e6/200))** 3)) }

FDB14AN06LA0 / FDP14AN06LA0

SPICE Thermal Model

REV January 2004 FDP14AN06LA0T

CTHERM1 TH 6 2.5e-3 CTHERM2 6 5 3e-3 CTHERM3 5 4 4e-3 CTHERM4 4 3 7e-3 CTHERM5 3 2 8. 2e-3 CTHERM6 2 TL 5e-2

RTHERM1 TH 6 4.2e-2 RTHERM2 6 5 8. 4e-2 RTHERM3 5 4 1. 04e-1 RTHERM4 4 3 1. 14e-1 RTHERM5 3 2 2. 74e-1 RTHERM6 2 TL 3.44e-1

SABER Thermal Model

SABER thermal model FDP1 4AN06LA0T template thermal_model th tl thermal_ c th , tl { ctherm.c th erm 1 th 6 =2.5e-3 ctherm.ctherm2 6 5 =3e-3 ctherm.ctherm3 5 4 =4e-3 ctherm.ctherm4 4 3 =7e-3 ctherm.ctherm5 3 2 =8.2e-3 ctherm.ctherm6 2 tl =5e-2

rtherm.rtherm1 th 6 =4.2 e-2 rtherm.rt herm2 6 5 =8.4e-2 rtherm.rt herm3 5 4 =1.04e-1 rtherm.rt herm4 4 3 =1.14e-1 rtherm.rt herm5 3 2 =2.74e-1 rthe r m.rtherm6 2 tl =3.4 4e-1 }

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

2

RTHERM6

tl

CTHERM6

CASE

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Rev. I7