Datasheet FDP120AN15A0, FDD120AN15A0 Datasheet (Fairchild)

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Page 1

FDP120AN15A0 / FDD120AN15A0

N-Channel PowerTrench® MOSFET 150V, 14A, 120mΩ

FDP120AN15A0 / FDD120AN15A0

September 2002

Features

•r

•Qg(tot) = 11.2nC (Typ.), V

• Low Miller Charge

• Low Qrr Body Diode

• UIS Capability (Single Pulse and Repetitive Pulse)

= 101mΩ (Typ.), V

DS(ON)

= 10V, ID = 4A

= 10V

Applications

• DC/D C C onverter s an d Of f-line UPS

• Distributed Power Ar chitectures and VRMs

• Primary Switch for 24V and 48V Systems

• High Voltage Synchronous Re ctifier

• Direct Injection / Diesel Injection Systems

• Elec tr on ic Valve Train Syst e m s

Formerly developmental type 82845

DRAIN

(FLANGE)

TO-220AB

FDP SERIES

SOURCE

DRAIN

GATE

MOSFET Maximum Ratings

GATE

SOURCE

TO-252AA

FDD SERIES

TC = 25°C unless otherwise noted

DRAIN

(FLANGE)

Symbol Parameter Ratings Units

DSS

Drain to Source Voltage 150 V Gate to Source Voltage ±20 V Drain Curr e nt Continuous (T

Continuous (T Continuous (T

= 25oC, VGS = 10V)

= 100oC, VGS = 10V) 9.7 A

= 25oC, VGS = 10V) with R

amb

= 52oC/W 2.8 A

θJA

14 A

Pulsed Figure 4 A

, T

STG

Single Pulse Avalanche Energy (Note 1) 122 mJ Power dissipation 65 W Derate above 25oC0.43W/ Operating and Storage Temperature -55 to 175

Thermal Characteristi cs

θJC

θJA

Thermal Resistance Junction to Case T O -252, TO-220 2.31 Thermal Resistance Junction to Ambien t TO-252 100 Thermal Resistance Junction to Ambient TO-220 (Note 2) 62 Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad ar ea 52

Reliability data can be fou nd a t: http://ww w.f airc hilds e m i.co m /pr oduc ts/dis c rete/reliab ility/ind ex.html.

C/W

Page 2

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDD12 0AN 1 5A0 FDD12 0AN15A0 TO-252AA 330mm 16mm 2500 un its FDP120AN15A0 FDP120AN15A0 TO- 220AB Tube N/A 50 unit s

FDP120AN15A0 / FDD120AN15A0

Electrical Characteristics

TC = 25°C unless otherwise not ed

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B I

DSS

GSS

VDSS

Drain to Sou r c e Br ea k down Voltag e ID = 250µA, VGS = 0V 150 - - V

= 120V - - 1

Zero Gate Voltage Drain Current

= 0V TC = 150oC- -250

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

GS(TH)

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

ID = 4A, VGS = 10V - 0.101 0.120 I

= 2A, VGS = 6V - 0.113 0.170

Drain to S ou r c e On Re si st ance

= 4A, VGS = 10V,

= 175oC

- 0.235 0.282

Dynamic Characteristics

C C C Q Q Q Q Q

ISS OSS RSS

g(TOT) g(TH) gs gs2 gd

Input Capacitance Output Capacitance - 85 - pF Reverse Transfer Capacitance - 17 - pF

= 25V, VGS = 0V,

f = 1MHz

Total Gate Charge at 10V VGS = 0V to 10V Threshold Gate Charge VGS = 0V to 2V - 1.4 1.8 nC Gate to Source Gate Charg e - 3.5 - nC Gate Charge Threshold to Plateau - 2.1 - nC

VDD = 75V ID = 4A I

= 1.0m A

Gate to Drain “Miller” Charge - 2.6 - nC

-770- pF

11.2 14.5 nC

µA

Ω

Switching Characteristics

d(ON)

d(OFF)

OFF

Turn-On Time Turn-On Delay Time - 6 - ns Rise Time - 16 - ns Turn-Off Delay Ti me - 30 - ns Fall Time - 19 - ns Turn-Off T ime - - 74 ns

(VGS = 10V)

Drain-Source Diode Characteristics

Notes: 1: Starting TJ = 25°C, L = 27mH, IAS = 3A. 2: Pulse width = 100s.

Source to Drain Diode Voltage Reverse Recovery Time ISD = 4A, dISD/dt = 100A/µs--61ns

Reverse Recovered Charge ISD = 4A, dISD/dt = 100A/µs - - 109 nC

- - 33 ns

VDD = 75V, ID = 4A VGS = 10V, RGS = 24Ω

= 4A - - 1.25 V

= 2A - - 1.0 V

Page 3

FDP120AN15A0 / FDD120AN15A0

Typical Characteristics

TC = 25°C unless otherwise not ed

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0255075100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

THERMAL IMPEDANCE

0.01

-5

SINGLE PULSE

-4

, DRAIN CURRENT (A)

150

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Curr ent vs

-3

t, RECTANGULAR PULSE DURATION (s)

-2

TC, CASE TEMPERATURE (oC)

Case Temperature

NOTES: DUTY FACTOR: D = t1/t PEAK TJ = PDM x Z

-1

θJC

x R

+ T

θJC

Figure 3. Normalized Maximum Transient Thermal Impedance

200

TRANSCONDUCTANCE

100

MAY LIMIT CURRENT IN THIS REGION

VGS = 10V

, PEAK CURRENT (A)

-5

-4

-3

-2

-1

t, PULSE WIDTH (s)

TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:

175 - T

I = I

150

Figure 4. Peak Current Capability

Page 4

Typical Characteristics

FDP120AN15A0 / FDD120AN15A0

TC = 25°C unless otherwise not ed

100

OPERATION IN THIS

, DRAIN CURRENT (A)

0.1

AREA MAY BE

LIMITED BY r

SINGLE PULSE TJ = MAX R ATED

TC = 25oC

1 10 100

DS(ON)

, DRAIN TO SOURCE VOLTAGE (V)

10ms

10µs

100µs

1ms

Figure 5. Forward Bias Safe Operating Area

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

= 15V

If R = 0

200

tAV = (L)(IAS)/(1.3*RATED BV If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BV

, AVALANCHE CURRENT (A)

STARTING TJ = 150oC

0.01 0.1 1 tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

TC = 25oC

VGS = 10V

VGS = 7V

VGS = 6V

, DRAIN CURRENT (A)

TJ = 25oC

TJ = 175oC

34567

VGS, GATE TO SOURCE VOLTAGE (V)

TJ = -55oC

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

140

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

130

120

110

100

DRAIN TO SOURCE ON RESISTANCE(mΩ)

03691215

VGS = 6V

VGS = 10V

ID, DRAIN CURRENT (A)

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

, DRAIN CURRENT (A)

012345

2.5

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

TJ, JUNCTION TEMPERATURE (oC)

VGS = 5V

VGS = 10V, ID = 4A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

Page 5

FDP120AN15A0 / FDD120AN15A0

Typical Characteristics

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

TC = 25°C unless otherwise not ed

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperatur e

1000

= CGS + C

ISS

≅ C

+ C

OSS

100

= C

RSS

C, CAPACITANCE (pF)

= 0V, f = 1MHz

0.1 1 10 150 VDS, DRAIN TO SOURCE VOLTAG E (V)

1.2 ID = 250µA

1.1

1.0

BREAKDOWN VOLTA GE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

VDD = 75V

, GATE TO SOURCE VOLTAGE (V)

04812

Qg, GATE CHARGE (nC)

WAVEFORMS IN DESCENDING ORDER:

ID = 14A ID = 4A

Figure 13. Capacitance vs Drain to Sour ce

Voltage

Figure 14. Gat e Charge Waveforms for Constant

Gate Currents

Page 6

Test Circuits and Waveforms

VARY t

TO OBTAIN

REQUIRED PEAK I

DUT

0.01Ω

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

g(REF)

DUT

g(REF)

= 2V

gs2

g(TH)

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

DSS

g(TOT)

FDP120AN15A0 / FDD120AN15A0

= 10V

DUT

10%

d(ON)

90%

10%

PULSE WIDTH

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

d(OFF)

90%

OFF

90%

10%

50%50%

Page 7

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, T must be reviewed to ensure that TJM is never exceeded.

(oC), and th ermal res istance R

θJA

(oC/W)

Equation 1 mathematically represents the relationship and serve s as the basis for establishing the rating of the part.

TJMTA–()

----------------- ------------=

θJA

(EQ. 1)

125

100

C/W)

(

θJA

= 33.32+ 23.84/(0.268+Area) EQ.2

θJA

= 33.32+ 154/(1.73+Area) EQ.3

θJA

FDP120AN15A0 / FDD120AN15A0

In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power d issipati on rating s. Precise d etermin ation of P comple x and infl uenced by many factors:

1. Mou nting pad area onto which the device is attach ed and whet her the re is copp er on one s ide or both side s of the board.

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For no n steady state applic ations, th e pulse widt h, the duty cycle and the transient ther mal resp onse of the part, the boa rd and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 board w i th 1 oz c opper af ter 100 0 se c on ds of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides the necessary i nformation for calculat ion of th e steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice t hermal model or manually u tilizing the normalized maximum transient thermal impedance curve.

0.01 0.1 1 10 (0.645) (6.45) (64.5)(0.0645)

AREA, TOP COPPER AREA in2 (cm2)

Figure 21. Thermal Resistance vs Mounting

Pad Area

Therma l resistances corresp onding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inch es squ are and equ ation 3 is for area in cent imeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads.

23.84

θJA

33.32

-------------------------------------+

0.268 Area+()

Area in Inches Squared

154

----------------------------------+

1.73 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

Page 8

PSPICE Electrical Model

.SUBCKT FDD120AN15A0 2 1 3 ; rev July 2002 Ca 12 8 2.5e-10 Cb 15 14 2.5e-10 Cin 6 8 7.5e-10

Dbod y 7 5 DbodyM OD Dbreak 5 11 Db reakMOD Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 162 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1

It 8 17 1 Lgat e 1 9 3e-9

Ldrain 2 5 1.0e -9 Lsou rce 3 7 2e-9 RLgate 1 9 30 RLdr ai n 2 5 10 RLsource 3 7 20

Mmed 16 6 8 8 M m edMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 6.55e-2 Rgate 9 20 3.6 RSLC1 5 51 RSL CM OD 1.0e-6 RSLC2 5 50 1.0e 3 Rsource 8 7 RsourceMOD 2.8e-2 Rvthres 22 8 RvthresMO D 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BM OD S2a 6 15 14 13 S2AM OD S2b 13 15 14 13 S2BM OD

GATE

LGATE

RLGATE

RGATE

ESG

EVTEMP

18 22

S1A

S1B

EGS EDS

6 8

RSLC2

S2A

14 13

S2B

6 8

DPLCAP

EVTHRES

CIN

MSTRO

5 8

RSLC1

ESLC

RDRAIN

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

RVTHRES

RVTEMP 19

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

SOURCE

FDP120AN15A0 / FDD120AN15A0

Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51))) *(PWR(V(5,51)/(1e-6 *25),3))} .MODEL DbodyMOD D (IS=4E-12 N=1.07 RS=6.5e-3 TRS1=3.0e-3 TRS2=1.5e-6

+ CJO=5.5e-10 M=0.65 TT=5e -8 X T I=4.2) .MODEL DbreakMOD D (RS=0.5 TRS1=1e-3 TRS2=-1e- 6) .MODEL Dpl capMOD D (CJO=1.56e-10 IS=1.0e-30 N=10 M=0.62)

.MODEL MmedM OD NMOS (VTO=3.6 KP=1.8 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3. 6) .MODEL MstroMOD NMOS (VTO =4.4 KP=30 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL Mwe akMOD NMOS (VTO =3.14 KP=0. 02 IS=1e-30 N= 10 T OX=1 L=1u W=1u RG=36 RS=0.1)

.MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1e-6) .MODEL Rd rai nMOD RES (TC1=8.5e-3 TC 2=2.5e-5) .MODEL RSLCMOD RES (TC1=3.4e-3 TC2=1.5e-6) .MODEL RsourceMOD RES (TC1=4.1e-3 TC 2=1e-6) .MODEL RvthresMOD RES (TC1=-3.6e -3 T C2=-1.4e-5 ) .MODEL RvtempMOD RES (T C1=-4.1e-3 TC2=1.5e-6)

.MODEL S1AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 6. 0 VOFF =-4 .0 ) .MODEL S1BMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 4. 0 VOFF =-6 .0 ) .MODEL S2AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 2. 5 VOFF =-0 .5 ) .MODEL S2BMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 0. 5 VOFF =-2 .5 )

.ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electroni cs Specialist Conference Records, 1991, written by Wil liam J. Hepp and C. F rank Wheatley.

Page 9

SABER Electrical Model

REV July 2002 template FDD 120AN15A0 n2, n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=4e-12,nl=1.07,rs=6.5e-3,trs1=3.0e-3,trs2=1.5e-6,cjo=5.5e-10,m=0.65,tt=5e-8,xti=4.2) dp..model dbreakmod = (rs=0.5,trs1=1e-3,trs2=-1e-6) dp..model dplcapmod = (cjo=1.56e-10,isl=10.0e-30,nl=10,m=0.62) m..model mmedmod = (type=_n,vto=3.6,kp=1.8,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.4,kp=30,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.14,kp=0.02,is=1e-30, tox=1,rs=0.1) sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0. 1, von=-6.0,voff=-4.0) sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0. 1, von=-4.0,voff=-6.0) sw_vcsp.. mo del s2amod = (ron=1e-5,roff=0. 1, von=-2.5,voff=-0.5) sw_vcsp.. mo del s2bmod = (ron=1e-5,roff=0. 1, von=-0.5,voff=-2.5) c.ca n12 n8 = 2.5e-10 c.cb n15 n14 = 2.5e-10 c.cin n6 n8 = 7.5e -10

dp.dbody n7 n5 = model=dbodym od dp.dbreak n5 n11 = model=dbr eakmod dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 162 spe.eds n14 n8 n5 n8 = 1

GATE

spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1

LGATE

RLGATE

RGATE

ESG

EVTEMP +

18 22

spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1 l.lgate n1 n9 = 3e -9

l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2e-9

S1A

S1B

res.rlgate n1 n9 = 30 res.rldrai n n2 n5 = 10 res.rlsource n3 n7 = 20

m.mmed n16 n6 n8 n8 = m odel=mmedm od, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l= 1u, w=1u m.mweak n16 n21 n8 n8 = model=mwea kmod, l=1u, w=1u

DPLCAP

RSLC2

EVTHRES

S2A

S2B

EGS EDS

RSLC1

ISCL

MMED

DBREAK

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

RVTHRES

17 18

50 RDRAIN

MSTRO

CIN

5 8

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

RVTEMP 19

VBAT

DRAIN

SOURCE

FDP120AN15A0 / FDD120AN15A0

res.rbreak n17 n18 = 1, tc1=1.1e- 3,tc2=-1e-6 res.rdrain n50 n16 = 6.55e-2, tc 1=8.5e-3,tc 2=2.5e-5 res.rgat e n9 n20 = 3.6 res.rslc1 n5 n51 = 1.0e-6, tc1=3.4e-3,tc2 =1.5e-6 res.rslc2 n5 n50 = 1.0e3 res.rsour ce n8 n7 = 2.8e-2, tc1= 4. 1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-3.6e-3,tc2=-1. 4e-5 res.rvtemp n18 n19 = 1, tc1=-4.1e-3,tc2=1.5e-6 sw_vcsp.s1 a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1 b n13 n12 n13 n8 = mode l= s1bmod sw_vcsp.s2 a n6 n15 n14 n13 = mode l= s2amod sw_vcsp.s2 b n13 n15 n14 n13 = model = s2bmod

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5 ,n51))))*(( abs(v(n5,n51)*1e6/25) )** 3)) }

Page 10

FDP120AN15A0 / FDD120AN15A0

SPICE Thermal Model

REV 23 July 2002 FDD120AN15A0T CTHERM1 TH 6 1.2e-3

CTHERM2 6 5 2e-3 CTHERM3 5 4 2. 5e-3 CTHERM4 4 3 3. 15e-3 CTHERM5 3 2 3. 3e-3 CTHERM6 2 TL 1.35e-2

RTHERM1 TH 6 6.8e-2 RTHERM2 6 5 1. 18e-1 RTHERM3 5 4 2. 28e-1 RTHERM4 4 3 3. 28e-1 RTHERM5 3 2 5. 28e-1 RTHERM6 2 TL 5.78e-1

SABER Thermal Model

SABER therm a l model FDD120A N15A0T template thermal_model th tl thermal_ c th , tl { ctherm.c th erm 1 th 6 =1.2e-3 ctherm.ctherm2 6 5 =2e-3 ctherm.ctherm3 5 4 =2.5e-3 ctherm.ctherm4 4 3 =3.15e-3 ctherm.ctherm5 3 2 =3.3e-3 ctherm.ctherm6 2 tl =1.35e- 2

rtherm.rtherm1 th 6 =6.8e-2 rtherm.rtherm 2 6 5 =1 . 18e-1 rtherm.rtherm 3 5 4 =2 . 28e-1 rtherm.rtherm 4 4 3 =3 . 28e-1 rtherm.rtherm 5 3 2 =5 . 28e-1 rthe r m.rthe rm6 2 tl =5. 7 8e-1 }

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

CTHERM1

CTHERM2

CTHERM3

CTHERM4

CTHERM5

RTHERM6

CTHERM6

CASE

Page 11

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

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C™

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OPTOPLANAR™

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QFET™ QS™ QT Optoelectronics™ Quiet Se ries™ RapidConfigure™ RapidConnect™ SILENT SWITCHER SMART START™

SPM™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET

VCX™

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which, (a) ar e int ende d fo r s urgic al i mpla nt into the bo dy, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

2. A c r it ic al c om ponent i s any com po ne n t o f a l ife supp or t device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Adva nce Information Formative or In

Design

Preliminary First Production This datasheet contain s preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Producti on This datash eet contains speci fications on a product

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

supple m entary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Semiconductor reserves the right to make changes at any time without notice in order to improve design.

that has been disco ntinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. I1

Datasheet FDP120AN15A0, FDD120AN15A0 Datasheet (Fairchild)

Specifications and Main Features

Frequently Asked Questions

User Manual