Page 1
FDMS8020
Power 56
D
D
D
D
G
S
S
S
Pin 1
Bottom
Top
G
S
S
S
D
D
D
D
5
6
7
8
3
2
1
4
N-Channel PowerTrench® MOSFET
30 V, 42 A, 2.5 mΩ
Features
Max r
Max r
Advanced Package and Silicon combination for low r
and high efficiency
Next generation enhanced body diode technology,
engineered for soft recovery
MSL1 robust package design
100% UIL tested
RoHS Compliant
= 2.5 mΩ at VGS = 10 V, ID = 26 A
DS(on)
= 3.6 mΩ at VGS = 4.5 V, ID = 21.5 A
DS(on)
DS(on)
General Description
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency and to minimize switch node
ringing of DC/DC converters using either synchronous or
conventional switching PWM controllers.It has been optimized
for low gate charge, low r
diode reverse recovery performance.
Applications
VRM Vcore Switching for Desktop and Server
OringFET / Load Switching
DC-DC Conversion
Motor Bridge Switch
November 2011
, fast switching speed ang body
DS(on)
FDMS8020 N-Channel PowerTrench
®
MOSFET
MOSFET Maximum Ratings T
Symbol Parameter Ratings Units
V
DS
V
GS
I
D
E
AS
P
D
, T
T
J
STG
Drain to Source Voltage 30 V
Gate to Source Voltage (Note 4) ±20 V
Drain Current -Continuous (Package limited) TC = 25 °C 42
-Continuous (Silicon limited) T
-Continuous T
-Pulsed 150
Single Pulse Avalanche Energy (Note 3) 93 mJ
Power Dissipation TC = 25 °C 65
Power Dissipation T
Operating and Storage Junction Temperature Range -55 to +150 °C
= 25 °C unless otherwise noted
A
= 25 °C 131
C
= 25 °C (Note 1a) 26
A
= 25 °C (Note 1a) 2.5
A
A
W
Thermal Characteristics
R
θJC
R
θJA
Thermal Resistance, Junction to Case 1.9
Thermal Resistance, Junction to Ambient (Note 1a) 50
°C/W
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FDMS8020 FDMS8020 Power 56 13 ’’ 12 mm 3000 units
©2011 Fairchild Semiconductor Corporation
FDMS8020 Rev. C
1
www.fairchildsemi.com
Page 2
FDMS8020 N-Channel PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
ΔBV
ΔT
I
DSS
I
GSS
DSS
DSS
J
Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 30 V
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current VDS = 24 V, V
Gate to Source Leakage Current, Forward VGS = 20 V, V
I
= 250 μA, referenced to 25 °C 14 mV/°C
D
= 0 V 1 μA
GS
= 0 V 100 nA
DS
On Characteristics
V
GS(th)
ΔV
ΔT
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 1.0 1.5 3.0 V
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
I
= 250 μA, referenced to 25 °C -6 mV/°C
D
V
= 10 V, ID = 26 A 2.0 2.5
GS
= 4.5 V, ID = 21.5 A 2.6 3.6
GS
= 10 V, ID = 26 A, TJ = 125 °C 2.9 3.7
V
GS
Forward Transconductance VDS = 5 V, ID = 26 A 154 S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance 1050 1400 pF
Reverse Transfer Capacitance 115 175 pF
= 15 V, VGS = 0 V,
V
DS
f = 1 MHz
Gate Resistance 0.9 Ω
2855 3800 pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
Q
Turn-On Delay Time
Rise Time 5.7 12 ns
Turn-Off Delay Time 32 52 ns
= 15 V, ID = 26 A,
V
DD
V
= 10 V, R
GS
GEN
= 6 Ω
Fall Time 410ns
g
g
gs
gd
Total Gate Charge VGS = 0 V to 10 V
Total Gate Charge VGS = 0 V to 4.5 V 21 29 nC
Gate to Source Charge 7.3 nC
V
DD
I
= 26 A
D
= 15 V,
Gate to Drain “Miller” Charge 6.0 nC
12 22 ns
43 61 nC
mΩV
®
MOSFET
Drain-Source Diode Characteristics
V
= 0 V, IS = 2.1 A (Note 2) 0.68 1.1
V
SD
t
rr
Q
rr
t
rr
Q
rr
Notes:
is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. boar d of FR-4 ma terial . R
1. R
θJA
the user's board design.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Starting TJ = 25 °C; N-ch: L = 0.3 mH, IAS = 25 A, VDD = 27 V, VGS = 10 V.
4.As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
©2011 Fairchild Semiconductor Corporation
FDMS8020 Rev. C
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge 18 33 nC
Reverse Recovery Time
Reverse Recovery Charge 36 57 nC
a) 125 °C/W when mounted on a
50 °C/W when mounted on a
2
pad of 2 oz copper
1 in
GS
= 0 V, IS = 26 A (Note 2) 0.78 1.2
V
GS
= 26 A, di/dt = 100 A/μs
I
F
= 26 A, di/dt = 300 A/μs
I
F
2
37 58 ns
30 48 ns
is guaranteed by design while R
θJC
b)
minimum pad of 2 oz copper.
V
is determined by
θCA
www.fairchildsemi.com
Page 3
FDMS8020 N-Channel PowerTrench
012345
0
30
60
90
120
150
VGS = 3 V
VGS = 10 V
VGS = 4.5 V
VGS = 4 V
VGS = 3.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
I
D
, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
0306090120150
0
1
2
3
4
5
VGS = 4.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTA NCE
I
D
, DRAIN CURRENT (A)
V
GS
= 3 V
VGS = 3.5 V
VGS = 4 V
V
GS
= 10 V
-75 -50 -25 0 25 50 75 100 125 150
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
ID = 26 A
V
GS
= 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
T
J
, JUNCTION TEMPERATURE (
o
C)
246810
0
2
4
6
8
10
TJ = 125 oC
ID = 26 A
TJ = 25 oC
V
GS
, GATE TO SOURCE VOLTA G E (V)
r
DS(on)
,
DRAIN TO
SOURCE ON-RESISTANCE
(mΩ)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
1.0 1.5 2.0 2.5 3.0 3.5 4.0
0
30
60
90
120
150
TJ = 25 oC
TJ = 150 oC
V
DS
= 5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
I
D
, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
0.0 0 .2 0.4 0.6 0.8 1.0 1.2
0.001
0.01
0.1
1
10
100
200
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
V
GS
= 0 V
I
S
, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Typical Characteristics T
Figure 1.
On-Region Characteristics Figure 2.
= 25 °C unless otherwise noted
J
Norma l i z e d O n - Resistanc e
vs Drain Current and Gate Voltage
®
MOSFET
Fig u r e 3. Nor m a lized O n - Resis t a nce
vs Junction Temperature
©2011 Fairchild Semiconductor Corporation
FDMS8020 Rev. C
Figure 5. Transfer Characteristics
Figure 4.
On-Resistance vs Gate to
Source Voltage
Figure 6.
Source to Drain Diode
Forward Voltage vs Source Current
3
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Page 4
FDMS8020 N-Channel PowerTrench
0 5 10 15 20 25 30 35 40 45
0
2
4
6
8
10
ID = 26 A
VDD = 12 V
V
DD
=15 V
V
GS
, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 18 V
0.1 1 10 30
10
100
1000
10000
f = 1 MHz
V
GS
= 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
C
rss
C
oss
C
iss
0.01 0.1 1 10 100 300
1
10
100
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVALANCHE (ms)
I
AS
, AVALANCHE CURRENT (A)
25 50 75 100 125 150
0
30
60
90
120
150
Limited by Package
V
GS
= 4.5 V
R
θJC
= 1.9 oC/W
V
GS
= 10 V
I
D
, DRAIN CURRENT (A)
T
C
, CASE TEMPERATURE (
o
C)
0.01 0.1 1 10 100200
0.01
0.1
1
10
100
200
100 μs
10 s
10 ms
DC
1 s
100 ms
1 ms
I
D
, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS A REA IS
LIMITED BY r
DS(on)
SINGLE PULSE
T
J
= MAX RATED
R
θJA
= 125
o
C/W
T
A
= 25
o
C
10-410-310-210-1110
100 1000
0.5
1
10
100
1000
SINGLE PULSE
R
θJA
= 125
o
C/W
T
A
= 25
o
C
P(
PK
), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
Typical Characteristics T
Figure 7.
Gate Charge Characteristics Figure 8.
= 25 °C unless otherwise noted
J
Capacitance vs Drain
to Source Voltage
®
MOSFET
Figure 9.
Uncl a m p e d I n duct i v e
Switching Capability
©2011 Fairchild Semiconductor Corporation
FDMS8020 Rev. C
Figure 11.
Operating Area
Forward Bias Safe
Figure 10.
Ma x imum C onti n uous D rain
Current vs Case Temperature
Fi gur e 12. Sing le Pulse Maxi mum
Power Dissipation
4
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Page 5
FDMS8020 N-Channel PowerTrench
10
-4
10
-3
10
-2
10
-1
110
100 1000
0.001
0.01
0.1
1
2
SINGLE PULSE
R
θJA
= 125 oC/W
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE,
Z
θJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
P
DM
t
1
t
2
NOTES:
DUTY FACTOR: D = t1/t
2
PEAK TJ = PDM x Z
θJA
x R
θJA
+ T
A
Typical Characteristics T
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
= 25 °C unless otherwise noted
J
®
MOSFET
©2011 Fairchild Semiconductor Corporation
FDMS8020 Rev. C
5
www.fairchildsemi.com
Page 6
FDMS8020 N-Channel PowerTrench
Dimensional Outline and Pad Layout
®
MOSFET
©2011 Fairchild Semiconductor Corporation
FDMS8020 Rev. C
6
www.fairchildsemi.com
Page 7
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tm
®
™
tm
tm
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FDMS8020 N-Channel PowerTrench
®
MOSFET
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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THEREIN, WHICH COVERS THESE PRODUCTS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used here in:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain life,
and (c) whose failure to perform when properly used in accordance wit h
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury of the user.
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Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,
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Counterfeiting of semiconductor parts is a growing problem in the industry. All man ufactures of semiconductor products are exper iencing counterfeiti ng of their
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PRODUCT STATUS DEFINITIONS
Definition of Terms
.
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
Datasheet Identification Product Status Definition
Advance Information Formative / In Design
Preliminary First Production
No Identification Needed Full Production
Obsolete Not In Production
©2011 Fairchild Semiconductor Corporation
FDMS8020 Rev. C
Datasheet contains the design specificatio ns for product development. Specifications
may change in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinu ed by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I60
7
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