Datasheet FDMS7602S Datasheet (Fairchild)

Page 1
Q
Q
Power 56
S2
S2
S2
G2
D1
D1
D1
G1
D1
S1/D2
S2
S2 S2 G2
D1
D1 D1
G1
Top Bottom
Dual N-Channel PowerTrench® MOSFET
Q1: 30 V, 30 A, 7.5 mΩ Q2: 30 V, 30 A, 5.0 mΩ
Features
Q1: N-Channel
Max rMax r
Q2: N-Channel
Max rMax r
RoHS Compliant
= 7.5 mΩ at VGS = 10 V, ID = 12 A
DS(on)
= 12 mΩ at VGS = 4.5 V, ID = 10 A
DS(on)
= 5.0 mΩ at VGS = 10 V, ID = 17 A
DS(on)
= 6.8 mΩ at VGS = 4.5 V, ID = 14 A
DS(on)
General Description
This device includes two specialized N-Channel MOSFETs in a dual MLP package.The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET (Q2) have been designed to provide optimal power efficiency.
Applications
ComputingCommunicationsGeneral Purpose Point of Load Notebook VCORE
FDMS7602S Dual N-Channel PowerTrench
August 2010
®
MOSFET
2
5 6 7 8
MOSFET Maximum Ratings T
Symbol Parameter Q1 Q2 Units
V
DS
V
GS
I
D
P
D
TJ, T
STG
Drain to Source Voltage 30 30 V Gate to Source Voltage (Note 3) ±20 ±20 V Drain Current -Continuous (Package limited) TC = 25 °C 30 30
-Continuous (Silicon limited) T
-Continuous T
-Pulsed 40 60 Power Dissipation for Single Operation TA = 25 °C 2.2 Power Dissipation for Single Operation T Operating and Storage Junction Temperature Range -55 to +150 °C
= 25 °C unless otherwise noted
A
= 25 °C 50 80
C
= 25 °C 12
A
= 25 °C 1.0
A
1a
1a 1c
1
17
2.5
1.0
4 3 2 1
1b
1b 1d
A
W
Thermal Characteristics
R
θJA θJA
R
θJC
Thermal Resistance, Junction to Ambient 57 Thermal Resistance, Junction to Ambient 125 Thermal Resistance, Junction to Case 3.5 2
1a
1c
50
120
1b
1d
°C/WR
Package Marking and Ordering Information
1
www.fairchildsemi.com
Device Marking Device Package Reel Size Tape Width Quantity
©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C1
FDMS7602S FDMS7602S Power 56 13 ” 12 mm 3000 units
Page 2
FDMS7602S Dual N-Channel PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
BV
ΔBV ΔT
I
DSS
I
GSS
DSS
DSS J
Drain to Source Breakdown Voltage Breakdown Voltage Temperature
Coefficient
ID = 250 μA, VGS = 0 V ID = 1 mA, VGS = 0 V
ID = 250 μA, referenced to 25 °C ID = 1 mA, referenced to 25 °C
Zero Gate Voltage Drain Current VDS = 24 V, V
Gate to Source Leakage Current
VGS = 20 V, VDS= 0 V VGS = 20 V, VDS= 0 V
GS
= 0 V
Q1Q230
30
Q1 Q2
Q1 Q2
Q1 Q2
15 15
V
mV/°C
1
500 100
100
On Characteristics
V
GS(th)
ΔV ΔT
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage Gate to Source Threshold Voltage
Temperature Coefficient
Drain to Source On Resistance
Forward Transconductance
VGS = VDS, ID = 250 μA VGS = VDS, ID = 1 mA
ID = 250 μA, referenced to 25 °C ID = 1 mA, referenced to 25 °C
VGS = 10 V, ID = 12 A VGS = 4.5 V, ID = 10 A VGS = 10 V , ID = 12 A , TJ = 125 °C
VGS = 10 V, ID = 17 A VGS = 4.5 V, ID = 14 A VGS = 10 V , ID = 17 A , TJ = 125 °C
VDS = 5 V, ID = 12 A VDS = 5 V, ID = 17 A
Q1Q21
Q1 Q2
Q1
Q2
Q1 Q2
1.8
1
1.8
-6
-5
6.0
8.5
8.3
4.2
5.4
4.9
3 3
mV/°C
7.5 12 12
5.0
6.8
7.2
63 87
μA μA
nA nA
V
mΩ
S
®
MOSFET
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
g
Q
gs
Q
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge V
Total Gate Charge V
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Q1: V
= 15 V, VGS = 0 V, f = 1 MHZ
DS
Q2: V
= 15 V, VGS = 0 V, f = 1 MHZ
DS
Q1: VDD = 15 V, ID = 12 A, R
Q2: VDD = 15 V, ID = 17 A, R
= 0 V to 10 V
GS
Q1 VDD = 15 V,
= 0 V to 4.5 V
GS
ID = 12 A
Q2 VDD = 15 V, ID = 17 A
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
GEN
= 6 Ω
Q1 Q2
Q1
GEN
= 6 Ω
Q2 Q1
Q2 Q1
Q2 Q1
Q2 Q1
Q2 Q1
Q2
1315 2020
445 860
45 9570145
0.9
0.7
8.61118
2.5
3.81010 20
27
2.3
3.21010 20
33
9.31613
4.3
5.8
2.2
4.6
1750 2690
600
1145
20
32 43
28 46
22
pF
pF
pF
Ω
ns
ns
ns
ns
nC
nC
nC
nC
©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C1
www.fairchildsemi.com
Page 3
FDMS7602S Dual N-Channel PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Diode Characteristics
0.8
V
= 0 V, IS = 12 A (Note 2)
V
SD
t
rr
Q
rr
Notes: 1: R
θJA
by the user's board design.
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
a. 57 °C/W when mounted on
2
a 1 in
pad of 2 oz copper
c. 125 °C/W when mounted on a minimum pad of 2 oz copper
GS
V
= 0 V, IS = 17 A (Note 2)Q1Q2
GS
Q1 I
= 12 A, di/dt = 100 A/μs
F
Q2 I
= 17 A, di/dt = 300 A/μs
F
Q1 Q2
Q1 Q2
is guaranteed by design wh ile R
θJC
b. 50 °C/W when mounted on a 1 in
d. 120 °C/W when mounted on a minimum pad of 2 oz copper
2
pad of 2 oz copper
0.8 272943
103118
1.2
1.2
46
50
θCA
is determined
V
ns
nC
®
MOSFET
2: Pulse Test: Pulse Wid th < 300 μs, Duty cycle < 2.0%. 3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C1
www.fairchildsemi.com
Page 4
FDMS7602S Dual N-Channel PowerTrench
0.0 0.5 1.0 1.5 2.0
0
10
20
30
40
VGS = 4.5 V
VGS = 3.5 V
V
GS
= 6 V
VGS = 4 V
PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX
VGS = 10 V
I
D
, DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0 10203040
0
1
2
3
4
VGS = 4 V
PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
I
D
, DRAIN CURRENT (A)
V
GS
= 4.5 V
VGS = 6 V
VGS = 3.5 V
V
GS
= 10 V
-75 -50 -25 0 25 50 75 100 125 150
0.8
1.0
1.2
1.4
1.6
ID = 12 A V
GS
= 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
T
J
, JUNCTION TEMPERATURE (
o
C)
246810
0
10
20
30
40
TJ = 125 oC
ID = 12 A
TJ = 25 oC
V
GS
, GATE TO S OURCE VOLTAGE (V)
r
DS(on)
,
DRAIN TO
SOURCE ON-RESISTANCE
(mΩ)
PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX
1.5 2.0 2.5 3.0 3.5 4.0
0
10
20
30
40
TJ = 150 oC
V
DS
= 5 V
PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
I
D
, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.001
0.01
0.1
1
10
40
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
V
GS
= 0 V
I
S
, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Typical Characteristics (Q1 N-Channel)T
Figure 1. On Region Characteristics Figure 2. Norm a l ized O n -Resi s tance
= 25°C unless otherwise noted
J
vs Drain Current and Gate Voltage
®
MOSFET
Fi g ure 3 . Nor mali z ed On Resi stan ce
vs Junction Temperature
©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C1
Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode
Figure 4. On- Re sistance vs Gate to
Source Voltage
Forward Voltage vs Source Current
www.fairchildsemi.com
Page 5
FDMS7602S Dual N-Channel PowerTrench
0 5 10 15 20
0
2
4
6
8
10
ID = 12 A
V
DD
= 20 V
V
DD
= 10 V
V
GS
, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 15 V
0.1 1 10 30
10
100
1000
2000
f = 1 MHz V
GS
= 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOL TAGE (V)
C
rss
C
oss
C
iss
25 50 75 100 125 150
0
20
40
60
Limited by Package
V
GS
= 4.5 V
R
θJC
= 3.5 oC/W
V
GS
= 10 V
I
D
, DRAIN CURRENT (A)
T
C
, CASE TEMPERATURE (
o
C)
0.01 0.1 1 10 100
0.01
0.1
1
10
100
DC
100 ms
10 ms
1 ms
1s
I
D
, DRAIN CURRENT (A)
VDS, DRA IN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY r
DS(on)
SINGLE PULSE T
J
= MAX RATED
R
θJA
= 125
o
C/W
T
A
= 25
o
C
10s
100us
200
10
-4
10
-3
10
-2
10
-1
110
100 1000
1
10
100
1000
P
(PK)
, PEAK TRANSIENT POWER (W)
SINGLE PULSE R
θJA
= 125 oC/W
T
A
= 25 oC
t, PULSE WIDTH (s)
0.5
Typical Characteristics (Q1 N-Channel)T
Figure 7. Gate Charge Characteristics Figure 8. C a p a c i t ance vs Drain
= 25°C unless otherwise noted
J
to Source Voltage
®
MOSFET
Figure 9. Maximum Co ntinuous Drain
Current vs Case Temperature
©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C1
Figure 10. Fo rward Bi as Safe
Figure 11. Single Pulse Maximum Power Dissipation
Operating Area
www.fairchildsemi.com
Page 6
FDMS7602S Dual N-Channel PowerTrench
10
-4
10
-3
10
-2
10
-1
110
100 1000
0.001
0.01
0.1
1
SINGLE PULSE R
θJA
= 125 oC/W
(Note 1c)
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, Z
θJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
2
P
DM
t
1
t
2
NOTES: DUTY FACTOR: D = t1/t
2
PEAK TJ = PDM x Z
θJA
x R
θJA
+ T
A
Typical Characteristics (Q1 N-Channel)T
Figure 12. Junction-to-Ambient Transient Thermal Response Cu rve
= 25°C unless otherwise noted
J
®
MOSFET
©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C1
www.fairchildsemi.com
Page 7
Typical Characteristics (Q2 SyncFET)
0.0 0.5 1.0 1.5 2.0
0
20
40
60
VGS = 4.5 V
VGS = 3 V
V
GS
= 4 V
VGS = 3.5 V
PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX
VGS = 10 V
I
D
, DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0204060
0
1
2
3
4
5
VGS = 3.5 V
PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
I
D
, DRAIN CURRENT (A)
V
GS
= 4.5 V
VGS = 4 V
VGS = 3 V
V
GS
= 10 V
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
ID = 17 A V
GS
= 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
T
J
, JUNCTION TEMPERATURE (
o
C)
246810
0
5
10
15
20
TJ = 125 oC
ID = 17 A
TJ = 25 oC
V
GS
, GATE TO S OURCE VOLTAGE (V)
r
DS(on)
,
DRAIN TO
SOURCE ON-RESISTANCE
(mΩ)
PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX
1.5 2.0 2.5 3.0 3.5
0
20
40
60
TJ = 125 oC
V
DS
= 5 V
PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
I
D
, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.01
0.1
1
10
60
TJ = -55 oC
TJ = 25 oC
TJ = 125 oC
V
GS
= 0 V
I
S
, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 13. On-Region Characteristics Figure 14. Normalized on-Resistance vs Drain
FDMS7602S Dual N-Channel PowerTrench
Current and Gate Voltage
®
MOSFET
Figure 15. Normalized On-Resistance
vs Junction Temperature
©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C1
Figure 17. Transfer Characteristics Figure 18. Source to Drain Diode
Figure 16. On-Resistance vs Gate to
Source Voltage
Forward Voltag e vs Source Current
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Page 8
Typical Characteristics (Q2 SyncFET)
0 10203040
0
2
4
6
8
10
ID = 17 A
V
DD
= 20 V
V
DD
= 10 V
V
GS
, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 15 V
0.1 1 10 30
60
100
1000
3000
f = 1 MHz V
GS
= 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOL TAGE (V)
C
rss
C
oss
C
iss
25 50 75 100 125 150
0
20
40
60
80
100
V
GS
= 4.5 V
R
θJC
= 2 oC/W
V
GS
= 10 V
I
D
, DRAIN CURRENT (A)
T
C
, CASE TEMPERATURE (
o
C)
Limited by package
0.01 0.1 1 10 100
0.01
0.1
1
10
100
100 us
DC
100 ms
10 ms
1 ms
1 s
I
D
, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AR EA IS
LIMITED BY r
DS(on)
SINGLE PULSE T
J
= MAX RATED
R
θJA
= 120
o
C/W
T
A
= 25
o
C
10 s
200
10
-4
10
-3
10
-2
10
-1
11010210
3
1
10
100
1000
SINGLE PULSE R
θJA
= 120
o
C/W
T
A
= 25
o
C
P(
PK
), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
FDMS7602S Dual N-Channel PowerTrench
Figure 19. Gate Charge Charact er is ti cs
Figu re 21. Maxi mu m Contin uo us Drain
Current vs
Case Temperature
Figure 20. Capacitance vs Drain
to Source Voltage
®
MOSFET
Figure 22. Forward Bias Safe Operating Area
©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C1
Figure 23. Single Pulse Maximum Power Dissipation
www.fairchildsemi.com
Page 9
Typical Characteristics (Q2 SyncFET)
10
-4
10
-3
10
-2
10
-1
11010210
3
0.001
0.01
0.1
1
SINGLE PULSE R
θJA
= 120 oC/W
(Note 1d)
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE,
Z
θJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
2
P
DM
t
1
t
2
NOTES: DUTY FACTOR: D = t
1/t2
PEAK TJ = PDM x Z
θJA
x R
θJA
+ T
A
Figure 24. Junction-to-Ambient Transient Thermal Response Curve
FDMS7602S Dual N-Channel PowerTrench
®
MOSFET
©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C1
www.fairchildsemi.com
Page 10
0 50 100 150 200
-5
0
5
10
15
20
di/dt = 300 A/μs
CURRENT (A)
TIME (ns)
Figure 25. FDMS7602S SyncFET body
diode reverse recovery characteristic
0 5 10 15 20 25 30
1
10
100
1000
10000
TJ = 125 oC
TJ = 100 oC
TJ = 25 oC
I
DSS
, REVERSE LEAKAGE CURRENT (uA)
VDS, REVERSE VOLTAGE (V)
Typical Characteristics (continued)
SyncFET Schottky body diode Characteristics
FDMS7602S Dual N-Channel PowerTrench
Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 25 shows the reverse recovery characteristic of the FDMS7602S.
Schottky barrier diodes exhibit significant leakage at high tem­perature and high reverse voltage. This will increase the power in the device.
®
MOSFET
Figure 26. SyncFET body diode reverse leakage versus drain-source voltage
©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C1
www.fairchildsemi.com
Page 11
Dimensional Outline and Pad Layout
FDMS7602S Dual N-Channel PowerTrench
®
MOSFET
©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C1
www.fairchildsemi.com
Page 12
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®
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®
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™
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FDMS7602S Dual N-Channel PowerTrench
®
MOSFET
LIFE SUPPORT POLICY
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As used here in:
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PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative / In Design
Preliminary First Production
No Identification Needed Full Production
Obsolete Not In Production
©2010 Fairchild Semiconductor Corporation FDMS7602S Rev.C1
Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.
Rev. I48
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