Datasheet FDML7610S Datasheet (Fairchild)

Page 1
Dual N-Channel PowerTrench® MOSFET
N-Channel: 30 V, 30 A, 7.5 mΩ N-Channel: 30 V, 28 A, 4.2 mΩ
Features
Q1: N-Channel
Max rMax r
Q2: N-Channel
Max rMax r
RoHS Compliant
= 7.5 mΩ at VGS = 10 V, ID = 12 A
DS(on)
= 12 mΩ at VGS = 4.5 V, ID = 10 A
DS(on)
= 4.2 mΩ at VGS = 10 V, ID = 17 A
DS(on)
= 5.5 mΩ at VGS = 4.5 V, ID = 14 A
DS(on)
General Description
This device includes two specialized N-Channel MOSFETs in a dual MLP package.The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET (Q2) have been designed to provide optimal power efficiency.
Applications
ComputingCommunicationsGeneral Purpose Point of Load
FDML7610S Dual N-Channel PowerTrench
April 2010
®
MOSFET
Notebook V
D1
D1
Pin 1
Top
MLP 3X4.5
MOSFET Maximum Ratings T
Symbol Parameter Q1 Q2 Units
V
DS
V
GS
I
D
P
D
TJ, T
STG
Drain to Source Voltage 30 30 V Gate to Source Voltage (Note 3) ±20 ±20 V Drain Current -Continuous (Package limited) TC = 25 °C 30 28
-Continuous (Silicon limited) T
-Continuous T
-Pulsed 40 40 Power Dissipation for Single Operation TA = 25 °C 2.1 T Operating and Storage Junction Temperature Range -55 to +150 °C
D1
G1
D1
S1/D2
S2
G2
Bottom
= 25 °C unless otherwise noted
A
S2
S2
CORE
S2 S2 S2 D1
G2 G1
= 25 °C 40 60
C
= 25 °C 12
A
= 25 °C 0.8
A
1a
1a 1c
17
2.2
0.9
1b
1b 1d
Thermal Characteristics
R
θJA θJA
R
θJC
Thermal Resistance, Junction to Ambient 60 Thermal Resistance, Junction to Ambient 150 Thermal Resistance, Junction to Case 4 3.5
1a
1c
56
140
1b
1d
Package Marking and Ordering Information
D1 D1
A
W
°C/WR
Device Marking Device Package Reel Size Tape Width Quantity
FDML7610S FDML7610S MLP3X4.5 13 ” 12 mm 3000 units
©2010 Fairchild Semiconductor Corporation FDML7610S Rev.C
1
www.fairchildsemi.com
Page 2
FDML7610S Dual N-Channel PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
BV
∆BV ∆T
I
DSS
I
GSS
DSS
DSS J
Drain to Source Breakdown Voltage Breakdown Voltage Temperature
Coefficient Zero Gate Voltage Drain Current VDS = 24 V, V
Gate to Source Leakage Current VGS = 20 V, VDS= 0 V
On Characteristics
V
GS(th)
∆V ∆T
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage Gate to Source Threshold Voltage
Temperature Coefficient
Drain to Source On Resistance
Forward Transconductance
ID = 250 µA, VGS = 0 V ID = 1 mA, VGS = 0 V
ID = 250 µA, referenced to 25 °C ID = 10 mA, referenced to 25 °C
= 0 V
GS
VGS = VDS, ID = 250 µA VGS = VDS, ID = 1 mA
ID = 250 µA, referenced to 25 °C ID = 10 mA, referenced to 25 °C
VGS = 10 V, ID = 12 A VGS = 4.5 V, ID = 10 A VGS = 10 V , ID = 12 A , TJ = 125 °C
VGS = 10 V, ID = 17 A VGS = 4.5 V, ID = 14 A VGS = 10 V , ID = 17 A , TJ = 125 °C
VDS = 5 V, ID = 12 A VDS = 5 V, ID = 17 A
Q1Q230
30
Q1 Q2
Q1 Q2
Q1 Q2
Q1Q21
Q1 Q2
Q1
Q2
Q1 Q2
1
15 14
1.8
1.8
6.0
8.5
8.3
3.2
4.1
4.1 63
86
V
mV/°C
1
500µAµA 100
100nAnA
3 3
-6
-5
mV/°C
7.5 12 12
4.2
5.5
6
V
mΩ
S
®
MOSFET
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
Q
g
g
gs
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge V
Total Gate Charge V
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Q1: V
= 15 V, VGS = 0 V, f = 1 MHZ
DS
Q2: V
= 15 V, VGS = 0 V, f = 1 MHZ
DS
Q1: VDD = 15 V, ID = 12 A, VGS = 10 V, R
GEN
= 6 Ω
Q2: VDD = 15 V, ID = 17 A, VGS = 10 V, R
= 0 V to 10 V
GS
GEN
= 6 Ω
Q1 VDD = 15 V,
= 0 V to 4.5 V
GS
ID = 12 A
Q2 VDD = 15 V, ID = 17A
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
Q1 Q2
1315
1750
2960
3940
455
1135
600
1510
45
10070150
0.9
0.6
8.61318
2.5410
20 31
2.3
3.11010 20
43
9.32013
4.3
8.9
2.2
4.7
23
10 32
49
28 60
28
pF
pF
pF
Ω
ns
ns
ns
ns
nC
nC
nC
nC
©2010 Fairchild Semiconductor Corporation FDML7610S Rev.C
2
www.fairchildsemi.com
Page 3
FDML7610S Dual N-Channel PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Diode Characteristics
0.8
V
= 0 V, IS = 12 A (Note 2)
V
SD
t
rr
Q
rr
Notes:
1: R
θJA
by the user's board design.
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
is determined with the devic e mo un ted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
a. 60 °C/W when mounted on
2
a 1 in
pad of 2 oz copper
c. 150 °C/W when mounted on a minimum pad of 2 oz copper
GS
V
= 0 V, IS = 17 A (Note 2)Q1Q2
GS
Q1 I
= 12 A, di/dt = 100 A/µs
F
Q2 I
= 17 A, di/dt = 300 A/µs
F
Q1 Q2
Q1 Q2
is guaranteed by design while R
θJC
b. 56 °C/W when mounted on a 1 in
d. 140 °C/W when mounted on a minimum pad of 2 oz copper
2
pad of 2 oz copper
0.8 273543
104018
1.2
1.2
56
64
θCA
is determined
V
ns
nC
®
MOSFET
2: Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%. 3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
©2010 Fairchild Semiconductor Corporation FDML7610S Rev.C
3
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Page 4
FDML7610S Dual N-Channel PowerTrench
Typical Characteristics (Q1 N-Channel) T
40
30
20
10
, DRAIN CURRENT (A)
D
I
VGS = 3.5 V
0
0.0 0.5 1.0 1 .5 2.0
Figure 1.
1.6
ID = 12 A V
= 10 V
GS
1.4
1.2
NORMALIZED
1.0
DRAIN TO SOURCE ON-RESISTANCE
0.8
-75 -50 -25 0 25 50 75 100 125 150
T
Fi g u r e 3. No r m alized O n Resist a n ce
vs Junction Temperature
VGS = 10 V
V
= 6
V
GS
VGS = 4.5 V
VGS = 4 V
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
V
,
DRAIN TO SOURCE VOLTAGE (V)
DS
On Region Characteristics Figure 2.
, JUNCTION TEMPERATURE (
J
o
C)
= 25 °C unless otherwise noted
J
4
3
VGS = 3.5 V
2
NORMALIZED
1
DRAIN TO SOURCE ON-RESISTANCE
0
0 10203040
I
,
D
Norm a l i z e d O n - R e sistance
vs Drain Current and Gate Voltage
40
)
Ω
m
(
30
20
DRAIN TO
,
DS(on)
r
10
SOURCE ON-RESISTANCE
0
246810
Figure 4.
TJ = 125 oC
TJ = 25 oC
V
,
GATE TO SOURCE VOLTAGE (V)
GS
On-Res istance vs Gate to
Source Voltage
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
VGS = 4 V
VGS = 6 V
DRAIN CURRENT (A)
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
ID = 12 A
V
GS
= 4.5 V
V
GS
= 10 V
®
MOSFET
40
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
30
V
= 5 V
DS
20
10
, DRAIN CURRENT (A)
D
I
0
1.5 2.0 2.5 3.0 3.5 4.0
TJ = 150 oC
TJ = 25 oC
VGS, GATE TO SOURCE V OLTAGE (V)
Figure 5. Transfer Characteristics
©2010 Fairchild Semiconductor Corporation FDML7610S Rev.C
40
V
= 0 V
GS
10
1
0.1
0.01
, REVERSE DRAIN CURRENT (A)
S
TJ = -55 oC
I
0.001
0.0 0.2 0.4 0.6 0.8 1.0 1.2
TJ = 150 oC
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6.
Source to Drain Diode
TJ = 25 oC
TJ = -55 oC
Forward Voltage vs Source Current
4
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Page 5
FDML7610S Dual N-Channel PowerTrench
Typical Characteristics (Q1 N-Channel) T
10
ID = 12 A
8
V
= 10 V
DD
6
4
V
DD
2
, GATE TO SOURCE VOLTAGE (V)
GS
V
0
0 5 10 15 20
Figure 7.
Qg, GATE CHARGE (nC)
Gate Charge Characteristics Figure 8.
60
V
= 10 V
GS
40
V
= 4.5 V
GS
Limited by Package
20
, DRAIN CURRENT (A)
D
I
0
25 50 75 100 125 150
T
, CASE TEMPERATURE (
C
= 20 V
VDD = 15 V
R
= 4 oC/W
θJC
o
C)
= 25 °C unless otherwise noted
J
2000 1000
100
CAPACITANCE (pF)
f = 1 MHz
= 0 V
V
GS
10
0.1 1 10 30
VDS, DRAIN TO SOURCE VOLTAGE (V)
Capa c i t a nce v s D r ain
to Source Voltage
100
10
1
THIS AREA IS
LIMITED BY r
SINGLE PULSE
, DRAIN CURRENT (A)
0.1
T
D
J
I
R
θJA
T
A
0.01
0.01 0.1 1 10 100
DS(on)
= MAX RATED
o
= 150
C/W
o
= 25
C
VDS, DRAIN to SOURCE VOLTAGE (V)
C
iss
C
oss
C
rss
®
MOSFET
100us
1 ms
10 ms
100 ms
1s
10s
DC
200
Figure 9.
Maximum Continuous Drain Current vs
Case Temperature
1000
100
10
, PEAK TRANSIENT POWER (W)
1
(PK)
P
0.5
-4
10
©2010 Fairchild Semiconductor Corporation FDML7610S Rev.C
-3
10
Figure 10. Forward Bias Safe Operating Area
SINGLE PULSE R
= 150 oC/W
θJA
= 25 oC
T
A
-2
10
-1
10
t, PULSE WIDTH (s)
110
100 1000
Figure 11. Single Pulse Maximum Power Dissipation
5
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Page 6
FDML7610S Dual N-Channel PowerTrench
Typical Characteristics (Q1 N-Channel) T
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
θJA
Z
0.1
IMPEDANCE,
0.01
NORMALIZED THERMAL
0.001
0.1
0.05
0.02
0.01
SINGLE PULSE R
= 150 oC/W
θJA
(Note 1c)
-4
10
-3
10
-2
10
10
t, RECTANGULAR PULSE DURATION (sec)
Figure 12. Junction-to-Ambient Transient Thermal Response Cu rve
= 25 °C unless otherwise noted
J
NOTES: DUTY FACTOR: D = t
PEAK TJ = PDM x Z
-1
110
P
DM
t
1
t
2
1/t2
x R
+ T
θJA
θJA
A
100 1000
®
MOSFET
©2010 Fairchild Semiconductor Corporation FDML7610S Rev.C
6
www.fairchildsemi.com
Page 7
FDML7610S Dual N-Channel PowerTrench
Typical Characteristics (Q2 SyncFET) T
40
30
20
10
, DRAIN CURRENT (A)
D
I
0
0.0 0.2 0.4 0.6 0.8
VGS = 3.5 V
VGS = 3 V
V
DS
Figure 13. On-Region Characteristics
1.6
ID = 17 A V
= 10 V
GS
1.4
1.2
1.0
NORMALIZED
0.8
DRAIN TO SOURCE ON-RESISTANCE
0.6
-75 -50 -25 0 25 50 75 100 125 150
T
J
Figure 15. Normalized On-Resistance
vs Junction Temperature
VGS = 10 V
VGS = 4.5 V
VGS = 4 V
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
, DRAIN TO SOURCE VOLTAGE (V)
, JUNCTION TEMPERATURE (
o
C)
= 25 oC unlenss otherwise noted
J
6
5
VGS = 3 V
4
3
2
NORMALIZED
1
DRAIN TO SOURCE ON-RESISTANCE
0
0 10203040
I
D
Figure 14. Normalized on-Resistance vs Drain
Current and Gate Voltage
20
(mΩ)
15
10
DRAIN TO
,
DS(on)
r
5
SOURCE ON-RESISTANCE
0
246810
V
, GATE TO S OURCE VOLTAGE (V)
GS
Figure 16. On-Resistance vs Gate to
Source Voltage
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
VGS = 3.5 V
VGS = 4 V
, DRAIN CURRENT (A)
ID = 17 A
TJ = 125 oC
TJ = 25 oC
V
GS
PULSE DURATION = 80 µ s DUTY CYCLE = 0.5% MAX
= 4.5 V
V
= 10 V
GS
®
MOSFET
40
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
V
= 5 V
30
20
10
, DRAIN CURRENT (A)
D
I
0
1.5 2.0 2.5 3.0 3.5
DS
TJ = 125 oC
TJ = 25 oC
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. Transfer Characteristics
©2010 Fairchild Semiconductor Corporation FDML7610S Rev.C
40
V
= 0 V
GS
10
TJ = 125 oC
1
TJ = 25 oC
0.1
, REVERSE DRAIN CURRENT (A)
S
TJ = -55 oC
I
0.01
0.0 0.2 0.4 0.6 0.8 1.0 1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
TJ = -55 oC
Figure 18. Source to Drain Diode
Forward Voltage vs Source Current
7
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Page 8
FDML7610S Dual N-Channel PowerTrench
Typical Characteristics (Q2 SyncFET) T
10
ID = 17A
8
V
= 10 V
6
4
2
, GATE TO SOURCE VOLTAGE (V)
GS
V
0
0 1020304050
Figure 19. Gate Charge Charac ter is tics
80
60
V
GS
40
DRAIN CURRENT (A)
,
20
D
I
Limited by package
0
25 50 75 100 125 150
DD
V
DD
Qg, GATE CHARGE (nC)
V
= 10 V
GS
= 4.5 V
T
,
CASE TEMPERATURE
C
= 20 V
VDD = 15 V
R
θ
JC
o
(
C
)
= 3.5 oC/W
o
= 25
C unless otherwise noted
J
5000
1000
CAPACITANCE (pF)
100
60
0.1 1 10 30
100
10
1
, DRAIN CURRENT (A)
0.1
D
I
0.01
0.01 0.1 1 10 100
f = 1 MHz
= 0 V
V
GS
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 20. Capacitance vs Drain
to Source Voltage
THIS A R EA IS
LIMITED BY r
SINGLE PULSE T
J
R
θ
T
A
DS(on
)
= MAX RATED
= 140 oC/W
JA
= 25 oC
VDS, DRAIN to SOURCE VOLTAGE (V)
C
C
rss
C
iss
oss
1 ms 10 ms
100 ms
1s
10s
DC
®
MOSFET
200
Figure 21.
Maximun Continuous Drain
Current vs Case Temperature
300
100
10
), PEAK TRANSIENT POWER (W)
PK
P(
1
0.001 0.01 0.1 1 10 1 00 1000
©2010 Fairchild Semiconductor Corporation FDML7610S Rev.C
Figure 22. Forward Bias Safe
Operating Area
t, PULSE WIDTH (sec)
Figure 23. Single Pulse Maximum Power Dissipation
8
SINGLE PULSE R
T
θJA
= 25
A
= 140
o
o
C/W
C
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Page 9
FDML7610S Dual N-Channel PowerTrench
Typical Characteristics (Q2 SyncFET) T
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
θJA
Z
0.1
IMPEDANCE,
0.01
NORMALIZED THERMAL
0.001
0.1
0.05
0.02
0.01
SINGLE PULSE R
= 140 oC/W
θJA
Note 1d
-3
10
-2
10
-1
10
t, RECTANGULAR PULSE DURATION (sec)
Figure24. Junction-to-Ambient Transient Thermal Response Curve
= 25 oC unless otherwise noted
J
NOTES: DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z
110
P
DM
t
1
t
2
2
x R
+ T
θJA
θJA
A
100 1000
®
MOSFET
©2010 Fairchild Semiconductor Corporation FDML7610S Rev.C
9
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Page 10
Typical Characteristics (continued)
SyncFET Schottky body diode Characteristics
FDML7610S Dual N-Channel PowerTrench
Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 25 shows the reverse recovery characteristic of the FDML7610S.
20
15
di/dt = 300 A/µs
10
5
CURRENT (A)
0
-5 0 50 100 150 200 250
TIME (ns)
Figure 25. FDML7610S SyncFET body diode reverse recovery characteristic
Schottky barrier diodes exhibit significant leakage at high tem­perature and high reverse voltage. This will increase the power in the device.
10000
1000
100
10
, REVERSE LEAKAGE CURRENT (A)
1
DSS
I
0 5 10 15 20 25 30
TJ = 125 oC
TJ = 100 oC
TJ = 25 oC
VDS, REVERSE VOLTAGE (V)
Figure 26. SyncFET body diode reverse leakage versus drain-source voltage
®
MOSFET
©2010 Fairchild Semiconductor Corporation FDML7610S Rev.C
10
www.fairchildsemi.com
Page 11
Dimensional Outline and Pad Layout
FDML7610S Dual N-Channel PowerTrench
®
MOSFET
©2010 Fairchild Semiconductor Corporation FDML7610S Rev.C
11
www.fairchildsemi.com
Page 12
TRADEMARKS
tm
®
tm
tm
The following includes registered and unregistered trademarks and se rvice marks, owned by Fairchild Semiconductor and/or it s global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
AccuPower™ Auto-SPM™ Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ DEUXPEED Dual Cool™ EcoSPARK EfficentMax™ ESBC™
Fairchild Fairchild Semiconductor FACT Quiet Series™ FACT FAST FastvCore™ FETBench™ FlashWriter FPS™
®
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*
F-PFS™
®
FRFET Global Power Resource Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MicroPak2™ MillerDrive™
®
MotionMax™ Motion-SPM™ OptiHiT™ OPTOLOGIC OPTOPLANAR
®
®
SM
®
PDP SPM™
Power-SPM™ PowerTrench PowerXS™ Programmable Active Droop™ QFET QS™ Quiet Series™ RapidConfigure™
Saving our world, 1mW/W/kW at a time™ SignalWise™ SmartMax™ SMART START™ SPM STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS™ SyncFET™ Sync-Lock™
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™
®
®* The Power Franchise
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®
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®
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
FDML7610S Dual N-Channel PowerTrench
®
MOSFET
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used here in:
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PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative / In Design
Preliminary First Production
No Identification Needed Full Production
Obsolete Not In Production
©2010 Fairchild Semiconductor Corporation FDML7610S Rev.C
Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time withou t notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.
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