Datasheet FDMF6705B Datasheet (Fairchild)

March 2012

FDMF6705B - Extra-Small, High-Performance, HighFrequency DrMOS Module

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Benefits

 Ultra-Compact 6x6mm PQFN, 72% Space-Saving

Compared to Conventional Discrete Solutions

 Fully Optimized System Efficiency  Clean Switching Waveforms with Minimal Ringing  High-Current Handling

Features

 Over 93% Peak-Efficiency  High-Current Handling of 40A at 12V  High-Current Handling of 38A at 19V

IN

 High-Performance PQFN Copper-Clip Package  3-State 3.3V PWM Input Driver  Skip-Mode SMOD# (Low-Side Gate Turn-Off) Input  Thermal Warning Flag for Over-Temperature

Condition

 Driver Output Disable Function (DISB# Pin)  Internal Pull-Up and Pull-Down for SMOD# and

DISB# Inputs, Respectively

 Fairchild PowerTrench

Clean Voltage Waveforms and Reduced Ringing

®

Technology MOSFETs for

 Fairchild SyncFET™ (Integrated Schottky Diode)

Technology in the Low-Side MOSFET

 Integrated Bootstrap Schottky Diode  Adaptive Gate Drive Timing for Shoot-Through

Protection

 Under-Voltage Lockout (UVLO)  Optimized for Switching Frequencies up to 1MHz  Low-Profile SMD Package  Fairchild Green Packaging and RoHS Compliance  Based on the Intel

®

4.0 DrMOS Standard

Description

The XS™ DrMOS family is Fairchild’s next-generation, fully optimized, ultra-compact, integrated MOSFET plus driver power stage solution for high-current, highfrequency, synchronous buck DC-DC applications. The FDMF6705B integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6x6mm PQFN package.

With an integrated approach, the complete switching power stage is optimized with regards to driver and MOSFET dynamic performance, system inductance, and power MOSFET R Fairchild's high-performance PowerTrench technology, which dramatically reduces switch ringing, eliminating the need for a snubber circuit in most buck converter applications.

A new driver IC with reduced dead times and propagation delays further enhances the performance of this part. A thermal warning function warns of a potential over-temperature situation. The FDMF6705B also incorporates features, such as Skip Mode (SMOD), for improved light-load efficiency, along with a three-state

3.3V PWM input for compatibility with a wide range of PWM controllers.

XS™ DrMOS uses

DS(ON).

®

MOSFET

Applications

High-Performance Gaming Motherboards

  Notebook Computers, V-Core and Non-V-Core  Compact Blade Servers, V-Core and Non-V-Core

DC-DC Converters

 Desktop Computers, V-Core and Non-V-Core

DC-DC Converters

 Workstations  High-Current DC-DC Point-of-Load (POL)

Converters

 Small Form-Factor Voltage Regulator Modules

Ordering Information

Part Number Current Rating Package Top Mark

FDMF6705B 40A 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package FDMF6705B

Typical Application Circuit

g

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

V5V

C

VDRV

DISB#

PWM Input

OFF

ON

Open-Drain Output

DrMOS Block Diagram

VCIN

DISB#

PWM

SMOD#

THWN#

VDRV

FDMF6705B

CGND

VIN

R

BOOT

PHASE

VSWH

PGND

Figure 1. Typical Application Circuit

VDRV

BOOT

VIN

C

BOOT

3V ~ 24V

L

OUT

V

OUT

C

OUT

C

VIN

BOOT

VIN

VCIN

DISB#

PWM

THWN#

R

UP_PWM

R

DN_PWM

CGND

10µA

UVLO

V

CIN

Temp. Sense

Input

3-

State

Logic

Q1

D

Boot

GH

Lo

ic

GL

Logic

V

CIN

10µA

SMOD#

Level Shift

Dead Time

Control

GH

30kΩ

V

DRV

GL

30kΩ

HS Power MOSFET

PHASE

VSWH

Q2 LS Power MOSFET

PGND

Figure 2. DrMOS Block Diagram

Pin Configuration

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 3. Bottom View Figure 4. Top View

Pin Definitions

Pin # Name Description

When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW,

1 SMOD#

2 VCIN IC bias supply. Minimum 1µF ceramic capacitor is recommended from this pin to CGND.

3 VDRV

4 BOOT

5, 37, 41 CGND IC ground. Ground return for driver IC.

6 GH For manufacturing test only. This pin must float; must not be connected to any pin.

7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.

8 NC

9 - 14, 42 VIN Power input. Output stage supply voltage.

15, 29 -

35, 43

16 – 28 PGND Power ground. Output stage ground. Source pin of low-side MOSFET.

36 GL For manufacturing test only. This pin must float; must not be connected to any pin.

38 THWN#

39 DISB#

40 PWM PWM signal input. This pin accepts a three-state logic-level PWM signal from the controller.

VSWH

the low-side driver is disabled. This pin has a 10µA internal pull-up current source. Do not add a noise filter capacitor.

Power for gate driver. Minimum 1µF ceramic capacitor is recommended, connected as close as possible from this pin to CGND.

Bootstrap supply input. Provides voltage supply to high-side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE.

No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience.

Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection.

Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module.

Output disable. When LOW, this pin disables power MOSFET switching (GH and GL are held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter capacitor.

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

V

Supply Voltage Referenced to CGND -0.3 6.0 V

CIN

V

Drive Voltage Referenced to CGND -0.3 6.0 V

DRV

V

Output Disable Referenced to CGND -0.3 6.0 V

DISB#

V

PWM Signal Input Referenced to CGND -0.3 6.0 V

PWM

V

Skip Mode Input Referenced to CGND -0.3 6.0 V

SMOD#

VGL Low Gate Manufacturing Test Pin Referenced to CGND -0.3 6.0 V

V

Thermal Warning Flag Referenced to CGND -0.3 6.0 V

THWN#

VIN Power Input Referenced to PGND, CGND -0.3 30.0 V

V

Bootstrap Supply

BOOT

VGH High Gate Manufacturing Test Pin

V

PHASE Referenced to CGND -0.3 30.0 V

PHS

V

Switch Node Input

SWH

V

Bootstrap Supply

BOOT

I

THWN# Sink Current -0.1 7.0 mA

THWN#

I

O(AV)

θ

JPCB

Output Current

Junction-to-PCB Thermal Resistance 3.5 °C/W

(1)

TA Ambient Temperature Range -40 +125 °C

TJ Maximum Junction Temperature +150 °C

T

Storage Temperature Range -55 +150 °C

STG

ESD Electrostatic Discharge Protection

Note:

1. I

is rated using Fairchild’s DrMOS evaluation board, TA = 25°C, natural convection cooling. This rating is limited

O(AV)

by the peak DrMOS temperature, T

= 150°C, and varies depending on operating conditions and PCB layout. This

J

rating can be changed with different application settings.

Referenced to VSWH, PHASE -0.3 6.0 V

Referenced to CGND -0.3 30.0 V

Referenced to VSWH, PHASE -0.3 6.0 V

Referenced to CGND -0.3 30.0 V

Referenced to PGND, CGND (DC Only) -0.3 30.0 V

Referenced to PGND, <20ns -8.0 33.0 V

Referenced to VDRV 22.0 V

Referenced to VDRV, <20ns 25.0 V

fSW=300kHz, VIN=19V, VO=1.0V 38

fSW=1MHz, VIN=19V, VO=1.0V 35

Human Body Model, JESD22-A114 2000

Charged Device Model, JESD22-C101 1000

A

V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

V

Control Circuit Supply Voltage 4.5 5.0 5.5 V

CIN

V

Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V

DRV

VIN Output Stage Supply Voltage 3.0 12.0 24.0

Note:

2. Operating at high V

can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes

IN

during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must

remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information.

(2)

V

Electrical Characteristics

Typical values are VIN = 12V, V

Symbol Parameter Condition Min. Typ. Max. Unit

Basic Operation

IQ Quiescent Current IQ=I

UVLO UVLO Threshold V

UVLO

PWM Input (V

R

V

t

D_HOLD-OFF

V

HiZ_PWM

PWM Input (V

R

V

t

D_HOLD-OFF

V

HiZ_PWM

DISB# Input

V

t

PD_DISBL

t

PD_DISBH

SMOD# Input

V

IH_SMOD

V

t

PD_SLGLL

t

PD_SHGLH

UVLO Hysteresis 0.4 V

_Hyst

= V

CIN

Pull-Up Impedance 26 kΩ

UP_PWM

Pull-Down Impedance 12 kΩ

DN_PWM

PWM High Level Voltage

IH_PWM

3-State Upper Threshold

TRI_HI

3-State Lower Threshold

TRI_LO

PWM Low Level Voltage

IL_PWM

= 5V ±10%)

DRV

3-State Shut-off Time 160 200 ns

3-State Open Voltage 1.40 1.60 1.90 V

= V

CIN

Pull-Up Impedance 26 kΩ

UP_PWM

Pull-Down Impedance 12 kΩ

DN_PWM

PWM High Level Voltage

IH_PWM

3-State Upper Threshold

TRI_HI

3-State Lower Threshold

TRI_LO

PWM Low Level Voltage

IL_PWM

= 5V ±5%)

DRV

3-State Shut-off Time 160 200 ns

3-State Open Voltage 1.45 1.60 1.80 V

High-Level Input Voltage 2 V

IH_DISB

Low-Level Input Voltage 0.8 V

IL_DISB

I

Pull-Down Current 10 µA

PLD

Propagation Delay

High-Level Input Voltage 2 V

Low-Level Input Voltage 0.8 V

IL_SMOD

I

Pull-Up Current 10 µA

PLU

Propagation Delay

= 5V, V

CIN

= 5V, and T

DRV

VCIN+IVDRV

Rising 2.9 3.1 3.3 V

CIN

= +25°C unless otherwise noted.

A

, PWM=LOW or HIGH or Float 2 mA

1.88 2.25 2.61

1.84 2.20 2.56

0.70 0.95 1.19

0.62 0.85 1.13

2.00 2.25 2.50

1.94 2.20 2.46

0.75 0.95 1.15

0.66 0.85 1.09

PWM=GND, Delay Between DISB# from HIGH to LOW to GL from HIGH to LOW

PWM=GND, Delay Between DISB# from LOW to HIGH to GL from LOW to HIGH

PWM=GND, Delay Between SMOD# from HIGH to LOW to GL from HIGH to LOW

PWM=GND, Delay Between SMOD# from LOW to HIGH to GL from LOW to HIGH

25 ns

10 ns

Continued on the following page…

V

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Electrical Characteristics

Typical values are VIN = 12V, V

Symbol Parameter Condition Min. Typ. Max. Unit

Thermal Warning Flag

T

Activation Temperature 150 °C

ACT

T

Reset Temperature 135 °C

RST

R

Pull-Down Resistance I

THWN

250ns Timeout Circuit

t

D_TIMEOUT

High-Side Driver

R

SOURCE_GH

R

t

D_DEADON

t

PD_PLGHL

t

PD_PHGHH

t

PD_TSGHH

Low-Side Driver

R

SOURCE_GL

R

t

D_DEADOFF

t

PD_PHGLL

t

PD_TSGLH

Boot Diode

Timeout Delay

Output Impedance, Sourcing Source Current=100mA 1 Ω

Output Impedance, Sinking Sink Current=100mA 0.8 Ω

SINK_GH

t

Rise Time GH=10% to 90%, C

R_GH

t

Fall Time GH=90% to 10%, C

F_GH

LS to HS Deadband Time

PWM LOW Propagation Delay

PWM HIGH Propagation Delay (SMOD Held LOW)

Exiting 3-State Propagation Delay

Output Impedance, Sourcing Source Current=100mA 1 Ω

Output Impedance, Sinking Sink Current=100mA 0.5 Ω

SINK_GL

t

Rise Time GL=10% to 90%, C

R_GL

t

Fall Time GL=90% to 10%, C

F_GL

HS to LS Deadband Time

PWM-HIGH Propagation Delay

Exiting 3-State Propagation Delay

VF Forward-Voltage Drop IF=10mA 0.35 V

VR Breakdown Voltage IR=1mA 22 V

= 5V, V

CIN

= 5V, and T

DRV

=5mA 30 Ω

PLD

SW=0V, Delay Between GH from HIGH to LOW and GL from LOW to HIGH

GL going LOW to GH going HIGH, 1V GL to 10% GH

PWM going LOW to GH going LOW, V

IL_PWM

PWM going HIGH to GH going HIGH, V

IH_PWM

PWM (from 3-State) going HIGH to GH going HIGH, V

SW going LOW to GL going HIGH,

2.2V SW to 10% GL

PWM going HIGH to GL going LOW, V

IH_PWM

PWM (from 3-State) going LOW to GL going HIGH, V

= +25°C unless otherwise noted.

A

=1.1nF 6 ns

LOAD

=1.1nF 5 ns

LOAD

to 90% GH

to 10% GH (SMOD=LOW)

to 10% GH

IH_PWM

=2.7nF 10 ns

LOAD

=2.7nF 8 ns

LOAD

to 90% GL

to 10% GL

IL_PWM

250 ns

10 ns

16 30 ns

30 ns

12 ns

9 25 ns

20 ns

PWM

VSW

V

IH_PWM

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

V

IL_PWM

GL

GH

to

VSWH

90%

1.0V 10%

90%

H

t

PD PHGLL

t D_DEADON

10%

t

PD PLGHL

Figure 5. PWM Timing Diagram

1.2V

t

D_DEADOFF

t

D_TIMEOUT

( 250ns Timeout)

2.2V

Typical Performance Characteristics

0

Test Conditions: VIN=12V, V unless otherwise specified.

=1.0V, V

OUT

CIN

=5V, V

DRV

=5V, L

=320nH, TA=25°C, and natural convection cooling,

OUT

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

45 40

(A)

35

OUT

30 25 20 15 10

VIN= 12V, V

5

Module Output c urr ent, I

0

0 25 50 75 100 125 150

Θ

JPCB

= 3.5°C/W

fSW= 300kHz

= 1.0V

OUT

fSW= 1MHz

PCB Temperature (°C)

Figure 6. Safe Operating Area Figure 7. Module Power Loss vs. Output Current

12 11 10

9 8 7 6 5 4 3

Module Power Loss (W)

2 1 0

0 5 10 15 20 25 30 35 40

300kHz 500kHz 800kHz 1MHz

Output Current, I

VIN= 19V, V

OUT

(A)

= 1V

11 10

9 8 7 6 5 4 3

Module Pow er Loss (W)

2 1 0

0 5 10 15 20 25 30 35 40

300kHz 500kHZ 800kHz 1MHz

Output Curre nt, I

9

8

7

6

5

4

3

Module Power Loss (W)

2

1

Vin = 19V, Iout = 30A Vin = 12V, Iout = 30A Vin = 19V, Iout = 20A Vin = 12V, Iout = 20A

200 300 400 500 600 700 800 900 100

VIN= 12V, V

OUT

(A)

OUT

= 1V

Module Switching Fre quency, fSW(kHz)

Figure 8. Module Power Loss vs. Output Current Figure 9. Module Power Loss vs. Switching

Frequency

1.20

1.15

1.10

1.05

1.00

I

= 30A, fSW= 300kHz

OUT

Norma lize d Module Powe r Los s

0.95 4 6 8 10121416182

Module Input V oltage, VIN(V)

1.15

1.10

1.05

1.00

0.95

VIN= 12V, I

= 30A, fSW= 300kHz

OUT

Norma liz e d Module Powe r Los s

0.90

4.50 4.75 5.00 5.25 5.50

Driver Sup p l y Voltage, V

DRV

and V

CIN

(V)

Figure 10. Normalized Power Loss vs. Input Voltage Figure 11. Normalized Power Loss vs. Driver

Supply Voltage

Typical Performance Characteristics (Continued)

Test Conditions: V

=12V, V

IN

unless otherwise specified.

=1.0V, V

OUT

=5V, V

CIN

DRV

=5V, L

OUT

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

=320nH, TA=25°C, and natural convection cooling,

1.9 VIN= 12V, I

1.7

1.5

1.3

1.1

= 30A, fSW= 300kHz

OUT

Normalized Module Power Loss

0.9

0.5 1.0 1.5 2.0 2.5 3.0 3.5

Output Voltage, V

OUT

(V)

Figure 12. Normalized Power Loss vs.

Output Voltage

(mA)

+ I

VCIN

VDRV

34

30

26

22

18

14

VIN= 12V, I

= 0A, fSW= 300kHz

OUT

1.05

1.04

1.03

1.02

1.01

1.00

0.99

Norm a lize d M odule Pow e r Los s

0.98 225 275 325 375 425

VIN= 12V, I

= 30A, fSW= 300kHz

OUT

Output Inductance, L

OUT

(nH)

Figure 13. Module Power Loss vs.

Output Inductance

12

(mA)

VCIN

+ I

11

VDRV

10

VIN= 12V, I

= 0A, fSW= 300kHz

OUT

10

Driver Supply Current, I

6

200 400 600 800 1000

Module Swit ching Fr equenc y , fSW(kHz)

Driver Supply Current, I

9

4.5 4.75 5 5.25 5.5

Driver Supply Voltage, V

DRV

& V

CIN

(V)

Figure 14. Driver Supply Current vs. Frequency Figure 15. Driver Supply Current vs. Driver

Supply Voltage

1.10

OUT

300kHz 1MHz

(A)

1.08

1.06

1.04

1.02

1.00

Normalized Driver Supply Current

0.98 0 5 10 15 20 25 30 35 40

Module Out put Cur re nt, I

Figure 16. Normalized Driver Supply Current vs.

Output Current

3.0

TA= 25°C

2.5

V

IH_PWM

2.0

1.5

1.0

0.5

V

TRI_HI

V

HiZ_PWM

V

TRI_LO

V

IL_PWM

PWM Threshold Voltage (V)

0.0

4.50 4.75 5.00 5.25 5.50

Driver Supply Voltage, V

CIN

(V)

Figure 17. PWM Thresholds vs. Driver

Supply Voltage

Typical Performance Characteristics (Continued)

Test Conditions: V

=12V, V

IN

unless otherwise specified.

=1.0V, V

OUT

=5V, V

CIN

DRV

=5V, L

OUT

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

=320nH, TA=25°C, and natural convection cooling,

3.0

V

= 5V

CIN

2.5

2.0

1.5

1.0

0.5

PWM Threshold V olt age (V)

0.0

-50 -25 0 25 50 75 100 12 5 150

V

IH_PWM

TRI_HI

V

TRI_LO

V

IL_PWM

Driver IC Junction Temperature, TJ(oC)

2.2

TA= 25°C

2.0

V

1.8

1.6

1.4

SMOD# Threshold Voltage (V)

1.2

4.50 4.75 5.00 5.25 5.50

IH_SMOD

Driver Supply Voltage, V

V

IL_SMOD

CIN

(V)

Figure 18. PWM Thresholds vs. Temperature Figure 19. SMOD# Thresholds vs. Driver Supply

Voltage

2.0

V

= 5V

CIN

1.9

1.8

1.7

1.6

1.5

SMOD Thre s hold Voltage (V)

1.4

1.3

-50 -25 0 25 50 75 100 125 150

V

IH_SMOD

V

IL_SMOD

Driver IC Jun ct ion Temperature (oC)

-9.0

V

= 5V

(uA)

-9.5

PLU

CIN

-10.0

-10.5

-11.0

-11.5

SMOD# Pull-up Current, I

-12.0

-50 -25 0 25 50 75 100 125 150

Driver IC Ju nctio n Temperature, TJ(oC)

Figure 20. SMOD# Thresholds vs. Temperature Figure 21. SMOD# Pull-Up Current vs. Temperature

2.1

TA= 25oC

2.0

1.9

1.8

1.7

1.6

1.5

1.4

DISB# Threshold Voltage (V)

1.3

4.50 4.75 5.00 5.25 5.50

Driver Supply Voltage, V

V

IH_DISB

V

IL_DISB

CIN

(V)

Figure 22. DISB# Thresholds vs. Driver

2.00

V

= 5V

CIN

1.90

1.80

1.70

1.60

1.50

DISB Threshold Voltage (V)

1.40

-50 -25 0 25 50 75 100 125 150

V

IH_DISB

V

IL_DISB

Driver IC Junction Temperature, TJ(°C)

Figure 23. DISB# Thresholds vs. Temperature

Supply Voltage

Typical Performance Characteristics (Continued)

Test Conditions: V

=12V, V

IN

unless otherwise specified.

=1.0V, V

OUT

11.5

(uA)

11.0

PLD

10.5

10.0

DISB# Pull-Down Current, I

9.5

-50 -25 0 25 50 75 100 125 150

=5V, V

CIN

V

= 5V

CIN

Driver IC Junction Temperature, TJ(°C)

DRV

=5V, L

OUT

Figure 24. DISB# Pull-Down Current vs. Temperature

=320nH, TA=25°C, and natural convection cooling,

I

PLD

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Functional Description

A

p

The FDMF6705B is a driver-plus-FET module optimized for the synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each part is capable of driving speeds up to 1MHz.

VCIN and Disable

The VCIN pin is monitored by an Under-Voltage Lockout (UVLO) circuit. When V is enabled. When V disabled (GH, GL=0). The driver can also be disabled by pulling the DISB# pin LOW (DISB# < V holds both GL and GH LOW regardless of the PWM input state. The driver can be enabled by raising the DISB# pin voltage HIGH (DISB# > V

Table 1. UVLO and Disable Logic

UVLO DISB# Driver State

0 X Disabled (GH, GL=0)

1 0 Disabled (GH, GL=0)

1 1 Enabled (See Table 2)

1 Open Disabled (GH, GL=0)

Note:

3. DISB# internal pull-down current source is 10µA.

Thermal Warning Flag

The FDMF6705B provides a thermal warning flag (THWN) to warn of over-temperature conditions. The thermal warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached. The THWN output returns to a highimpedance state once the temperature falls to the reset temperature (135°C). The THWN output requires a pullup resistor, which can be connected to VCIN. THWN does NOT disable the DrMOS module.

HIGH

THWN Logic State

Normal Operation

LOW

Figure 25. THWN Operation

rises above ~3.1V, the driver

CIN

falls below ~2.7V, the driver is

CIN

), which

IL_DISB

).

IH_DISB

135°C Reset

150°C

ctivation

Tem

erature

Thermal Warning

T

J_driverIC

3-State PWM Input

The FDMF6705B incorporates a three-state PWM input gate drive design. The three-state gate drive has both logic HIGH level and LOW level, along with a three-state shutdown window. When the PWM input signal enters and remains within the three-state window for a defined hold-off time (t

D_HOLD-OFF

), both GL and GH are pulled LOW. This feature enables the gate drive to shut down both high-and low-side MOSFETs to support features such as phase shedding, which is a common feature on multiphase voltage regulators.

Operation when Exiting Three-State Condition

When exiting a valid three-state condition, the FDMF6705B design follows the PWM input command. If the PWM input goes from three-state to LOW, the lowside MOSFET is turned on. If the PWM input goes from three-state to HIGH, the high-side MOSFET is turned on. This is illustrated in Figure 26. The FDMF6705B design allows for short propagation delays when exiting

the three-state window (see Electrical Characteristics).

Low-Side Driver

The low-side driver (GL) is designed to drive a groundreferenced low R

N-channel MOSFET. The bias

DS(ON)

for GL is internally connected between VDRV and CGND. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB#=0V), GL is held LOW.

High-Side Driver

The high-side driver is designed to drive a floating Nchannel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the internal Schottky diode and external bootstrap capacitor (C held at PGND, allowing C through the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from C Q1 turns on, V

+ V

V

IN

BOOT

rises to VIN, forcing the BOOT pin to

SWH

, which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to VSWH. C VDRV when VSWH falls to PGND. GH output is inphase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is held within the three-state window for longer than the three-state hold-off time, t

). During startup, VSWH is

BOOT

to charge to VDRV

BOOT

and delivered to the gate of Q1. As

is then recharged to

BOOT

D_HOLD-OFF

.

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Adaptive Gate Drive Circuit

_

V

The driver IC advanced design ensures minimum MOSFET dead time, while eliminating potential shootthrough (cross-conduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to ensure they do not conduct simultaneously. Figure 26 provides the relevant timing waveforms. To prevent overlap during the LOW-to-HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes

V

IH_PWM

t

).

R_GH

HIGH, Q2 turns off after a propagation delay (t

PD_PHGLL

Once the GL pin is discharged below ~1V, Q1 turns on after adaptive delay, t

D_DEADON

.

V

IH_PWM

V

IL_PWM

PWM

To preclude overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the VSWH pin. When the PWM signal goes LOW, Q1 turns off after a propagation delay (t

PD_PLGHL

Once the VSWH pin falls below ~2.2V, Q2 turns on after adaptive delay, t monitored. When V

D_DEADOFF

GS(Q1)

. Additionally, V

GS(Q1)

is discharged below ~1.2V, a secondary adaptive delay is initiated, which results in Q2 being driven on after t

D_TIMEOUT

state. This function is implemented to ensure C

, regardless of SW

BOOT

recharged each switching cycle in the event that the SW voltage does not fall below the 2.2V adaptive threshold. Secondary delay t

V

TRI_HI

t

F_GH

IH_PWM

D_TIMEOUT

is longer than t

D_DEADOFF

V

TRI_HI

TRI_LO

IL_PWM

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

).

is

.

less than

t

OFF

GH

to

VSWH

GL

CCM

t

PD_PHGLL

90%

1.0V

t

D_DEADON

t

D_HOLD

2.2

10%

t

PD

PLGHL

t

D_DEADOFF

t

R_GL

D_HOLD -

OFF

-

DCM

t

3

F_GL

Enter

State

-

t

Exit

3-State

PD_TSGHH

t

D_HOLD -OFF

Notes: t

= propagation delay from external sign al (PWM, SMOD#, etc.) to IC generated signal. Example (t

PD_xxx

= delay from IC generated signal to IC generated signal. Example (t

t

D_xxx

PWM Exiting 3-state t

= PWM rise to LS VGS fall, V

PD_PHGLL

= PWM fall to HS VGS fall, V

t

PD_PLGHL

t

= PWM rise to HS VGS rise, V

PD_PHGHH

SMOD# Dead Times t

= SMOD# fall to LS VGS fall, V

PD_SLGLL

= SMOD# rise to LS VGS rise, V

t

PD_SHGLH

to 90% LS VGS t

IH_PWM

to 90% HS VGS t

IL_PWM

to 10% HS VGS (SMOD# held LOW)

IH_PWM

to 90% LS VGS t

IL_SMOD

to 10% LS VGS t

IH_SMOD

– LS VGS (GL) LOW to HS VGS (GH) HIGH)

D_DEADON

PD_TSGHH

PD_TSGLH

D_DEADON

D_DEADOFF

Figure 26. PWM and 3-StateTiming Diagram

DCM

t

PD_TSGHH

Enter

3

-State

PD_PHGLL

= PWM 3-state to HIGH to HS VGS rise, V

= PWM 3-state to LOW to LS VGS rise, V

= LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS

= VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS

Exit 3 S t at e

– PWM going HIGH to LS VGS (GL) going LOW)

less than

t

D_HOLD -

IH_PWM

IL_PWM

t

D_HOLD

OFF

Enter

3 -

to 10% HS VGS

to 10% LS VGS

State

-OFF

t

PD_TSGLH

3-

Exit

State

90%

10%

V

90%

1

IN

OUT

0%

Skip Mode (SMOD)

V

#

The SMOD function allows higher converter efficiency

under light-load conditions. During SMOD, the low-side FET gate signal is disabled (held LOW), preventing discharging of the output capacitors as the filter inductor current attempts reverse current flow – also known as Diode Emulation Mode. When the SMOD# pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode, gating on the low-side FET. When the SMOD# pin is pulled LOW, the low-side FET is gated off. The SMOD# pin is connected to the PWM controller, which enables or disables SMOD automatically when the controller detects light-load condition from output current sensing. Normally this pin

is active LOW. See Figure 27 for timing delays.

SMOD

Table 2. SMOD Logic

DISB# PWM SMOD# GH GL

0 X X 0 0

1 3-State X 0 0

1 0 0 0 0

1 1 0 1 0

1 0 1 0 1

1 1 1 1 0

Note:

4. The SMOD feature is intended to have low

propagation delay between the SMOD signal and the low-side FET VGS response time to control diode emulation on a cycle-by-cycle basis.

V

IL_SMOD

IH_SMOD

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

V

IH_PWM

10%

CCM

t

PD_PHGHH

HS turn -on with SMOD# LOW

DCM

t

Delay from SMOD# going

HIGH to LS VGSHIGH

PD_SHGLH

10%

V

OUT

PWM

GH

to

SWH

V

SWH

GL

IH_PWM

t

PD_PHGLL

t

D_DEADON

90%

1.0V

t

PD_PLGHL

V

IL_PWM

90%

10%

2.2V

t

D_DEADOFF

10%

CCM

t

PD_SLGLL

Delay from SMOD# going

LOW to LS VGSLOW

Figure 27. SMOD Timing Diagram

Application Information

V

R

A

V

A

V

R

A

V

A

V

R

V

Supply Capacitor Selection

For the supply inputs (VDRV and VCIN), a local ceramic bypass capacitor is required to reduce noise and to supply peak transient currents during gate drive switching action. It is recommended to use a minimum capacitor value of 1µF X7R or X5R. Keep this capacitor close to the VCIN and VDRV pins and connect it to the GND plane with vias.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor (C

), as shown in Figure 28. A bootstrap capacitance

BOOT

of 100nF X7R or X5R capacitor is typically adequate. A series bootstrap resistor may be needed for specific applications to improve switching noise immunity. The boot resistor (R near the maximum rated V controlling the high-side MOSFET turn-on slew rate and VSHW overshoot. Typical R are effective in reducing VSWH overshoot.

) may be required when operating

BOOT

5V

I

5V

and is effective at

IN

values from 0.5 to 3.0Ω

BOOT

CVDRV

CIN

C

CIN

VCIN Filter

The VDRV pin provides power to the gate drive of the high-side and low-side power MOSFETs. In most cases, VDRV can be connected directly to VCIN, which supplies power to the logic circuitry of the gate driver. For additional noise immunity, an RC filter can be inserted between VDRV and VCIN. Recommended values of 10Ω (R and 1µF (C

VCIN

) placed between VDRV and VCIN

VCIN

) from VCIN to CGND, Figure 28.

Power Loss and Efficiency

Measurement and Calculation

Refer to Figure 29 for power-loss testing method. Power loss calculations are:

P

=(VIN x IIN) + (V5V x I5V) (W)

IN

P

SW=VSW

P

OUT=VOUT

P

LOSS_MODULE=PIN

P

LOSS_BOARD=PIN

EFF

MODULE

BOARD

C

VIN

x I

(W)

OUT

x I

(W)

OUT

- PSW (W)

- P

OUT

=100 x PSW/PIN (%)

=100 x P

I

IN

V

IN

OUT/PIN

(W)

(%)

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

(1)

(2)

(3)

(4)

(5)

(6)

(7)

DISB#

PWM

Input

OFF

ON

Open -

Drain

Output

5V

DISB#

PWM Input

OFF

ON

Open -

Drain

Output

VDRV

VCIN

DISB#

PWM

FDM 67 5

FDMF6705B

SMOD#

THWN

CGND

Figure 28. Block Diagram with V

I

5V

C

VDRV

DISB#

PWM

SMOD

THWN#

FDMF6705B

FDM 5

CGND

VIN

BOOT

C

BOOT

VIN

BOOT

SW

I

IN

C

CIN

BOOT

SW

L

OUT

Filter

IN

L

OUT

I

V

C

OUT

I

OUT

C

OUT

VSWH

PHASE

PGND

VCIN

VIN

BOOT

VSWH

PHASE

PGND

Figure 29. Power Loss Measurement

PCB Layout Guidelines

Figure 30 provides an example of a proper layout for critical components. All of the high-current paths, such as V

, V

IN

SWH

, and GND copper, should be short

OUT

and wide for low inductance and resistance. This technique achieves a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance.

The following guidelines are recommendations for the PCB designer:

1. Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This helps reduce the high-current power loop inductance and the input current ripple induced by the power MOSFET switching operation.

2. The V

copper trace serves two purposes. In

SWH

addition to being the high-frequency current path from the DrMOS package to the output inductor, it also serves as a heat sink for the low-side MOSFET in the DrMOS package. The trace should be short and wide enough to present a low-impedance path for the high-frequency, high-current flow between the DrMOS and inductor to minimize losses and temperature rise. Note that the VSWH node is a high-voltage and high-frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace also acts as a heat sink for the lower FET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission.

3. An output inductor should be located close to the FDMF6705B to minimize the power loss due to the VSWH copper trace. Care should also be taken so the inductor dissipation does not heat the DrMOS.

®

4. PowerTrench

MOSFETs are used in the output stage. The power MOSFETs are effective at minimizing ringing due to fast switching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The resistor and capacitor need to be of proper size for the power dissipation.

5. VCIN, VDRV, and BOOT capacitors should be placed as close as possible to the VCIN to CGND, VDRV to CGND, and BOOT to PHASE pins to ensure clean and stable power. Routing width and length should be considered.

6. Include a trace from PHASE to VSWH to improve

noise margin. Keep the trace as short as possible.

7. The layout should include a place holder to insert a small-value series boot resistor (R boot capacitor (C

) and DrMOS BOOT pin. The

BOOT

) between the

BOOT

BOOT-to-VSWH loop size, including R C

, should be as small as possible. The boot

BOOT

resistor may be required when operating near the maximum rated VIN. The boot resistor is effective at controlling the high-side MOSFET turn-on slew rate and VSHW overshoot. R

can improve noise

BOOT

operating margin in synchronous buck designs that have noise issues due to ground bounce or high positive and negative VSWH ringing. However, inserting a boot resistance lowers the DrMOS efficiency. Efficiency versus noise trade-offs must be considered. R

values from 0.5 to 3.0Ω are

BOOT

typically effective in reducing VSWH overshoot.

The VIN and PGND pins handle large current transients with frequency components greater than 100MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is

discouraged

since this adds inductance to the

power path. This added inductance in series with either the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSWH ringing.

8. CGND pad and PGND pins should be connected to the GND plane copper with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to faulty operation of the gate driver and MOSFETs.

9. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to the PGND capacitor. This may lead to excess current flow through the BOOT diode.

10. The SMOD# and DISB# pins have weak internal pull-up and pull-down current sources, respectively. These pins should not have any noise filter capacitors. Do not to float these pins unless absolutely necessary.

11. Use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current flow and heat conduction. Vias should be relatively large and of reasonably low inductance. Critical high-frequency components,

, C

such as R

BOOT

, the RC snubber, and bypass

BOOT

capacitors should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible, they should be connected from the backside through a network of low-inductance vias.

BOOT

and

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 30. PCB Layout Example

Bottom View Top View

Physical Dimensions

0.10 C

2X

6.00

B

A

6.00

PIN#1 INDICATOR

2.50

31

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module

5.80

4.50

2130

20

0.40

0.65

11

0.35

0.50 (0.70)

0.40

2.00±0.10

0.10 C

0.08

0.40

C

FRONT VIEW

(2.20)

21

20

11

10

(0.20)

BOTTOM VIEW

1.10

0.90

0.30

0.20

TOP VIEW

4.40±0.10

0.05

0.00

DETAIL 'A'

SCALE: 2:1

(0.20)

0.10 C

2X

SEE

DETAIL 'A'

0.10 CAB

0.05

0.30 (40X)

0.20

30

31

2.40±0.10

1.50±0.10

40

1

2.00±0.10

0.50

C

SEATING PLANE

0.25

1.60

40

0.60

0.50 TYP

C

0.20

0.50

0.30

NOTES: UNLESS OTHERWISE SPECIFIED

A) DOES NOT FULLY CONFORM TO JEDEC

B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN40AREV2

1

2.10

LAND PATTERN

RECOMMENDATION

PIN #1 INDICATOR

(40X)

REGISTRATION MO-220, DATED MAY/2005.

10

0.15

2.10

Figure 31. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0mm Package

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

.

FDMF6705B - Extra-Small, High-Performance, High-Frequency DrMOS Module