Datasheet FDMC8200S Datasheet (Fairchild)

FDMC8200S

Bottom

Power33

Pin 1

G1

D1

D

2

/

S

1

G2

S2

V

IN

V

IN

V

IN

V

IN

S

W

I

T

C

H

N

O

D

E

G

LS

GND

G

HS

Dual N-Channel PowerTrench® MOSFET

30 V, 10 mΩ, 20 mΩ

FDMC8200S Dual N-Channel PowerTrench

March 2011

Features

Q1: N-Channel

 Max r  Max r

Q2: N-Channel

 Max r  Max r  RoHS Compliant

= 20 mΩ at VGS = 10 V, ID = 6 A

DS(on)

= 32 mΩ at VGS = 4.5 V, ID = 5 A

DS(on)

= 10 mΩ at VGS = 10 V, ID = 8.5 A

DS(on)

= 13.5 mΩ at VGS = 4.5 V, ID = 7.2 A

DS(on)

General Description

This device includes two specialized N-Channel MOSFETs in a due power33(3mm X 3mm MLP) package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous MOSFET (Q2) have been designed to provide optimal power efficiency.

Applications

 Mobile Computing  Mobile Internet Devices  General Purpose Point of Load

Q 2

5 6 7 8

Q 1

4 3 2 1

®

MOSFET

MOSFET Maximum Ratings T

Symbol Parameter Q1 Q2 Units

V

DS

V

GS

I

D

E

AS

P

D

TJ, T

STG

Drain to Source Voltage 30 30 V Gate to Source Voltage (Note 4) ±20 ±20 V Drain Current -Continuous (Package limited) TC = 25 °C 18 13

-Continuous (Silicon limited) T

-Continuous T

-Pulsed 40 27 Single Pulse Avalanche Energy (Note 3) 12 32 Power Dissipation for Single Operation TA = 25°C 1.9 Power Dissipation for Single Operation T Operating and Storage Junction Temperature Range -55 to +150 °C

= 25°C unless otherwise noted

C

= 25 °C 23 46

C

= 25 °C 6

A

= 25°C 0.7

A

1a

1a 1c

8.5

2.5

1.0

1b

1b 1d

A

W

Thermal Characteristics

R

θJA θJA

R

θJC

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDMC8200S FDMC8200S Power 33 13” 12

Thermal Resistance, Junction to Ambient 65 Thermal Resistance, Junction to Ambient 180 Thermal Resistance, Junction to Case 7.5 4.2

1a

1c

mm 3000 units

50

125

1b

1d

°C/WR

FDMC8200S Dual N-Channel PowerTrench

Electrical Characteristics T

= 25°C unless otherwise noted

J

Symbol Parameter Test Conditions Type Min Typ Max Units

Off Characteristics

BV

ΔBV ΔT

I

DSS

I

GSS

DSS

DSS J

Drain to Source Breakdown Voltage Breakdown Voltage Temperature

Coefficient Zero Gate Voltage Drain Current V

Gate to Source Leakage Current V

= 250 μA, VGS = 0 V

D

I

= 1mA, V

D

I

= 250 μA, referenced to 25°C

D

I

= 1mA, referenced to 25°C

D

= 24 V, V

DS

= ±20 V, V

GS

= 0 V

GS

= 0 V

DS

Q1Q230

30

Q1 Q2

V

14 13

mV/°C

1

500 100

100nAnA

I

On Characteristics

V

GS(th)

ΔV ΔT

r

DS(on)

g

FS

GS(th)

J

Gate to Source Threshold Voltage Gate to Source Threshold Voltage

Temperature Coefficient

Static Drain to Source On Resistance

Forward Transconductance

= VDS, I

GS

V

= VDS, ID = 1mA

GS

I

= 250 μA, referenced to 25°C

D

I

= 1mA, referenced to 25°C

D

= 10 V, ID = 6 A

V

GS

V

= 4.5 V, ID = 5 A

GS

V

= 10 V, ID = 6 A, T

GS

V

= 10 V, ID = 8.5 A

GS

V

= 4.5 V, ID = 7.2 A

GS

V

= 10 V, ID = 8.5 A, T

GS

V

= 5 V, ID = 6 A

DD

V

= 5 V, ID = 8.5 A

DD

= 250 μA

D

= 125°C

J

= 125°C

J

Q1Q21.0

1.0

Q1 Q2

Q1

Q2

Q1 Q2

2.3

2.0

-5

-6

16 24 22

7.8

10.3

11.4 29

43

3.0

3.0 mV/°C

20 32 28

10.0

13.5

13.1

μA

V

mΩ

S

®

MOSFET

Dynamic Characteristics

C

iss

C

oss

C

rss

R

g

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Gate Resistance

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q

g(TOT)

gs

gd

Turn-On Delay Time

Rise Time

Turn-Off Delay Time

Fall Time

Total Gate Charge V

Gate to Source Charge

Gate to Drain “Miller” Charge

= 15 V, VGS = 0 V, f = 1 MHZ

V

DS

Q1 V

= 15 V, ID = 1 A,

DD

V

= 10 V, R

GS

GEN

= 6 Ω

Q2

= 15 V, ID = 1 A,

V

DD

V

= 10 V, R

GS

= 0 V to 10 V

GS

= 0 V to 4.5 V

GS

GEN

= 6 Ω

Q1 V

DD

I

= 6 A

D

Q2 V

DD

I

= 8.5 A

D

= 15 V,

= 15 V

Q1 Q2

Q1Q20.2

0.2

Q1 Q2

495

660

1080

1436

145

195

373

495

20 35

1.4

1.2

11

7.62015

3.1

1.81010 35

21

1.3

8.51017

7.3

15.71022

3.1

7.2

1.8

3 1

1.9

30 52

4.2

3.6

56 34

4.3 10

pF

Ω

ns

nC

Electrical Characteristics T

a.65 °C/W when mounted on a 1 in

2

pad of 2 oz copper

c. 180 °C/W when mounted on a minimum pad of 2 oz copper

b.50 °C/W when mounted on a 1 in

2

pad of 2 oz copper

d. 125 °C/W when mounted on a minimum pad of 2 oz copper

= 25°C unless otherwise noted

J

Symbol Parameter Test Conditions Type Min Typ Max Units

Drain-Source Diode Characteristics

= 0 V, IS = 6 A (Note 2)

V

GS

V

SD

t

rr

Q

rr

Notes:

1. R

is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R

θJA

by the user's board design.

Source-Drain Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

V

= 0 V, IS = 8.5 A (Note 2)

GS

V

= 0 V, IS = 1.3 A (Note 2)

GS

Q1 I

= 6 A, di/dt = 100 A/s

F

Q2 I

= 8.5 A, di/dt = 300 A/s

F

Q1 Q2 Q2

Q1 Q2

is guaranteed by design while R

θJC

1.2

0.8

1.2

0.8

0.6 13

24

20

32

2.31510

24

θCA

is determined

ns

nC

FDMC8200S Dual N-Channel PowerTrench

V

®

MOSFET

2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.

3.Starting Q1: T = 25 °C, L = 1 mH, I = 5 A, Vgs = 10V, Vdd = 27V, 100% test at L = 3 mH, I = 4 A; Q2: T = 25°C, L = 1 mH, I = 8 A, Vgs = 10V, Vdd = 27V, 100% test at L = 3 mH, I = 3.2 A.

4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.

FDMC8200S Dual N-Channel PowerTrench

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0

10

20

30

40

VGS = 10 V

VGS = 4 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

VGS = 3.5 V

VGS = 4.5 V

VGS = 6 V

I

D

, DRAIN CURRENT (A)

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

0 10203040

0

1

2

3

4

VGS = 3.5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

NORMALIZED

DRAIN TO SOURCE ON-RESISTANCE

I

D

, DRAIN CURRENT (A)

V

GS

= 4 V

VGS = 4.5 V

VGS = 6 V

V

GS

= 10 V

-75 -50 -25 0 25 50 75 100 125 150

0.8

1.0

1.2

1.4

1.6

ID = 6 A V

GS

= 10 V

NORMALIZED

DRAIN TO SOURCE ON-RESISTANC E

T

J

, JUNCTION TEMPERATURE (

o

C)

246810

0

20

40

60

80

100

TJ = 125 oC

ID = 6 A

TJ = 25 oC

V

GS

, GATE TO SOURCE VOLTA GE (V)

r

DS(on)

,

DRAIN TO

SOURCE ON-RESISTANCE

(mΩ)

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

2.0 2.5 3.0 3.5 4.0 4.5

0

10

20

30

40

TJ = 150 oC

V

DS

= 5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

TJ = -55 oC

TJ = 25 oC

I

D

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

0.2 0.4 0.6 0.8 1.0 1.2

0.001

0.01

0.1

1

10

40

TJ = -55 oC

TJ = 25 oC

TJ = 150 oC

V

GS

= 0 V

I

S

, REVERSE DRAIN CURRENT (A)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Typical Characteristics (Q1 N-Channel) T

Figure 1.

On Region Characteristics Figure 2.

= 25°C unless otherwise noted

J

Nor ma liz ed On- Res is tan ce

vs Drain Current and Gate Voltage

®

MOSFET

Fi gu re 3. No rmalized On Resistance

vs Junction Temperature

Figure 5. Transfer Characteristics

Figure 4.

On-Resi stance vs Gate to

Source Voltage

Figure 6.

Source to Drain Diode

Forward Voltage vs Source Current

FDMC8200S Dual N-Channel PowerTrench

02468

0

2

4

6

8

10

ID = 6 A

VDD = 10 V

V

DD

= 15 V

V

GS

, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 20 V

0.1 1 10 30

10

100

1000

f = 1 MHz V

GS

= 0 V

CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

rss

C

oss

C

iss

0.01 0.1 1 7

1

2

3

4

5

6

7

8

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I

AS

, AVALANCHE CURRENT (A)

25 50 75 100 125 150

0

5

10

15

20

25

Limited by Package

R

θJC

= 7.5 oC/W

V

GS

= 4.5 V

V

GS

= 10 V

I

D

, DRAIN CURRENT (A)

T

c

, CASE TEMPERATURE (

o

C)

0.01 0.1 1 10 100200

0.01

0.1

1

10

50

10 s

1 s

DC

100 ms

10 ms

1 ms

100 us

I

D

, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS A REA IS LIMITED BY r

DS(on)

SINGLE PULSE T

J

= MAX RATED

R

θJA

= 125

o

C/W

T

A

= 25

o

C

0.01 0.1 1 10 100200

0.001

0.01

0.1

1

10

100

10 s

1 s

DC

100 ms

10 ms

1 ms

100 us

I

D

, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA IS LIMITED BY r

DS(on)

SINGLE PULSE T

J

= MAX RA TED

R

θJA

= 180

o

C/W

T

C

= 25

o

C

0.001 0.01 0.1 1 1 0 100 1000

0.1

1

10

100

SINGLE PULSE R

θJA

= 125

o

C/W

T

A

= 25

o

C

VGS = 10 V

P(

PK

), PEAK TRANSIENT POWER (W)

t, PULSE WIDTH (sec)

Typical Characteristics (Q1 N-Channel) T

Figure 7.

Gate Charge Characteristics Figure 8.

= 25°C unless otherwise noted

J

Cap aci tan ce v s Dr ain

to Source Voltage

®

MOSFET

Figure 9.

Unc l amp ed I n duc tiv e

Switching Capability

Figure 11. Forward Bias Safe

Op

erating Area

Figure 10.

Ma ximum Conti nuous Drain

Current vs Case Temperature

Figure 12.

Single Pu lse Maxim um

Power Dissipation

FDMC8200S Dual N-Channel PowerTrench

P

DM

t

1

t

2

NOTES: DUTY FACTOR: D = t1/t

2

PEAK TJ = PDM x Z

θJC

x R

θJc

+ T

C

10

-4

10

-3

10

-2

10

-1

110

100 1000

0.003

0.01

0.1

1

SINGLE PULSE R

θJA

= 180 oC/W

DUTY CYCLE-DESCENDING ORDER

NORMALIZED THERMAL

IMPEDANCE,

Z

θJA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

2

Typical Characteristics (Q1 N-Channel) T

Figure 13. Junction-to-Ambient Transient Thermal Response Curve

= 25°C unless otherwise noted

J

®

MOSFET

FDMC8200S Dual N-Channel PowerTrench

0.00.51.01.5

0

9

18

27

VGS = 3.5 V

VGS = 3 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

VGS = 4.5 V VGS = 4 V

VGS = 10 V

I

D

, DRAIN CURRENT (A)

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

091827

1

2

3

4

VGS = 3.5 V

PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX

NORMALIZED

DRAIN TO SOURCE ON-RESISTANCE

I

D

, DRAIN CURRENT (A)

V

GS

= 4 V

VGS = 4.5 V

VGS = 3 V

V

GS

= 10 V

-75 -50 -25 0 25 50 75 100 125 150

0.8

1.0

1.2

1.4

1.6

ID = 8.5 A V

GS

= 10 V

NORMALIZED

DRAIN TO SOURCE ON-RESISTANCE

T

J

, JUNCTION TEMPERATURE (

o

C)

246810

0

20

40

60

80

100

TJ = 125 oC

ID = 8.5 A

TJ = 25 oC

V

GS

, GATE TO SOURCE VOLTA GE (V)

r

DS(on)

,

DRAIN TO

SOURCE ON-RESISTANCE

(mΩ)

PULSE DURA TION = 80 μs DUTY CYCLE = 0.5% MAX

1.0 1.5 2.0 2.5 3.0 3.5 4.0

0

9

18

27

TJ = 150 oC

V

DS

= 5 V

PULSE DURA TION = 80 μs DUTY CYCLE = 0.5% MAX

TJ = -55 oC

TJ = 25 oC

I

D

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.001

0.01

0.1

1

10

30

TJ = -55 oC

TJ = 25 oC

TJ = 150 oC

V

GS

= 0 V

I

S

, REVERSE DRAIN CURRENT (A)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Typical Characteristics (Q2 N-Channel) T

Figure 14. On- Region Characteristics Figure 15. Normalized on-Resistance vs Drain

= 25 °C unless otherwise noted

J

Current and Gate Voltage

®

MOSFET

Figure 16. Normalized On-Resistance

vs Junction Temperature

Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode

Figure 17. On-Resistance vs Gate to

Source Voltage

Forward Voltag e vs Source Current

FDMC8200S Dual N-Channel PowerTrench

0246810121416

0

2

4

6

8

10

ID = 8.5 A

VDD = 20 V

V

DD

= 10 V

V

GS

, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 15 V

0.1 1 10 30

10

100

1000

3000

f = 1 MHz V

GS

= 0 V

CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

rss

C

oss

C

iss

0.01 0.1 1 10 30

1

10

20

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I

AS

, AVALANCHE CURRENT (A)

25 50 75 100 125 150

0

3

6

9

12

15

Limited by package

V

GS

= 4.5 V

R

θJA

= 50 oC/W

V

GS

= 10 V

I

D

, DRAIN CURRENT (A)

T

A

, CASE TEMPERATURE (

o

C)

0.01 0.1 1 10 100200

0.01

0.1

1

10

50

10 s

1 s

DC

100 ms

10 ms

1 ms

100 us

I

D

, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS A REA IS LIMITED BY r

DS(on)

SINGLE PULSE T

J

= MAX RATED

R

θJA

= 125

o

C/W

T

A

= 25

o

C

0.001 0.01 0.1 1 10 100 1000

0.1

1

10

100

SINGLE PULSE R

θJA

= 125

o

C/W

T

A

= 25

o

C

VGS = 10 V

P(

PK

), PEAK TRANSIENT POWER (W)

t, PULSE WIDTH (sec)

Typical Characteristics (Q2 N-Channel) T

Figure 20. Gate Charge Characteristics

= 25°C unless otherwise noted

J

Figure 21. Capacitance vs Drain

to Source Volt age

®

MOSFET

Figure 22. Unclamped Inductive

Switching Capability

Figur e 24 . Forward Bias Sa fe

Operating Area

Figure 2 3. Maxim um Con ti nu ous Dr ai n

Current vs Case Temperature

Figure 25. Single Pulse Maximum Power

Dissipation

10

-4

10

-3

10

-2

10

-1

110

100 1000

0.001

0.01

0.1

1

SINGLE PULSE R

θJA

= 125 oC/W

(Note 1b)

DUTY CYCLE-DESCENDING ORDER

NORMALIZED THERMAL

IMPEDANCE,

Z

θJA

t, RECTANGULAR PU L SE D U R ATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

2

P

DM

t

1

t

2

NOTES: DUTY FACTOR: D = t1/t

2

PEAK TJ = PDM x Z

θJC

x R

θJC

+ T

C

FDMC8200S Dual N-Channel PowerTrench

Typical Characteristics (Q2 N-Channel) T

Figure 26. Junction-to-Ambient Transient Thermal Response Curve

= 25 °C unless otherwise noted

J

®

MOSFET

Figure 27. FDMC8200S SyncFET body diode reverse recovery characteristic

0 20406080100

-2

-1

0

1

2

3

4

5

6

7

di/dt = 300 A/μs

CURRENT (A)

TIME (ns)

Figure 28. SyncFET body diode reverses leakage versus drain-source voltage

0 5 10 15 20 25 30

0.000001

0.00001

0.0001

0.001

0.01

TJ = 125 oC

TJ = 100 oC

TJ = 25 oC

I

DSS

, REVERSE LEAKAGE CURRENT (A)

VDS, REVERSE VOLTAGE (V)

Typical Characteristics (continued)

SyncFET Schottky body diode Characteristics

FDMC8200S Dual N-Channel PowerTrench

Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 14 shows the reverses recovery characteristic of the FDMC8200S.

Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device.

®

MOSFET

Dimensional Outline and Pad Layout

FDMC8200S Dual N-Channel PowerTrench

®

MOSFET

tm

®

tm

TRADEMARKS

The following includes registered and unregistered trademar ks and service marks, owned by Fair child Semicondu ctor and/or its glo bal subsidiaries, and is no t intended to be an exhaustive list of all such trademarks.

AccuPower™ Auto-SPM™ AX-CAP™* Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ DEUXPEED Dual Cool™ EcoSPARK EfficentMax™ ESBC™

Fairchild Fairchild Semiconductor FACT Quiet Series™ FACT FAST FastvCore™ FETBench™ FlashWriter FPS™

®

® ®

®

*

F-PFS™

®

FRFET Global Power Resource Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MicroPak2™ MillerDrive™ MotionMax™

®

Motion-SPM™ mWSaver™ OptiHiT™ OPTOLOGIC OPTOPLANAR

®

PDP SPM™

Power-SPM™ PowerTrench

SM

PowerXS™ Programmable Active Droop™ QFET QS™ Quiet Series™ RapidConfigure™

Saving our world, 1mW/W/kW at a time™ SignalWise™ SmartMax™ SMART START™ SPM STEALTH™ SuperFET SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS SyncFET™ Sync-Lock™ ®*

®

™

®

The Power Franchise The Right Technology for Your Success™

TinyBoost™ TinyBuck™ TinyCalc™ TinyLogic TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ TriFault Detect™ TRUECURRENT μSerDes™

UHC Ultra FRFET™ UniFET™ VCX™ VisualMax™ XS™

®

*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

®

*

FDMC8200S Dual N-Channel PowerTrench

®

MOSFET

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used here in:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

ANTI-COUNTERFEITING POLICY

Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support Counterfeiting of semiconductor parts is a growing problem in the indust ry. All manufactures of semiconductor products are experiencin g counterfeiting of their parts. Customers who inadvertently purchase counte rfe it parts e xpe rien ce many probl ems such as loss of b rand reputa tio n, subst andard p erf orman ce, fai led

application, and increased cost of production and manufacturing del ays. Fairch ild is taking stro ng measure s to prot ect ourselves and our customers fro m the proliferation of counterfeit parts. Fairchild strongly encou rages customer s to purchase Fairchild parts either direct ly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s qua lity standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is

.

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

committed to combat this global problem and encourage our customer s to do their part in stopping this practice by buying direct or from authorized distrib utors.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative / In Design

Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The data sheet is for reference information only.

Rev. I53

FDMC8200S Rev.C4