Datasheet FDMA3027PZ Datasheet (Fairchild)

Page 1
G2
S1
G1
D2
D1
S2
S1 G1 D2
S2
MicroFET 2x2
D1 G2
PIN 1
D1 D2
Top Bottom
1
2
3
6
5
4
Dual P-Channel PowerTrench® MOSFET
-30 V, -3.3 A, 87 mΩ Features
Max rMax rHBM ESD protection level > 2 KV typical (Note 3)Low profile - 0.8 mm maximum - in the new package
MicroFET 2x2 mm
RoHS Compliant
= 87 mΩ at VGS = -10 V, ID = -3.3 A
DS(on)
= 152 mΩ at VGS = -4.5 V, ID = -2.3 A
DS(on)
General Description
This device is designed specifically as a single package solution for dual switching requirements such as gate driver for larger Mosfets. It features two independent P-Channel MOSFETs with low on-state resistance for minimum conduction losses. The MicroFET 2x2 package offers exceptional thermal performance for its physical size and is well suited to linear mode applications. G-S zener has been added to enhance ESD voltage level.
Applications
Load SwitchDiscrete Gate Driver
FDMA3027PZ Dual P-Channel PowerTrench
June 2012
®
MOSFET
MOSFET Maximum Ratings T
Symbol Parameter Ratings Units
V
DS
V
GS
I
D
P
D
, T
T
J
STG
Thermal Characteristics
R
θJA
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
©2012 Fairchild Semiconductor Corporation FDMA3027PZ Rev.C
Drain to Source Voltage -30 V Gate to Source Voltage ±25 V Drain Current -Continuous (Note 1a) -3.3
-Pulsed -15 Power Dissipation (Note 1a) 1.4 Power Dissipation (Note 1b) 0.7 Operating and Storage Junction Temperature Range -55 to +150 °C
Thermal Resistance for Single Operation, Junction to Ambient (Note 1a) 86 Thermal Resistance for Single Operation, Junction to Ambient (Note 1b) 173 Thermal Resistance for Dual Operation, Junction to Ambient (Note 1c) 69 Thermal Resistance for Dual Operation, Junction to Ambient (Note 1d) 151 Thermal Resistance for Single Operation, Junction to Ambient (Note 1e) 160 Thermal Resistance for Dual Operation, Junction to Ambient (Note 1f) 133
327 FDMA3027PZ MicroFET 2X2 7 ’’ 8 mm 3000 units
= 25 °C unless otherwise noted
A
1
A
W
°C/W
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Page 2
FDMA3027PZ Dual P-Channel PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
ΔBV ΔT
I
DSS
I
GSS
DSS
DSS J
Drain to Source Breakdown Voltage ID = -250 μA, VGS = 0 V -30 V Breakdown Voltage Temperature
Coefficient Zero Gate Voltage Drain Current VDS = -24 V, V Gate to Source Leakage Current VGS = ±25 V, V
I
= -250 μA, referenced to 25 °C -22 mV/°C
D
= 0 V -1 μA
GS
= 0 V ±10 μA
DS
On Characteristics
V
GS(th)
ΔV ΔT
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage VGS = VDS, ID = -250 μA-1-1.9-3V Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
I
= -250 μA, referenced to 25 °C 5 mV/°C
D
V
= -10 V, ID = -3.3 A 69 87
GS
= -4.5 V, ID = -2.3 A 108 152
GS
= -10 V, ID = -3.3 A, TJ = 125 °C 97 122
V
GS
Forward Transconductance VDS = -5 V, ID = -3.3 A 6 S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance Output Capacitance 59 80 pF Reverse Transfer Capacitance 53 80 pF
= -15 V, VGS = 0 V,
V
DS
f = 1 MHz
Gate Resistance 12 Ω
324 435 pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g(TOT)
Q
gs
Q
gd
Turn-On Delay Time Rise Time 310ns Turn-Off Delay Time 17 31 ns
= -15 V, ID = -3.3 A,
V
DD
V
= -10 V, R
GS
GEN
= 6 Ω
Fall Time 11 25 ns Total Gate Charge V Total Gate Charge V Gate to Source Charge 1.0 nC
= 0 V to -10 V
GS
= 0 V to -5 V 4.1 6 nC
GS
= -15 V,
V
DD
I
= -3.3 A
D
Gate to Drain “Miller” Charge 1.9 nC
5.2 11 ns
7.2 10 nC
mΩV
®
MOSFET
Drain-Source Diode Characteristics
V
SD
t
rr
Q
rr
©2012 Fairchild Semiconductor Corporation FDMA3027PZ Rev.C
Source to Drain Diode Forward Voltage V Reverse Recovery Time Reverse Recovery Charge 10 18 nC
= 0 V, IS = -3.3 A (Note 2) -0.94 -1.3 V
GS
= -3.3 A, di/dt = 100 A/μs
I
F
2
20 32 ns
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Page 3
FDMA3027PZ Dual P-Channel PowerTrench
Electrical Characteristics T
Notes:
1. R
is determined with the device mounted on a 1 in2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
θJA
user's board design. (a) R
(b) R (c) R
(d) R (e) R (f) R
= 86 °C/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick PCB. For single operation.
θJA
= 173 °C/W when mounted on a minimum pad of 2 oz copper. For single operation.
θJA
= 69 oC/W when mounted on a 1 in
θJA
= 151 oC/W when mounted on a minimum pad of 2 oz copper. For dual operation.
θJA
= 160 oC/W when mounted on a 30 mm2 pad of 2 oz copper. For single operation.
θJA
= 133 oC/W when mounted on a 30 mm2 pad of 2 oz copper. For dual operation.
θJA
a. 86 °C/W when mounted on a 1 in
c. 69 °C/W when mounted on a 1 in
= 25 °C unless otherwise noted
J
2
pad of 2 oz copper, 1.5 ” x 1.5 ” x 0.062 ” thick PCB. For dual operation.
2
pad of 2 oz copper
2
pad of 2 oz copper
is guaranteed by design while R
θJC
b. 173 °C/W when mounted on a minimum pad of 2 oz copper
d. 151 °C/W when mounted on a minimum pad of 2 oz copper
is determined by the
θJA
®
MOSFET
e. 160 °C/W when mounted on 30 mm2 pad of 2 oz copper
2. Pulse Test : Pulse Width < 300 us, Duty Cycle < 2.0%
3. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
©2012 Fairchild Semiconductor Corporation
3
FDMA3027PZ Rev.C
f. 133 °C/W when mounted on 30 mm2 pad of 2 oz copper
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Page 4
FDMA3027PZ Dual P-Channel PowerTrench
012345
0
3
6
9
12
15
VGS = -5 V
VGS = -3.5 V
PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX
VGS = -4 V
VGS = -4.5 V
VGS = -10 V
-I
D
, DRAIN CURRENT (A)
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
03691215
0
1
2
3
4
5
V
GS
= -4 V
VGS = -3.5 V
PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
-I
D
, DRAIN CURRENT (A)
V
GS
= -5 V
VGS = -4.5 V
V
GS
= -10 V
-75 - 50 -25 0 25 50 75 100 125 150
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
ID = -3.3 A V
GS
= -10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
T
J
, JUNCTION TE M P E R ATURE (
o
C)
246810
0
100
200
300
400
TJ = 125 oC
ID = -3.3 A
TJ = 25 oC
-V
GS
, GATE TO SOURCE VOL TA G E (V)
r
DS(on)
,
DRAIN TO
SOURCE ON-RESISTANCE
(mΩ)
PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX
123456
0
3
6
9
12
15
TJ = 150 oC
V
DS
= -5 V
PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
-I
D
, DRAIN CURRENT (A)
-VGS, GATE TO SOURCE VOLTAGE (V)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
0.001
0.01
0.1
1
10
20
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
V
GS
= 0 V
-I
S
, REVERSE DRAIN CURRENT (A)
-VSD, BODY DIODE FORWARD VOLTAGE (V)
Typical Characteristics T
Figure 1.
On-Region Characteristics Figure 2.
= 25 °C unless otherwise noted
J
Normal i z e d O n - R esistance
vs Drain Current and Gate Voltage
®
MOSFET
Figu r e 3. Norm a l ized On - R esista n c e
vs Junction Temperature
©2012 Fairchild Semiconductor Corporation FDMA3027PZ Rev.C
Figure 5. Transfer Characteristics
Figure 4.
On-Resistance vs Gate to
Source Voltage
Figure 6.
Source to Drain Diode
Forward Voltage vs Source Current
4
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Page 5
FDMA3027PZ Dual P-Channel PowerTrench
02468
0
2
4
6
8
10
ID = -3.3 A
VDD = -10 V
V
DD
= -15 V
-V
GS
, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = -20 V
0.1 1 10 30
10
100
1000
f = 1 MHz V
GS
= 0 V
CAPACITANCE (pF)
-VDS, DRAIN TO SOURCE VOLTAGE (V)
C
rss
C
oss
C
iss
0 4 8 121620242832
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
V
DS
= 0 V
TJ = 25 oC
TJ = 125 oC
-V
GS
,
GATE TO SOURCE VOLTAGE (V)
-I
g
, GATE LEAKAGE CURRENT (A)
0.1 1 10 100
0.01
0.1
1
10
20
10 s
10 ms
DC
1 s
100 ms
1 ms
-I
D
, DRAIN CURRENT (A)
-VDS, DRAIN to SOURCE VOLTAGE (V)
THIS A REA IS LIMITED BY r
DS(on)
SINGLE PULSE T
J
= MAX RATED
R
θJA
= 173
o
C/W
T
A
= 25
o
C
10
-3
10
-2
10
-1
110
100 1000
0.5
1
10
30
P
(PK)
, PEAK TRANSIENT POWER (W)
SINGLE PULSE R
θJA
= 173 oC/W
T
A
= 25 oC
t, PULSE WIDTH (sec)
Typical Characteristics T
Figure 7.
Gate Charge Characteristics Figure 8.
= 25 °C unless otherwise noted
J
Capacitance vs Drain
to Source Voltage
®
MOSFET
Figure 9.
Gate Leakage Current vs Gate to
Source Voltage
Figure 11.
©2012 Fairchild Semiconductor Corporation FDMA3027PZ Rev.C
Figure 10.
Forward Bias Safe
Operating Area
Single Pulse Maximum Power Dissipation
5
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Page 6
FDMA3027PZ Dual P-Channel PowerTrench
10
-3
10
-2
10
-1
110
100 1000
0.02
0.1
1
2
SINGLE PULSE R
θJA
= 173 oC/W
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE,
Z
θJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
P
DM
t
1
t
2
NOTES: DUTY FACTOR: D = t1/t
2
PEAK TJ = PDM x Z
θJA
x R
θJA
+ T
A
Typical Characteristics T
Figure 12. Junction-to-Ambient Transient Thermal Response Curve
= 25 °C unless otherwise noted
J
®
MOSFET
©2012 Fairchild Semiconductor Corporation FDMA3027PZ Rev.C
6
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Page 7
Dimensional Outline and Pad Layout
FDMA3027PZ Dual P-Channel PowerTrench
®
MOSFET
©2012 Fairchild Semiconductor Corporation FDMA3027PZ Rev.C
7
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Page 8
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®
™
tm
tm
The following includes registered and unregistered trademarks a nd service marks, owned by Fairch ild Semiconductor and/ or its global subsidiaries, and is n ot intended to be an exhaustive list of all such trademarks.
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Fairchild Fairchild Semiconductor FACT Quiet Series™ FACT FAST FastvCore™ FETBench™ FlashWriter FPS™
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
FDMA3027PZ Dual P-Channel PowerTrench
®
MOSFET
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used here in:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the bo dy or (b ) support or su stain life, and (c) whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
ANTI-COUNTERFEITING POLICY
Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are exper iencing counterfeiting of their
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PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative / In Design
Preliminary First Production
No Identification Needed Full Production
Obsolete Not In Production
©2012 Fairchild Semiconductor Corporation FDMA3027PZ Rev.C
Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
Datasheet contains preliminary data; supplementa ry data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.
Rev. I61
8
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