Datasheet FDH3632 Datasheet (Fairchild)

FDB3632 / FDP3632 / FDI3632 / FDH3632

N-Channel PowerTrench® MOSFET
100V, 80A, 9mΩ

FDB3632 / FDP3632 / FDI3632 / FDH3632

November 2004

Features

•r

•Q

• Low Miller Charge

•Low Q

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

= 7.5mΩ (Typ.), V

DS(ON)

(tot) = 84nC (Typ.), V

g

Body Diode

RR

= 10V, ID = 80A

GS

= 10V

GS

Applications

• DC/DC converters and Off-Line UPS

• Distributed Power Architectures and VRMs

• Primary Switch for 24V and 48V Systems

• High Voltage Synchronous Rectifier

• Direct Injection / Diesel Injection Systems

• 42V Automotive Load Control

• Electronic Valve Train Systems

S

DRAIN

D

G

G

DRAIN

(FLANGE)

TO-220AB

FDP SERIES

S

G

D

G

S

TO-263AB

FDB SERIES

MOSFET Maximum Ratings T

DRAIN

(FLANGE)

DRAIN

(FLANGE)

TO-262AB

FDI SERIES

= 25°C unless otherwise noted

C

S

D

G

TO-247

FDH SERIES

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Source Voltage 100 V
Gate to Source Voltage ±20 V
Drain Current

I

D

Continuous (T
Continuous (T

< 111oC, VGS = 10V)

C

= 25oC, VGS = 10V, R

amb

= 43oC/W) 12 A

θJA

80 A

Pulsed Figure 4 A

E

AS

P

D

, T

T

J

STG

Single Pulse Avalanche Energy (Note 1) 393 mJ
Power dissipation 310 W

o

Derate above 25

C2.07W/

Operating and Storage Temperature -55 to 175

D

S

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

R

θJA

This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a

All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

©2004 Fairchild Semiconductor Corporation

Thermal Resistance Junction to Case TO-220, TO-263, TO-262,
TO-247

Thermal Resistance Junction to Ambient TO-220, TO-262 (Note 2) 62
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 43
Thermal Resistance Junction to Ambient TO-247 (Note 2) 30

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

certification.

0.48

FDB3632 / FDP3632 / FDI3632 / FDH3632 Rev. C1

o

C/W

o

C/W

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDB3632 FDB3632 TO-263AB 330mm 24mm 800 units
FDP3632 FDP3632 TO-220AB Tube N/A 50 units

FDI3632 FDI3632 TO-262AA Tube N/A 50 units

FDH3632 FDH3632 TO-247 Tube N/A 30 units

FDB3632 / FDP3632 / FDI3632 / FDH3632

Electrical Characteristics T

= 25°C unless otherwise noted

C

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B
I

DSS

I

GSS

VDSS

Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 100 - - V

V

= 80V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC= 150oC - - 250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

I

=80A, VGS=10V - 0.0075 0.009

D

Drain to Source On Resistance

=40A, VGS = 6V, - 0.009 0.015

D

=80A, VGS=10V, TC=175oC - 0.018 0.022

I

D

Dynamic Characteristics

C
C
C
Q
Q
Q
Q
Q

ISS
OSS
RSS

g(TOT)
g(TH)
gs
gs2
gd

Input Capacitance
Output Capacitance - 820 - pF
Reverse Transfer Capacitance - 200 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total Gate Charge at 10V VGS = 0V to 10V
Threshold Gate Charge VGS = 0V to 2V - 11 14 nC
Gate to Source Gate Charge - 30 - nC
Gate Charge Threshold to Plateau - 20 - nC

= 50V

V

DD

I

= 80A

D

I

= 1.0mA

g

Gate to Drain “Miller” Charge - 20 - nC

- 6000 - pF

- 84 110 nC

µA

ΩI

Resistive Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 30 - ns
Rise Time - 39 - ns
Turn-Off Delay Time - 96 - ns
Fall Time - 46 - ns
Turn-Off Time - - 213 ns

(VGS = 10V)

V

DD

V

GS

- - 102 ns

= 50V, ID = 80A
= 10V, RGS = 3.6Ω

Drain-Source Diode Characteristics

I

= 80A - - 1.25 V

V

SD

t

rr

Q

RR

Notes:
1: Starting T
2: Pulse Width = 100s

©2004 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 / FDH3632 Rev. C1

Source to Drain Diode Voltage
Reverse Recovery Time ISD = 75A, dISD/dt= 100A/µs- - 64ns

Reverse Recovered Charge ISD = 75A, dISD/dt= 100A/µs - - 120 nC

= 25°C, L = 0.12mH, IAS = 75A, VDD = 80V.

J

SD

= 40A - - 1.0 V

I

SD

FDB3632 / FDP3632 / FDI3632 / FDH3632

Typical Characteristics T

= 25°C unless otherwise noted

A

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

150

125

CURRENT LIMITED
BY PACKAGE

100

75

V

= 10V

GS

50

, DRAIN CURRENT (A)

D

I

25

0

25 50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

Figure 2. Maximum Continuous Drain Current vs

Case Temperature

, NORMALIZED
Z

, PEAK CURRENT (A)
I

θJC

DM

THERMAL IMPEDANCE

2000

1000

100

50

0.1

0.01

10

-5

10

VGS = 10V

-5

SINGLE PULSE

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

NOTES:
DUTY FACTOR: D = t1/t

PEAK TJ = PDM x Z

-1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

TRANSCONDUCTANCE
MA Y LIMIT CURRENT
IN THIS REGION

-4

10

-3

10

-2

10

t, PULSE WIDTH (s)

-1

10

TC = 25oC

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

I = I

P

DM

2

x R

θJC

0

10

o

C DERATE PEAK

175 - T

25

0

10

t

1

θJC

150

t

2

+ T

C

1

10

C

1

10

Figure 4. Peak Current Capability

©2004 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 / FDH3632 Rev. C1

Typical Characteristics T

= 25°C unless otherwise noted

A

FDB3632 / FDP3632 / FDI3632 / FDH3632

400

100

OPERATION IN THIS

10

, DRAIN CURRENT (A)

1

D

I

0.1

AREA MAY BE

LIMITED BY r

SINGLE PULSE
TJ = MAX RATED

TC = 25oC

110100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

10µs

100µs

1ms

10ms

DC

200

Figure 5. Forward Bias Safe Operating Area

150

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

V

= 15V

DD

120

90

60

, DRAIN CURRENT (A)

D

I

30

0

3.0 3.5 4.0 4.5 5.0 5.5 6.0

TJ = 25oC

TJ = 175oC

TJ = -55oC

VGS, GATE TO SOURCE VOLTAGE (V)

200

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

100

STARTING TJ = 150oC

, AVALANCHE CURRENT (A)

AS

I

10

0.01

0.1 1 10

tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

150

VGS = 10V

120

90

60

, DRAIN CURRENT (A)

D

30

I

0

01234

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 6V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = 5.5V

VGS = 5V

TC = 25oC

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

10

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

9

8

7

DRAIN TO SOURCE ON RESISTANCE (m Ω)

6

0 20406280

ID, DRAIN CURRENT (A)

VGS = 6V

VGS = 10V

Figure 9. Drain to Source On Resistance vs Drain

Current

©2004 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 / FDH3632 Rev. C1

2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID =80A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDB3632 / FDP3632 / FDI3632 / FDH3632

Typical Characteristics T

1.4

1.2

1.0

0.8

0.6

NORMALIZED GATE

THRESHOLD VOLTAGE

0.4

0.2

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

A

VGS = VDS, ID = 250µA

Figure 11. Normalized Gate Threshold Voltage vs

Junction Temperature

10000

C

= CGS + C

1000

ISS

C

≅ C

+ C

OSS

DS

GD

C

= C

RSS

GD

GD

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junctio n Te m pe r ature

10

VDD = 50V

8

6

4

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

100

0.1 1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Source

Voltage

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 20406080100

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 80A
ID = 40A

Figure 14. Gate Charge Waveforms for Constant

Gate Currents

©2004 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 / FDH3632 Rev. C1

Test Circuits and Waveforms

FDB3632 / FDP3632 / FDI3632 / FDH3632

VARY tP TO OBTAIN
REQUIRED PEAK I

V

GS

V

DS

L

I

AS

R

AS

G

+

V

DD

-

BV

DSS

t

P

V

DS

DUT

t

0V

P

I

AS

0.01Ω

0

t

AV

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

I

g(REF)

DS

L

V

GS

+

V

DD

-

DUT

V

DD

V

GS

V

= 2V

GS

Q

0

Q

g(TH)

I

g(REF)

gs2

Q

gs

Q

g(TOT)

V

DS

Q

gd

0

V

DD

V

= 10V

GS

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

t

d(OFF)

90%

t

OFF

t

f

90%

10%

50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2004 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 / FDH3632 Rev. C1

Thermal Resistance vs. Mounting Pad Area

)

d

)

)

d

80

o

)

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and

(oC), and thermal resistance R

A

is never exceeded.

JM

serves as the basis for establishing the rating of the part.

TJMTA–()

-----------------------------=

P

DM

R

θJA

In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
complex and influenced by many factors:

1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.

DM

(oC/W)

θJA

(EQ. 1

, in an

is

DM

60

C/W)
(

θJA

R

40

20

Figure 21. Thermal Resistance vs Mounting

R

= 26.51+ 19.84/(0.262+Area) EQ.2

θJA

R

= 26.51+ 128/(1.69+Area) EQ.3

θJA

0.1

(0.645) (6.45) (64.5

AREA, TOP COPPER AREA in2 (cm2)

110

Pad Area

FDB3632 / FDP3632 / FDI3632 / FDH3632

Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.

R

R

©2004 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 / FDH3632 Rev. C1

θJA

θJA

26.51

26.51

19.84

------------------------------------ -+=

0.262 Area+()

Area in Inches Square

128

--------------------------------- -+=

1.69 Area+()

Area in Centimeters Square

(EQ. 2

(EQ. 3

PSPICE Electrical Model

E

.SUBCKT FDB3632 2 1 3 ; rev May 2002
CA 12 8 1.7e-9
Cb 15 14 2.5e-9
Cin 6 8 6.0e-9

Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 102.5
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1
Lgate 1 9 5.61e-9

Ldrain 2 5 1.0e-9
Lsource 3 7 2.7e-9

RLgate 1 9 56.1
RLdrain 2 5 10
RLsource 3 7 27

Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 3.8e-3
Rgate 9 20 1.1
RSLC1 5 51 RSLCMOD 1.0e-6

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

EVTEMP
+

20

S1A

12

S1B

18
22

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

+

19

6

-

S2A

13814

13

S2B

13

+

+

6

EGS EDS

8

-

-

5

RSLC1

51

+

5

ESLC

51

­50

RDRAIN

16

21

-

8

MSTRO

CIN

15

CB

8

14

+

5
8

-

MMED

8

DBREAK

11

+

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 2.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*350),3))}
.MODEL DbodyMOD D (IS=5.9E-11 N=1.07 RS=2.3e-3 TRS1=3.0e-3 TRS2=1.0e-6

+ CJO=4e-9 M=0.58 TT=4.8e-8 XTI=4.2)
.MODEL DbreakMOD D (RS=0.17 TRS1=3.0e-3 TRS2 =-8.9e-6)
.MODEL DplcapMOD D (CJO=15e-10 IS=1.0e-30 N=10 M=0.6)

.MODEL MstroMOD NMOS (VTO=4.1 KP=200 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=3.4 KP=10.0 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.1)
.MODEL MweakMOD NMOS (VTO=2.75 KP=0.05 IS=1e- 30 N=10 TOX=1 L=1u W=1u RG=1.1e+1 RS=0.1)

.MODEL RbreakMOD RES (TC1=1.0e-3 TC2=-1.7e-6)
.MODEL RdrainMOD RES (TC1=8.5e-3 TC2=2.8e-5)
.MODEL RSLCMOD RES (TC1=2.0e-3 TC2=2.0e-6)
.MODEL RsourceMOD RES (TC1=4e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-4.0e-3 TC2=-1.8e-5)
.MODEL RvtempMOD RE S (TC1=-4.4e-3 TC2=2.2e-6)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=0.4)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.4 VOFF=-0.8)

.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

17
18

-

7

+

RVTEMP
19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURC

3

FDB3632 / FDP3632 / FDI3632 / FDH3632

©2004 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 / FDH3632 Rev. C1

SABER Electrical Model

E

LDRAIN

REV May 2002
template FDB3632 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=5.9e-11,nl=1.07,rs=2.3e-3,trs1=3.0e-3,trs 2=1.0e-6,cjo=4e-9,m=0.58,tt=4.8e-8,xti=4.2)
dp..model dbreakmod = (rs=0.17,trs1=3.0e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=15e-10,isl=10.0e-30,nl=10,m=0.6)
m..model mstrongmod = (type=_n,vto=4.1,kp=200,is=1e-30, tox=1)
m..model mmedmod = (type=_n,vto=3.4,kp=10.0,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.75,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-2)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.8,voff=0.4)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.4,voff=-0.8)
c.ca n12 n8 = 1.7e-9
c.cb n15 n14 = 2.5e-9
c.cin n6 n8 = 6.0e-9

dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod

RGATE

ESG

EVTEMP
+

18
22

20

dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 102.5

spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1

GATE

spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1

LGATE

1

9

RLGATE

spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1

CA

S1A

12

S1B

l.lgate n1 n9 = 5.61e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.7e-9

res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 27

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=1.0e-3,tc2=-1.7e-6
res.rdrain n50 n16 = 3.8e-3, tc1=8.5e-3,tc2=2.8e-5
res.rgate n9 n20 = 1.1
res.rslc1 n5 n51 = 1.0e-6, tc1=2.0e-3,tc2=2.0e-6
res.rslc2 n5 n50 = 1.0e3
res.rsource n8 n7 = 2.5e-3, tc1=4e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-4.0e-3,tc2=-1.8e-5
res.rvtemp n18 n19 = 1, tc1=-4.4e-3,tc2=2.2e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/350))** 3))
}
}

DPLCAP

10

RSLC2

-

6
8

EVTHRES

+

+

19

8

6

-

S2A

13814

13

S2B

13

+

+

6

EGS EDS

8

-

-

15

CIN

CB

-

+

-

5

51

MSTRO

14

5
8

RSLC1

ISCL

50

RDRAIN

16

21

8

MMED

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17
18

­7

RVTEMP
19

-

+

22

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURC

3

FDB3632 / FDP3632 / FDI3632 / FDH3632

©2004 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 / FDH3632 Rev. C1

FDB3632 / FDP3632 / FDI3632 / FDH3632

SPICE Thermal Model

REV May 2002
FDB3632
CTHERM1 TH 6 7.5e-3

CTHERM2 6 5 8.0e-3
CTHERM3 5 4 9.0e-3
CTHERM4 4 3 2.4e-2
CTHERM5 3 2 3.4e-2
CTHERM6 2 TL 6.5e-2

RTHERM1 TH 6 3.1e-4
RTHERM2 6 5 2.5e-3
RTHERM3 5 4 2.2e-2
RTHERM4 4 3 8.1e-2
RTHERM5 3 2 1.35e-1
RTHERM6 2 TL 1.5e-1

SABER Thermal Model

SABER thermal model FDB3632
template thermal _ model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =7.5e-3
ctherm.ctherm2 6 5 =8.0e-3
ctherm.ctherm3 5 4 =9.0e-3
ctherm.ctherm4 4 3 =2.4e-2
ctherm.ctherm5 3 2 =3.4e-2
ctherm.ctherm6 2 tl =6.5e-2

rtherm.rtherm1 th 6 =3.1e-4
rtherm.rtherm2 6 5 =2.5e-3
rtherm.rtherm3 5 4 =2.2e-2
rtherm.rtherm4 4 3 =8.1e-2
rtherm.rtherm5 3 2 =1.35e-1
rtherm.rtherm6 2 tl =1.5e-1
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

RTHERM6

2

CTHERM6

tl

CASE

©2004 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 / FDH3632 Rev. C1

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PRODUCT STA TUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Formative or
In Design

First Production

Full Production

2. A critical component is any component of a life
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Rev. I14