Page 1
June 2008
FDG6322C
Dual N & P Channel Digital FET
General Description Features
These dual N & P-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. This device has been designed
especially for low voltage applications as a replacement for
bipolar digital transistors and small signal MOSFETs. Since
bias resistors are not required, this dual digital FET can
replace several different digital transistors, with different bias
resistor values.
SC70-6
SOT-23
SuperSOT
S2
G2
D1
D2
SC70-6
Mark: .22
pin
1
S1
G1
N-Ch 0.22 A, 25 V, R
R
P-Ch -0.41 A,-25V, R
R
DS(ON)
= 4.0 Ω @ VGS= 4.5 V,
DS(ON)
= 5.0 Ω @ VGS= 2.7 V.
DS(ON)
= 1.1 Ω @ VGS= -4.5V,
DS(ON)
= 1.5 Ω @ VGS= -2.7V.
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (V
GS(th)
< 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
TM
-6
SOT-8
1
2
3
SO-8
SOIC-14
66
Q1
5
Q2
4
Absolute Maximum Ratings T
Symbol Parameter N-Channel P-Channel Units
V
DS
V
GSS
I
D
Drain-Source Voltage 25 -25 V
S
Gate-Source Voltage 8 -8 V
Drain Current - Continuous 0.22 -0.41 A
= 25oC unless other wise noted
A
- Pulsed 0.65 -1.2
P
D
T
J,TSTG
ESD Electrostatic Discharge Rating MIL-STD-883D
Maximum Power Dissipation (Note 1) 0.3 W
Operating and Storage Temperature Range -55 to 150 °C
6 kV
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
R
JA
θ
© 2008 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note1) 415 °C/W
FDG6322C Rev.F1
Page 2
DMOS Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA N-Ch 25 V
VGS = 0 V, ID = -250 µA P-Ch -25
∆BV
DSS
Breakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC N-Ch 25 mV/oC
/∆T
J
ID = -250 µA, Referenced to 25 oC P-Ch -22
I
DSS
I
DSS
I
GSS
Zero Gate Voltage Drain Current V
= 20 V, VGS= 0 V, N-Ch 1 µA
DS
Zero Gate Voltage Drain Current VDS =-20 V, V
Gate - Body Leakage Current VGS = 8 V, V
VGS = -8 V, V
ON CHARACTERISTICS (Note 2)
V
GS(th)
Gate Threshold Voltage VDS = VGS, ID = 250 µA N-Ch 0.65 0.85 1.5 V
VDS = VGS, ID = -250 µA P-Ch -0.65 -0.82 -1.5
∆V
GS(th)
Gate Threshold Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 o C N-Ch -2.1 mV/ oC
/∆T
J
ID= -250 µA, Referenced to 25 o C P-Ch 2.1
R
DS(ON)
Static Drain-Source On-Resistance VGS = 4.5 V, ID = 0.22 A N-Ch 2.6 4
VGS = 2.7 V, ID = 0.19 A 3.7 5
VGS = -4.5 V, ID = -0.41 A P-Ch 0.85 1.1
VGS = -2.7 V, ID = -0.25 A 1.15 1.5
I
D(ON)
On-State Drain Current VGS = 4.5 V, VDS = 5 V N-Ch 0.22 A
VGS = -4.5 V, VDS = -5 V P-Ch -0.41
g
FS
Forward Transconductance VDS = 5 V, ID= 0.22 A N-Ch 0.2 S
VDS = -5 V, ID = -0.5 A P-Ch 0.9
DYNAMIC CHARACTERISTICS
C
iss
C
oss
Input Capacitance N-Channel N-Ch 9.5 pF
V
= 10 V, V
DS
Output Capacitance f = 1.0 MHz N-Ch 6
P-Channel P-Ch 34
C
rss
Reverse Transfer Capacitance V
= -10 V, VGS = 0 V, N-Ch 1.3
DS
f = 1.0 MHz P-Ch 10
Min Typ Max Units
Type
TJ = 55°C 10
= 0 V, P-Ch -1 µA
GS
TJ = 55°C -10
= 0 V N-Ch 100 nA
DS
= 0 V P-Ch -100 nA
DS
TJ =125°C 5.3 7
TJ =125°C 1.2 1.9
= 0 V, P-Ch 62
GS
Ω
FDG6322C Rev.F1
Page 3
Electrical Characteristics (continued)
SWITCHING CHARACTERISTICS (Note 2)
Symbol Parameter Conditions
t
D(on)
Turn - On Delay Time N-Channel N-Ch 5 10 nS
Type
VDD = 5 V, ID = 0.5 A, P-Ch 7 15
t
r
Turn - On Rise Time
VGS = 4.5 V, R
= 50 Ω
GEN
N-Ch 4.5 10 nS
P-Ch 8 16
t
D(off)
Turn - Off Delay Time P-Channel N-Ch 4 8 nS
VDD = -5 V, ID = -0.5 A, P-Ch 55 80
t
f
Turn - Off Fall Time
VGS = -4.5 V, R
GEN
= 50 Ω
N-Ch 3.2 7 nS
P-Ch 35 60
Q
g
Total Gate Charge N-Channel N-Ch 0.29 0.4 nC
VDS= 5 V, ID = 0.22 A, P-Ch 1.1 1.5
Q
gs
Gate-Source Charge VGS = 4.5 V N-Ch 0.12 nC
P- Channel P-Ch 0.31
Q
gd
Gate-Drain Charge VDS = -5 V, ID = -0.41 A, N-Ch 0.03 nC
VGS = -4.5 V P-Ch 0.29
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain-Source Diode Forward Current N-Ch 0.25 A
P-Ch -0.25
V
SD
Notes:
1. R
by design while R
2. Pulse Test: Pulse Width <
Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.5 A
VGS = 0 V, IS = -0.5 A
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
is determined by the user's board design. R
CA
θ
300µs, Duty Cycle < 2.0%.
= 415OC/W on minimum mounting pad on FR-4 board in still air.
JA
θ
(Note 2) N-Ch 0.8 1.2 V
(Note 2) P-Ch -0.85 -1.2
Min Typ Max Units
is guaranteed
JC
θ
FDG6322C Rev.F1
Page 4
Typical Electrical Characteristics: N-Channel
0.5
0.4
0.3
0.2
0.1
D
I , DRAIN-SOURCE CURRENT (A)
V =4.5V
GS
3.5V
3.0V
2.7V
2.5V
2.0V
0
0 1 2 3 4 5
V , DRAIN-SOURCE VOLTAGE (V)
DS
Figure 1. On-Region Characteristics.
1.8
I = 0.22A
D
1.6
V = 4.5V
GS
1.4
1.2
1
DS(ON)
R , NORMALIZED
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
5
4.5
4
V = 2.5V
GS
2.7V
3.0V
3.5
3
DS(ON)
R , NORMALIZED
2.5
DRAIN-SOURCE ON-RESISTANCE
2
0 0.1 0.2 0.3 0.4
I , DRAIN CURRENT (A)
D
3.5V
4.0V
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
20
16
12
8
T =125°C
4
DS(ON)
R , ON-RESISTANCE(OHM)
0
1 2 3 4 5
V ,GATE TO SOURCE VOLTAGE (V)
GS
A
25°C
4.5V
I = 0.10A
D
5.0V
Figure 3. On-Resistance Variation
with Temperature.
0.2
V = 5V
DS
0.15
0.1
0.05
D
I , DRAIN CURRENT (A)
0
0.5 1 1.5 2 2.5 3
V , GATE TO SOURCE VOLTAGE (V)
GS
Figure 5. Transfer Characteristics.
T = -55°C
J
25°C
125°C
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0.4
V = 0V
GS
0.1
T = 125°C
0.01
0.001
S
I , REVERSE DRAIN CURRENT (A)
0.0001
0 0.2 0.4 0.6 0.8 1 1.2
V , BODY DIODE FORWARD VOLTAGE (V)
SD
J
25°C
-55°C
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDG6322C.Rev F1
Page 5
Typical Electrical Characteristics: N-Channel (continued)
6
I = 0.22A
D
5
4
3
2
1
GS
V , GATE-SOURCE VOLTAGE (V)
0
0 0.1 0.2 0.3 0.4 0.5 0.6
V = 5V
DS
Q , GATE CHARGE (nC)
g
10V
Figure 7. Gate Charge Characteristics.
1
10ms
0.3
RDS(ON) LIMIT
0.1
V = 4.5V
GS
SINGLE PULSE
D
0.03
I , DRAIN CURRENT (A)
0.01
JA
R = 415 °C/W
θ
T = 25°C
A
0.4 0.8 2 5 10 25 40
V , DRAIN-SOURCE VOLTAGE (V)
DS
100ms
1s
10s
DC
30
15
C
8
5
CAPACITANCE (pF)
f = 1 MHz
3
V = 0 V
GS
2
0.1 0.3 1 3 10 25
V , DRAIN TO SOURCE VOLTAGE (V)
DS
iss
C
oss
C
rss
Figure 8. Capacitance Characteristics.
50
40
30
20
POWER (W)
10
0
0.0001 0.001 0.01 0.1 1 10 200
SINGLE PULSE TIME (SEC)
SINGLE PULSE
R =415°C/W
JA
θ
T = 25°C
A
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
FDG6322C Rev.F1
Page 6
Typical Electrical Characteristics: P-Channel
1.2
V =-4.5V
0.9
0.6
0.3
D
-I , DRAIN-SOURCE CURRENT (A)
0
0 1 2 3 4
-3.0V
GS
-2.7V
-2.5V
-V , DRAIN-SOURCE VOLTAGE (V)
DS
-2.0V
Figure 11. On-Region Characteristics.
1.6
I = -0.41A
D
V = -4.5V
1.4
GS
1.2
1
DS(ON)
0.8
R , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
0.6
-50 -25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C)
J
-1.5V
2.5
V = -2.0V
2
GS
1.5
DS(ON)
1
R , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
0.5
0 0.2 0.4 0.6 0.8 1 1.2
-2.5V
-2.7V
-3.0V
-I , DRAIN CURRENT (A)
D
-3.5V
-4.5V
Figure 12. On-Resistance Variation with
Drain Current and Gate Voltage.
5
4
3
2
1
DS(ON)
R ,ON-RESISTANCE(OHM)
0
1 2 3 4 5
-V , GATE TO SOURCE VOLTAGE (V)
GS
I =-0.2A
D
T =125 °C
J
25°C
Figure 13. On-Resistance Variation
with Temperature.
1
V = -5V
DS
0.8
0.6
0.4
D
-I , DRAIN CURRENT (A)
0.2
0
0.5 1 1.5 2 2.5 3
-V , GATE TO SOURCE VOLTAGE (V)
GS
T = -55°C
J
25°C
125°C
Figure 15. Transfer Characteristics.
Figure 14. On-Resistance Variation with
Gate-to-Source Voltage.
1
V = 0V
GS
T = 125°C
0.1
J
25°C
0.01
0.001
S
-I , REVERSE DRAIN CURRENT (A)
0.0001
0.2 0.4 0.6 0.8 1 1.2
-V , BODY DIODE FORWARD VOLTAGE (V)
SD
-55°C
Figure 16. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDG6322C Rev.F1
Page 7
1Typical Electrical Characteristics: P-Channel (continued)
5
I = -0.41A
D
4
3
2
1
GS
-V , GATE-SOURCE VOLTAGE (V)
0
0 0.4 0.8 1.2 1.6
Q , GATE CHARGE (nC)
g
V = -5V
DS
-10V
-15V
Figure 17. Gate Charge Characteristics.
3
1
DC
100ms
1s
10s
0.5
RDS(ON) LIMIT
0.1
V = -4.5V
0.05
D
-I , DRAIN CURRENT (A)
0.01
GS
SINGLE PULSE
R = 415°C
JA
θ
A
T = 25°C
A
0.1 0.2 0.5 1 2 5 10 25 40
- V , DRAIN-SOURCE VOLTAGE (V)
DS
10ms
1ms
200
80
30
10
CAPACITANCE (pF)
f = 1 MHz
V = 0 V
5
GS
3
0.1 0.3 1 2 5 10 25
-V , DRAIN TO SOURCE VOLTAGE (V)
DS
C
iss
C
oss
C
rss
Figure 18. Capacitance Characteristics.
50
40
30
20
POWER (W)
10
0
0.0001 0.001 0.01 0.1 1 10 200
SINGLE PULSE TIME (SEC)
SINGLE PULSE
R =415°C/W
JA
θ
T = 25°C
A
Figure 19. Maximum Safe Operating Area.
Figure 20. Single Pulse Maximum Power
Dissipation.
FDG6322C Rev.F1
Page 8
Typical Thermal Characteristics: N & P-Channel (continued)
1
D = 0.5
0.5
0.2
0.2
0.1
0.1
0.05
0.02
0.01
r(t), NORMALIZED EFFECTIVE
0.005
TRANSIENT THERMAL RESISTANCE
0.002
0.05
0.02
0.01
Single Pulse
0.0001 0.001 0.01 0.1 1 10 100 200
Figure 21. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in note 1.
Transient thermalresponse will change depending on the circuit board design.
t , TIME (sec)
1
R (t) = r(t) * R
JA
θ
R =415
JA
θ
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t / t
°C/W
JA
θ
1 2
JA
θ
FDG6322C Rev.F1
Page 9
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative / In Design
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
This datasheet contains preliminary data; supplementary data will be published
Preliminary First Production
No Identification Needed Full Production
Obsolete Not In Production
at a later date. Fairchild Semiconductor reserves the right to make changes at
any time without notice to improve design.
This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve the design.
This datasheet contains specifications on a product that is discontinued by
Fairchild Semiconductor. The datasheet is for reference information only.
Rev. I34
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
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