Datasheet fdg6301n_f085 Datasheet

FDG6301N_F085
Dual N-Channel, Digital FET

General Description Features

These dual N-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. This device has been
designed especially for low voltage applications as a
replacement for bipolar digital transistors and small

signal MOSFETs.

March 2009

25 V, 0.22 A continuous, 0.65 A peak.
R
R

Very low level gate drive requirements allowing direct
operation in 3 V circuits (V

Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).

Compact industry standard SC70-6 surface mount
package.

Qualified to AEC Q101

RoHS Compliant

= 4 Ω @ V

DS(ON)

= 5 Ω @ V

DS(ON)

GS(th)

= 4.5 V,

GS

= 2.7 V.

GS

< 1.5 V).

FDG6301N_F085 Dual N-Channel, Digital FET

SC70-6

SOT-23

SuperSOTTM-6

SuperSOTTM-8

SO-8

SOT-223

S2

1 or 4

2 or 5

*

6 or 3

5 or 2

D1

G2

.01

D2

SC70-6

*The pinouts are symmetrical; pin 1 and 4 are interchangeable.

Units inside the carrier can be of either orientation and will not affect the functionality of the device.

Absolute Maximum Ratings T

Symbol Parameter FDG6301N_F085 Units

V

DSS

V

GSS

I

D

P

D

TJ,T

ESD Electrostatic Discharge Rating MIL-STD-883D

THERMAL CHARACTERISTICS

R

θJA

Drain-Source Voltage 25 V

Gate-Source Voltage 8 V

Drain/Output Current - Continuous 0.22 A

Maximum Power Dissipation (Note 1) 0.3 W

Operating and Storage Temperature Range -55 to 150 °C

STG

Human Body Model(100 pF / 1500 Ω)

Thermal Resistance, Junction-to-Ambient 415 °C/W

G1

S1

= 25°C unless otherwise noted

A

- Pulsed 0.65

3 or 6

6.0 kV

4 or 1

*

©2009 Fairchild Semiconductor Corporation

G6301N_F085 Rev. A

FD

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Electrical Characteristics (T

= 25 OC unless otherwise noted )

A

Symbol Parameter Conditions Min Typ Max Units

OFF CHARACTERISTICS

BV

∆BV

I

DSS

DSS

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 25 V

Breakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 o C 25 mV / oC

/∆T

J

Zero Gate Voltage Drain Current VDS = 20 V, V

= 0 V 1 µA

GS

TJ = 55°C 10 µA

I

GSS

Gate - Body Leakage Current VGS = 8 V, V

= 0 V 100 nA

DS

ON CHARACTERISTICS (Note 2)

V

∆V

R

GS(th)

GS(th)

DS(ON)

Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.65 0.85 1.5 V

Gate Threshold Voltage Temp.Coefficient ID = 250 µA, Referenced to 25 o C -2.1 mV / oC

/∆T

J

Static Drain-Source On-Resistance VGS = 4.5 V, ID = 0.22 A 2.6 4

Ω

TJ =125°C 5.3 7

VGS = 2.7 V, ID = 0.19 A 3.7 5

I

g

D(ON)

FS

On-State Drain Current VGS = 4.5 V, VDS = 5 V 0.22 A

Forward Transconductance VDS = 5 V, ID= 0.22 A 0.2 S

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance VDS = 10 V, VGS = 0 V,

Output Capacitance 6 pF

f = 1.0 MHz

9.5 pF

Reverse Transfer Capacitance 1.3 pF

SWITCHING CHARACTERISTICS (Note 2)

t

t

t

t

Q

Q

Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time VDD = 5 V, ID = 0.5 A,

Turn - On Rise Time 4.5 10 ns

VGS = 4.5 V, R

GEN

= 50 Ω

5 10 ns

Turn - Off Delay Time 4 8 ns

Turn - Off Fall Time 3.2 7 ns

Total Gate Charge VDS = 5 V, ID = 0.22 A,

Gate-Source Charge 0.12 nC

VGS = 4.5 V

0.29 0.4 nC

Gate-Drain Charge 0.03 nC

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

V

SD

Notes:

1. R

JA

θ

by design while R

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

Maximum Continuous Source Current 0.25 A

Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.25 A (Note 2) 0.8 1.2 V

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

is determined by the user's board design. R

CA

θ

= 415OC/W on minimum pad mounting on FR-4 board in still air.

JA

θ

is guaranteed

JC

θ

FDG6301N_F085 Dual N-Channel, Digital FET

FDG6301N_F085 Rev. A

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Typical Electrical Characteristics

FDG6301N_F085 Dual N-Channel, Digital FET

0.5

0.4

0.3

0.2

0.1

D

I , DRAIN-SOURCE CURRENT (A)

V =4.5V

GS

3.5V

3.0V

2.7V

2.5V

2.0V

0

0 1 2 3 4 5

V , DRAIN-SOURCE VOLTAGE (V)

DS

Figure 1. On-Region Characteristics.

1.8

I = 0.22A

D

1.6

V = 4.5V

GS

1.4

1.2

1

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

-50 -25 0 25 50 75 100 125 150

T , JUNCTION TEMPERATURE (°C)

J

5

4.5

4

V = 2.5V

GS

2.7V

3.0V

3.5

3.5V

3

DS(ON)

R , NORMALIZED

2.5

DRAIN-SOURCE ON-RESISTANCE

2

0 0.1 0.2 0.3 0.4

I , DRAIN CURRENT (A)

D

4.0V

Figure 2. On-Resistance Variation with

Drain Current and Gate Voltage.

20

16

12

8

T =125°C

4

DS(ON)

R , ON-RESISTANCE(OHM)

0

1 2 3 4 5

V ,GATE TO SOURCE VOLTAGE (V)

GS

A

25°C

4.5V

5.0V

I = 0.10A

D

Figure 3. On-Resistance Variation

with Temperature.

0.2

V = 5V

DS

0.15

0.1

0.05

D

I , DRAIN CURRENT (A)

0

0.5 1 1.5 2 2.5 3

FDG6301N_F085 Rev. A

V , GATE TO SOURCE VOLTAGE (V)

GS

Figure 5. Transfer Characteristics.

T = -55°C

J

25°C

125°C

Figure 4. On-Resistance Variation with

Gate-to-Source Voltage.

0.4

V = 0V

GS

0.1

T = 125°C

0.01

0.001

S

I , REVERSE DRAIN CURRENT (A)

0.0001
0 0.2 0.4 0.6 0.8 1 1.2

V , BODY DIODE FORWARD VOLTAGE (V)

SD

J

25°C

-55°C

Figure 6. Body Diode Forward Voltage

Variation with Source Current
and Temperature.

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Typical Electrical Characteristics ( continued)

FDG6301N_F085 Dual N-Channel, Digital FET

6

I = 0.22A

D

5

4

3

2

1

GS

V , GATE-SOURCE VOLTAGE (V)

0

0 0.1 0.2 0.3 0.4 0.5 0.6

V = 5V

DS

Q , GATE CHARGE (nC)

g

10V

Figure 7. Gate Charge Characteristics.

1

0.3

RDS(ON) LIMIT

0.1

V = 4.5V

GS

SINGLE PULSE

D

0.03

I , DRAIN CURRENT (A)

0.01

JA

R = 415 °C/W

θ

T = 25°C

A

0.4 0.8 2 5 10 25 40

V , DRAIN-SOURCE VOLTAGE (V)

DS

100ms

1s

10s

DC

10ms

30

15

C

8

5

CAPACITANCE (pF)

f = 1 MHz

3

V = 0 V

GS

2

0.1 0.3 1 3 10 25

V , DRAIN TO SOURCE VOLTAGE (V)

DS

iss

C

oss

C

rss

Figure 8. Capacitance Characteristics.

50

40

30

20

POWER (W)

10

0

0.0001 0.001 0.01 0.1 1 10 200

SINGLE PULSE TIME (SEC)

SINGLE PULSE

R =415°C/W

JA

θ

T = 25°C

A

Figure 9. Maximum Safe Operating Area.

1

D = 0.5

0.5

0.2

0.2

0.1

0.1

0.05

0.02

0.01

r(t), NORMALIZED EFFECTIVE

0.005

TRANSIENT THERMAL RESISTANCE

0.002

FDG6301N_F085 Rev. A

0.05

0.02

0.01

Single Pulse

0.0001 0.001 0.01 0.1 1 10 100 200

Figure 11. Transient Thermal Response Curve.

Thermal characterization performed using the conditions described in note 1.

Transient thermal response will change depending on the circuit board design.

t , TIME (sec)

1

Figure 10. Single Pulse Maximum Power

Dissipation.

R (t) = r(t) * R

JA

θ

R =415 °C/W

JA

θ

P(pk)

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t / t

JA

θ

JA

θ

1 2

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FDG6301N_F085 Dual N-Channel, Digital FET

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Advance Information Formative / In Design

Preliminary First Production

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Obsolete Not In Production

Datasheet contains the design specifications for product development. Specifications
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Rev. I39

FDG6301N_F085 Rev. A

5

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