Datasheet FDD8882, FDU8882 Datasheet (Fairchild)

2

April 2008

FDD8882 / FDU8882 N-Channel PowerTrench® MOSFET

FDD8882 / FDU8882
N-Channel PowerTrench

®

30V, 55A, 11.5mΩ

Features

! r
! r
! High performance trench technology for extremely low

! Low gate charge
! High power and current handling capability

 RoHS Complicant

Application

! DC/DC converters

DS(ON)
DS(ON)

r

DS(ON)

= 11.5mΩ, V
= 15mΩ, V

= 10V, ID = 35A

GS

= 4.5V, ID = 35A

GS

MOSFET

General Description

This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
r

and fast switching speed.

DS(ON)

tm

G

D

S

D-PAK

TO-252

(TO-252)

©2008 Fairchild Semiconductor Corporation

FDD8882/FDU8882 Rev. C

G DS

1

I-PAK

(TO-251AA)

D

G

S

www.fairchildsemi.com

FDD8882 / FDU8882 N-Channel PowerTrench® MOSFET

Absolute Maximum Ratings T

= 25°C unless otherwise noted

C

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Source Voltage 30 V
Gate to Source Voltage ±20 V
Drain Current
Continuous (T

I

D

Continuous (T
Continuous (T

= 25oC, VGS = 10V) (Note 1)

C

= 25oC, VGS = 4.5V) (Note 1) 50 A

C

= 25oC, VGS = 10V, with R

amb

= 52oC/W) 12.6 A

θJA

55 A

Pulsed Figure 4 A

E

AS

P

D

T

, T

J

STG

Single Pulse Avalanche Energy (Note 2) 41 mJ
Power dissipation 55 W
Derate above 25

o

C0.37W/

Operating and Storage Te mperature -55 to 175

Thermal Characteristics

R

θJC

R

θJA

R

θJA

Thermal Resistance Junction to Case TO-252, TO-251 2.73
Thermal Resistance Junction to Ambient TO-252, TO-251 100
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 52

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDD8882 FDD8882 TO-252AA 13” 12mm 2500 units
FDU8882 FDU8882 TO-251AA N/A (Tube) N/A 75 units
F
F

o

C/W

o

C/W

o

C/W

o

C

o

C

Electrical Characteristics T

= 25°C unless otherwise noted

C

Symbol Parameter Tes t Cond itions Min Typ Max Units

Off Characteristics

B
I

DSS

I

GSS

VDSS

Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V

V

= 24V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC - - 250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1.2 - 2.5 V

I

= 35A, VGS = 10V - 0.0094 0.0115

D

= 35A, VGS = 4.5V - 0.0130 0.0150

I

Drain to Source On Resistance

D

I

= 35A, VGS = 10V,

D

= 175oC

T

J

- 0.0150 0.0190

µA

Ω

FDD8882/FDU8882 Rev. C

2

www.fairchildsemi.com

Dynamic Characteristics

C
C
C
R
Q
Q
Q
Q
Q
Q

ISS
OSS
RSS
G

g(TOT)
g(5)
g(TH)
gs
gs2
gd

Input Capacitance
Output Capacitance - 240 - pF
Reverse Transfer Capacitance - 140 - pF
Gate Resistance VGS = 0.5V, f = 1MHz - 2.4 - Ω
Total Gate Charge at 10V VGS = 0V to 10V
Total Gate Charge at 5V VGS = 0V to 5V - 11.7 17.6 nC
Threshold Gate Charge VGS = 0V to 1V - 1.2 1.8 nC
Gate to Source Gate Charge - 3.7 - nC
Gate Charge Threshold to Plateau - 2.5 - nC
Gate to Drain “Miller” Charge - 4.6 - nC

= 15V, VGS = 0V,

V

DS

f = 1MHz

V

DD

= 35A

I

D

= 1.0mA

I

g

FDD8882 / FDU8882 N-Channel PowerTrench® MOSFET

- 1260 - pF

-2233nC

= 15V

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 8 - ns
Rise Time - 82 - ns
Turn-Off Delay Time - 40 - ns
Fall Time - 25 - n s
Turn-Off Time - - 98 ns

(VGS = 10V)

Drain-Source Diode Characteristics

V

SD

t

rr

Q

RR

Notes:
1: Package current limitation is 35A.
2: Starting T
3

Source to Drain Diode Voltage
Reverse Recovery Ti me ISD = 35A, dISD/dt = 100A/µs- -32ns

Reverse Recovered Charge ISD = 35A, dISD/dt = 100A/µs- -21nC

= 25°C, L = 0.1mH, IAS = 28A, VDD = 27V, VGS = 10V.

J

- - 135 ns

= 15V, ID = 35A

V

DD

= 10V, RGS = 13Ω

V

GS

I

= 35A - - 1.25 V

SD

I

= 15A - - 1.0 V

SD

FDD8882/FDU8882 Rev. C

3

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FDD8882 / FDU8882 N-Channel PowerTrench® MOSFET

Typical Characteristics T

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 175

TC, CASE TEMPERATURE (oC)

= 25°C unless otherwise noted

C

150

125

Figure 1. Normali ze d Po we r Dis sip ation vs Case

Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

60

CURRENT LIMITED
BY PACKAGE

40

20

, DRAIN CURRENT (A)

D

I

VGS = 10V

0

25 50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

Figure 2. Maximum Contin uous Drain Current vs

Case Temperature

P

DM

t

1

t

x R

2

+ T

θJC

C

0

1

10

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-2

10

-1

10

θJC

1/t2

10

600

100

, PEAK CURRENT (A)

DM

I

30

VGS = 4.5V

-5

10

FDD8882/FDU8882 Rev. C

Figure 3. Normalized Maximum Transient Thermal Impedance

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

-4

10

-3

10

t, PULSE WIDTH (s)

-2

10

-1

10

TC = 25oC

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

I = I

Figure 4. Peak Current Capability

4

o

C DERATE PEAK

175 - T

25

150

0

10

www.fairchildsemi.com

C

1

10

FDD8882 / FDU8882 N-Channel PowerTrench® MOSFET

Typical Characteristics T

1000

100

10

OPERATION IN THIS

AREA MAY BE

LIMITED BY r

, DRAIN CURRENT (A)

D

I

1

SINGLE PULSE
TJ = MAX RATED

T

= 25oC

C

0.1
110

DS(ON)

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

= 25°C unless otherwise noted

C

Figure 5. Forward Bias Safe Operating Area

80

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 15V

V

DD

60

10µs

100µs

1ms

10ms

DC

500

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

100

10

, AVALANCHE CURRENT (A)

AS

I

1

60

STARTING TJ = 150oC

0.001 0.01 0.1 1 10 100
tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Applica ti on Note s AN75 14 and AN75 15

Figure 6. Unclamped Inductive Switching

Capability

80

VGS = 10V

60

VGS = 4.5V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = 3.5V

40

, DRAIN CURRENT (A)

D

I

20

0

1.5 2.0 2.5 3.0 3.5 4.0 4.5

TJ = 25oC

TJ = 175oC

VGS, GATE TO SOURCE VOLTAGE (V)

TJ = -55oC

40

, DRAIN CURRENT (A)

D

I

20

0

0 0.5 1.0 1.5 2.0 2.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

20

ID = 35A

16

, DRAIN TO SOURCE

12

ON RESISTANCE (mΩ)

DS(ON)

r

ID = 1A

8

246810

, GATE TO SOURCE VOLTAGE (V)

V

GS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.8

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.6

1.4

1.2

ON RESISTANCE

1.0

0.8

NORMALIZED DRAIN TO SOURCE

0.6

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

VGS = 3V

TC = 25oC

VGS = 10V, ID = 35A

Figure 9. Drain to Source On Resis tanc e vs Ga te

Voltage and Drain Current

FDD8882/FDU8882 Rev. C

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

5

www.fairchildsemi.com

FDD8882 / FDU8882 N-Channel PowerTrench® MOSFET

Typical Characteristics T

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

C

VGS = VDS, ID = 250µA

Figure 11. Normalized Gate Thresho ld Voltage vs

Junction Temperature

3000

C

= CGS + C

1000

C

= C

RSS

C, CAPACITANCE (pF)

100

0.1 1 10

GD

V

= 0V, f = 1MHz

GS

VDS, DRAIN TO SOURCE VOLTAGE (V)

ISS

C

≅ C

OSS

GD

+ C

DS

GD

30

1.10

ID = 250µA

1.05

1.00

BREAKDOWN VOLTAGE

0.95

NORMALIZED DRAIN TO SOURCE

0.90

-80 -40 0 40 80 120 160 200
T

, JUNCTION TEMPERATURE (oC)

J

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 15V

8

6

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 5 10 15 20 25

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 35A

= 5A

I

D

Figure 13. Capacitance vs Drain to Source

Voltage

FDD8882/FDU8882 Rev. C

Figure 14. Gate Charge Waveforms for Constant

Gate Current

6

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Test Circuits and Waveforms

V

DS

L

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

R

AS

G

+

V

DD

-

I

AS

DUT

t

0V

P

I

AS

0.01Ω

0

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

DS

V

DD

L

V

I

g(REF)

GS

DUT

+

V

DD

-

V

GS

0

I

g(REF)

= 1V

Q

gs2

Q

g(TH)

Q

gs

Q

0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

BV

DSS

t

P

t

AV

Q

g(TOT)

V

DS

Q

g(5)

V

GS

VGS = 5V

gd

FDD8882 / FDU8882 N-Channel PowerTrench® MOSFET

V

DS

V

DD

V

= 10V

GS

V

GS

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

FDD8882/FDU8882 Rev. C

V

DS

R

L

V

GS

R

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

7

t

d(ON)

90%

t

ON

50%

10%

t

r

PULSE WIDTH

t

OFF

t

d(OFF)

t

f

90%

10%

90%

50%

www.fairchildsemi.com

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and

(oC), and thermal resistance R

A

is never exceeded.

JM

DM

θJA

, in an

(oC/W)

serves as the basis for establishing the rating of the part.

P

DM

TJMTA–()

------------------- ----------=

R

θJA

(EQ. 1)

125

100

C/W)

o

(

75

θJA

R

50

R

= 33.32+ 23.84/(0.268+Area) EQ.2

θJA

R

= 33.32+ 154/(1.73+Area) EQ.3

θJA

FDD8882 / FDU8882 N-Channel PowerTrench® MOSFET

In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
complex and influenced by many factors:

DM

is

1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of t he
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.

25

0.01 0.1 1 10
(0.645) (6.45) (64.5)(0.0645)

AREA, TOP COPPER AREA in2 (cm2)

Figure 21. Thermal Resistance vs Mounting

Pad Area

Thermal resistances corresponding to other copper area s
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.

R

R

θJA

θJA

33.32

33.32

23.84

-------------------------------------+=

0.268 Area+()

Area in Inches Squared

154

----------------------------------+=

1.73 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

FDD8882/FDU8882 Rev. C

8

www.fairchildsemi.com

PSPICE Electrical Model

.SUBCKT FDD8882 2 1 3 ; rev October 2004
Ca 12 8 9e-10
Cb 15 14 9e-10
Cin 6 8 1.55e-9

Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 34.1
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1
Lgate 1 9 8.6e-9

Ldrain 2 5 1.0e-9
Lsource 3 7 2.67 e -9

RLgate 1 9 86
RLdrain 2 5 10
RLsource 3 7 26.7

Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2.5e-3
Rgate 9 20 2.43
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 6.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

18
22

20

S1A

12

13

8

S1B

EGS EDS

FDD8882 / FDU8882 N-Channel PowerTrench® MOSFET

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

6

-

S2A

14
13

S2B

13

+

+

6
8

-

-

5

RSLC1

51

+

5

ESLC

51

­50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5
8

-

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

+

17
18

-

Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5, 51)/(1e-6*600),10))}
.MODEL DbodyMOD D (IS=2E-12 IKF=10 N=1.01 RS=5.7e-3 TRS1=8e-4 TRS2=2e-7

+ CJO=4.6e-10 M=0.58 TT=1e-11 XTI=2.7)
.MODEL DbreakMOD D (RS=1 TRS1= 1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=5 .0e-10 IS=1e-30 N=10 M= 0.45)

.MODEL MmedMOD NMOS (VTO=2.11 KP=14 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.43)
.MODEL MstroMOD NMOS (VTO=2.65 KP=240 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.82 KP=0.09 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=24.3 RS=0.1)

.MODEL RbreakMOD RES (TC1 =8.0e-4 TC2=-8e-7)
.MODEL RdrainMOD RES (TC1=-6e-3 TC2=6e-6)
.MODEL RSLCMOD RES (TC1=8e -5 TC2=2e-6)
.MODEL RsourceMOD RES (TC1=7.5e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-1.2e-3 TC2=-8.3e-6)
.MODEL RvtempMOD RES (TC1=- 2.5e-3 TC2=3.3e-7)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-1.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-2)
.ENDS

Note: For further discussio n of the PSP ICE mode l, consul t A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Confere nce Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

FDD8882/FDU8882 Rev. C

9

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SABER Electrical Model

rev October 2004
template FDD8882 n2,n 1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.0e-12,ikf=10,nl=1.01,rs=5.7e-3,trs1=8e-4,trs2=2e-7,cjo=4.6e-10,m=0.58,tt=1e-11,xti=2.7)
dp..model dbreakmod = (rs=1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=5.0e-10,isl=10e-30,nl=10,m=0.45)
m..model mmedmod = (type=_n,vto=2.11, kp=14,is=1e-30, to x=1)
m..model mstrong mod = (type=_n,vto=2.65,kp=240,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.82,kp=0.09,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-1.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-2)
c.ca n12 n8 = 9e-10
c.cb n15 n14 = 9e-10
c.cin n6 n8 = 1.1e-9

dp.dbody n7 n5 = model= dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 34.1
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n 21 n19 n8 = 1

GATE

1

LGATE

RLGATE

RGATE

9

EVTEMP
+

20

spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1

CA

S1A

12

S1B

l.lgate n1 n9 = 8.6e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.67e-9

res.rlgate n1 n9 = 86
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 26.7

m.mmed n16 n6 n8 n8 = model=mmedm od, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=8.0e-4,tc2=-8e-7
res.rdrain n50 n16 = 2.5e-3, tc1=-6e-3,tc2=6e-6
res.rgate n9 n20 = 2.4 3
res.rslc1 n5 n51 = 1e-6, tc1=8e-5,tc2=2e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e-3, tc1=7.5e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-1.2e-3,tc2= -8.3e-6
res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=3.3e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

DPLCAP

10

RSLC2

­6

ESG

8

+

6

-

18
22

S2A

14

13

13

8

S2B

13

+

+

6

EGS EDS

8

-

-

EVTHRES

+

19

8

CIN

15

CB

-

+

-

5

MSTRO

14

5
8

RSLC1

51

ISCL

50
RDRAIN

16

21

8

MMED

8

DBREAK

11

MWEAK

EBREAK

+

RSOURCE

RBREAK

17 18

IT

RVTHRES

17
18

­7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDD8882 / FDU8882 N-Channel PowerTrench® MOSFET

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v ( n5,n51))))*((abs(v(n5,n51)*1e6/600))** 10))
}
}

FDD8882/FDU8882 Rev. C

10

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FDD8882 / FDU8882 N-Channel PowerTrench® MOSFET

PSPICE Thermal Model

REV 23 October 2004
FDD8882T
CTHERM1 TH 6 5.6e-4

CTHERM2 6 5 6.8e-4
CTHERM3 5 4 2.0e-3
CTHERM4 4 3 2.8e-3
CTHERM5 3 2 5.7e-3
CTHERM6 2 TL 5.8e-3

RTHERM1 TH 6 5.3e-2
RTHERM2 6 5 2.2e-1
RTHERM3 5 4 2.9e-1
RTHERM4 4 3 3.9e-1
RTHERM5 3 2 6.0e-1
RTHERM6 2 TL 6.6e-1

SABER Thermal Model

SABER thermal model FDD8882T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 t h 6 =5.6e-4
ctherm.ctherm2 6 5 =6.8e-4
ctherm.ctherm3 5 4 =2.0e-3
ctherm.ctherm4 4 3 =2.8e-3
ctherm.ctherm5 3 2 =5.7e-3
ctherm.ctherm6 2 t l =5.8e-3

rtherm.rtherm1 th 6 =5.3e-2
rtherm.rtherm2 6 5 =2.2e-1
rtherm.rtherm3 5 4 =2.9e-1
rtherm.rtherm4 4 3 =3.9e-1
rtherm.rtherm5 3 2 =6.0e-1
rtherm.rtherm6 2 tl =6.6e-1
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

RTHERM6

2

CTHERM6

tl

CASE

FDD8882/FDU8882 Rev. C

11

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TRADEMARKS

®

tm

tm

The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
subsidianries, and is not intended to be an exhaustive list of all such trademarks.

®

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®

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™

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FAST
FastvCore™
FlashWriter

®

®

®

®

®

*

* EZSWITCH™ and FlashWriter

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®

FRFET
Global Power Resource
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®

®

are trademarks of System General Corporation, used under license by Fairchild Semiconductor.

®

®

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SM

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®

®

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Saving our world 1mW at a time™
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®

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®

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®

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®

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DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

®

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body or (b)
support or sustain life, and (c) whose failure to perform when
properly used in accordance with instructions for use provided

2. A critical component in any component of a life support,
device, or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.

in the labeling, can be reasonably expected to result in a
significant injury of the user.

PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design

This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.

This datasheet contains preliminary data; supplementary data will be pub-

Preliminary First Production

lished at a later date. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve design.

No Identification Needed Full Production

Obsolete Not In Production

FDD8882/FDU8882 Rev. C

This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve the design.

This datasheet contains specifications on a product that is discontinued by
Fairchild Semiconductor. The datasheet is for reference information only.

Rev. I34

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