Datasheet FDD8878, FDU8878 Datasheet (Fairchild)

0

April 2008

FDD8878 / FDU8878 N-Channel PowerTrench

FDD8878 / FDU8878 N-Channel PowerTrench® MOSFET

30V, 40A, 15mΩ Features



r

= 15mΩ, V

DS(ON)



r

= 18.5mΩ, V

DS(ON)



High pe rformance trench tech nology for e xtremely low r

DS(ON)



Low gat e ch arge



High power and current handling capability



RoHS Compliant

= 10V, ID = 35A

GS

= 4.5V, ID = 35A

GS

General Description

This N- Channe l MOSF ET has been desig ned sp ecif icall y to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM contro llers. It ha s be en optimize d for low gate cha r ge , low r

and fast switching speed.

DS(ON)

Application

 DC / DC Converters

tm

®

MOSFET

G

D

S

D-PAK

(TO-252)

DD8878 / FDU8878 Rev.

F

A4

G DS

1

I-PAK

(TO-251AA)

D

G

S

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FDD8878 / FDU8878 N-Channel PowerTrench

Absolute Maximum Rating s T

= 25°C unless otherwise noted

C

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Sou r c e Voltage 30 V Gate to Source Voltage ±20 V Drain Cur re nt Continuous (T

I

D

Continuous (T Continuous (T

= 25oC, VGS = 10V) ( Note 1)

C

= 25oC, VGS = 4.5V) (Note 1) 36 A

C

= 25oC, VGS = 10V, with R

amb

= 52oC/W) 11 A

θJA

40 A

Pulsed Figure 4 A

E

AS

P

D

T

, T

J

STG

Single Pulse Avalanche Energy (Note 2) 25 mJ Power dissipation 40 W Derate above 25

o

C0.27W/

Operating and Storage Temperature -55 to 175

Thermal Characteristics

R

θJC

R

θJA

R

θJA

Thermal Resistance Junction to Case TO-252, TO-251 3.75 Thermal Resistance Junction to Ambient TO-252, TO-251 100 Thermal Resistance Junction to Am bient TO-252, 1in2 copper pad ar ea 52

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDD8878 FDD8878 TO-252AA 13” 12mm 2500 units FDU88 78 FDU8878 TO- 251AA Tube N/A 75 unit s F F

o

C/W

o

C/W

o

C/W

o

C

o

C

®

MOSFET

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Condit ions Min Typ Max Units

Off Characteristics

B I

DSS

I

GSS

VDSS

Drain to Sou r c e Br ea k down Voltage ID = 250µA, VGS = 0V 30 - - V

V

= 24V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- -250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1.2 - 2.5 V

I

= 35A, VGS = 10V - 0.011 0.015

D

= 35A, VGS = 4.5V - 0.014 0.0185

I

Drain to S ou r c e On Re si st ance

D

I

= 35A, VGS = 10V,

D

T

= 175oC

J

- 0.018 0.024

µA

Ω

DD8878 / FDU8878 Rev. A

F

4

2

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Dynamic Characteristics

C C C R Q Q Q Q Q Q

ISS OSS RSS G

g(TOT) g(5) g(TH) gs gs2 gd

Input Capacitance Output Capacit ance - 195 - pF Reverse Transfer Capacitance - 110 - pF Gate Resistance VGS = 0.5V, f = 1MHz - 3.1 - Ω Total Gate Charge at 10V VGS = 0V to 10V Total Gate Charge at 5V VGS = 0V to 5V - 10 14 nC Threshold Gate Charge VGS = 0V to 1V - 0.9 1.3 nC Gate to Source Gate Charg e - 2.6 - nC Gate Charge Threshold to Plateau - 1.7 - nC Gate to Drain “Miller” Charge - 4.5 - nC

= 15V, VGS = 0V,

V

DS

f = 1MHz

V

DD

I

= 35A

D

= 1.0m A

I

g

FDD8878 / FDU8878 N-Channel PowerTrench

-880- pF

-1926nC

= 15V

Switching Characteristi cs

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Ti me Turn-On Delay Time - 7 - ns Rise Time - 79 - ns Turn-Off Delay Time - 38 - ns Fall Time - 27 - ns Turn-Off Time - - 97 ns

(VGS = 10V)

Drain-Source Diode Character istics

V

SD

t

rr

Q

RR

Notes: 1: Package current limitation is 35A. 2: Starting TJ = 25°C, L = 65uH, IAS = 28A, VDD = 27V, VGS = 10V. 3

Source to Drain Diode Voltage Reverse Recovery Time ISD = 35A, dISD/dt = 100A/µs- -23ns

Reverse Recovered Charge ISD = 35A, dISD/dt = 100A/µs- - 9nC

--129ns

= 15V, ID = 35A

V

DD

= 4.5V, RGS = 16Ω

V

GS

I

= 35A - - 1.2 5 V

SD

I

= 3.2A - - 1.0 V

SD

®

MOSFET

DD8878 / FDU8878 Rev. A

F

4

3

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fairchildsemi.com

FDD8878 / FDU8878 N-Channel PowerTrench

Typical Characteristics T

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

TC, CASE TEMPERATURE (oC)

= 25°C unless otherwise noted

C

150

125

Figure 1. Normalized Power Dissipation vs Case

Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

25 50 75 100 125 150

TC, CASE TEMPERATURE (oC)

VGS = 4.5V

CURRENT LIMITED BY PACKAGE

VGS = 10V

175

Figure 2. Maximum Continuous Drain Curr ent vs

Case Temperature

P

DM

t

1

t

x R

2

+ T

θJC

C

1

10

NOTES: DUTY FACTOR: D = t1/t PEAK TJ = PDM x Z

-2

10

-1

10

θJC

10

0

®

MOSFET

Figure 3. Normalized Maximum Transient Thermal Impedance

500

100

, PEAK CURRENT (A)

DM

I

30

DD8878 / FDU8878 Rev. A

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

VGS = 4.5V

-5

10

VGS = 10V

4

-4

10

-3

10

-2

10

t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

4

TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:

I = I

-1

10

175 - T

25

150

0

10

www.

C

1

10

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FDD8878 / FDU8878 N-Channel PowerTrench

Typical Characteristics T

1000

100

10

, DRAIN CURRENT (A)

D

I

1

SINGLE PULSE TJ = MAX RATED TC = 25oC

0.1 110

OPERATION IN THIS

AREA MAY BE

LIMITED BY r

VDS, DRAIN TO SOURCE VOLTAGE (V)

DS(ON)

= 25°C unless otherwise noted

C

Figure 5. Forward Bias Safe Operating Area

80

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

V

= 15V

DD

60

TJ = 25oC

40

10µs

100µs

1ms 10ms

DC

500

If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0 tAV = (L/R)ln [(IAS*R)/(1.3*RATED BV

100

10

, AVALANCHE CURRENT (A)

AS

I

60

STARTING TJ = 150oC

1

0.01 0.1 1 tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

ST ARTING TJ = 25oC

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

80

VGS = 5V

60

40

VGS = 10V

VGS = 4V

10

®

MOSFET

VGS = 3V

, DRAIN CURRENT (A)

D

I

20

TJ = 175oC

0

1.52.02.53.03.54.0 VGS, GATE TO SOURCE VOLTAGE (V)

TJ = -55oC

Figure 7. Transfer Charact eristics Figure 8. Saturation Characteristics

30

ID = 35A

25

20

, DRAIN TO SOURCE

ON RESISTANCE (mΩ)

15

ID = 1A

DS(ON)

r

10

246810

VGS, GATE TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

Figure 9. Drain to So urce On Resistance vs Gate

Voltage and Drain Current

, DRAIN CURRENT (A)

D

I

20

PULSE DURATION = 80µs

0

0 0.25 0.5 0.75 1.0 1.25 1.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

1.8

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

1.6

1.4

1.2

ON RESISTANCE

1.0

0.8

NORMALIZED DRAIN TO SOURCE

0.6

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

DUTY CYCLE = 0.5% MAX

TC = 25oC

VGS = 10V, ID = 35A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

DD8878 / FDU8878 Rev. A

4

5

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FDD8878 / FDU8878 N-Channel PowerTrench

Typical Characteristics T

1.2

1.0

0.8

NORMALIZED GATE

THRESHOL D VO LTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

C

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperature

2000

C

= CGS + C

1000

ISS

C

OSS

≅ C

DS

+ C

GD

1.10 ID = 250µA

1.05

1.00

BREAKDOWN VOLTAGE

0.95

NORMALIZED DRAIN TO SOURCE

0.90

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 15V

8

6

®

MOSFET

C

= C

RSS

GD

C, CAPACITANCE (pF)

100

V

= 0V, f = 1MHz

GS

50

0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Sour ce

Voltage

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

30

0 5 10 15 20

Qg, GATE CHARGE (nC)

WAVEFORMS IN DESCENDING ORDER:

ID = 35A ID = 1A

Figure 14. Gat e Charge Waveforms for Constant

Gate Current

DD8878 / FDU8878 Rev. A

4

6

fairchildsemi.com

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Test Circuits and Waveforms

V

DS

L

VARY tP TO OBTAIN REQUIRED PEAK I

V

GS

R

AS

G

+

V

DD

-

I

AS

DUT

t

0V

P

I

AS

0.01Ω

0

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

DS

V

DD

V

Q

I

g(REF)

L

V

GS

DUT

+

V

DD

-

V

GS

0

I

g(REF)

= 1V

Q

gs2

Q

g(TH)

Q

gs

0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

BV

DSS

t

P

t

AV

Q

g(TOT)

DS

Q

g(5)

V

GS

VGS = 5V

gd

FDD8878 / FDU8878 N-Channel PowerTrench

V

DS

V

DD

V

= 10V

GS

®

MOSFET

V

GS

R

GS

V

GS

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

DD8878 / FDU8878 Rev. A

4

V

DS

R

L

+

V

DD

-

V

DS

0

DUT

V

GS

10%

0

7

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

90%

PULSE WIDTH

50%50%

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Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, P application. Therefore the application’s ambient temperature, T must be reviewed to ensure that T Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

DM

θJA

, in an

(oC/W)

serve s as the basis for est ablis hing the rating of the part.

P

DM

TJMTA–()

----------------- ------------=

R

θJA

(EQ. 1)

125

100

C/W)

o

(

75

θJA

R

50

R

= 33.32+ 23.84/(0.268+Area) EQ.2

θJA

R

= 33.32+ 154/(1.73+Area) EQ.3

θJA

FDD8878 / FDU8878 N-Channel PowerTrench

In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power d issipati on rating s. Precise d etermin ation of P comple x and influenced by many factors:

DM

is

1. Mounting pad area onto which the device is attach ed and whethe r the re is copp er on one s ide or both side s of the board.

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air f low and board orientation.

6. For no n steady st ate applic ations, the pulse widt h, the duty cycle and the transient thermal response of the part, the boa rd and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 board with 1 oz c opper after 1 00 0 secon ds of stea dy st ate powe r w ith n o air flow . Th is gr aph prov ides the necessary inform ation for calc ulation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice t hermal model or manu ally utilizing the no rmalized maximum transient thermal impedance curve.

25

0.01 0.1 1 10 (0.645) (6.45) (64.5)(0.0645)

AREA, TOP COPPER AREA in2 (cm2)

Figure 21. Thermal Resistance vs Mounting

Pad Area

®

MOSFET

Therma l resist ances corresp onding to other co pper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inch es squ are and equ ation 3 is for area in centim eters square. The area, in square inches or square centimeters is the top copper area including the gate an d source pads.

23.84

R

DD8878 / FDU8878 Rev. A

θJA

=

33.32

-------------------------------------+

0.268 Area+()

Area in Inches Squared

154

----------------------------------+

1.73 Area+()

Area in Centimeters Squared

4

(EQ. 2)

(EQ. 3)

8

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PSPICE Electrical Model

.SUBCKT FDD8878 2 1 3 ; rev February 2004 Ca 12 8 8.6e-10 Cb 15 14 7.2e-10 Cin 6 8 8e-10

Dbod y 7 5 Dbody M OD Dbreak 5 11 D breakMOD Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 32.97 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1

It 8 17 1 Lgat e 1 9 5.4e- 9

Ldrain 2 5 1.0e -9 Lsou rce 3 7 2e- 9

RLgate 1 9 54 RLdr ai n 2 5 10 RLsource 3 7 20

Mmed 16 6 8 8 M m edMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 6.9e-3 Rgate 9 20 3.1 RSLC1 5 51 RSL CM OD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2.7e-3 Rvthres 22 8 RvthresMO D 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BM OD S2a 6 15 14 13 S2AM OD S2b 13 15 14 13 S2BM OD

Vbat 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

-

18 22

20

S1A

12

13814

S1B

EGS EDS

-

13

10

6 8

+

RSLC2

6

S2A

13

S2B

6 8

-

DPLCAP

EVTHRES

+

19

8

CIN

15

CB

-

+

-

5

51

5

51

21

MSTRO

14

5 8

RSLC1

+

ESLC

50

RDRAIN

16

8

MMED

8

DBREAK

11

+

17

EBREAK

18

-

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

7

+

RVTEMP 19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDD8878 / FDU8878 N-Channel PowerTrench

®

MOSFET

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))* (P WR(V(5,51)/(1e-6*125),5))} .MODEL DbodyMOD D (IS=2.6E-12 IKF=8 N=1.01 RS=6.4e-3 TRS1=8e-4 TRS2=2e-7

+ CJO=3.4e-10 M=0.53 TT=1e -17 XTI=2) .MODEL DbreakMOD D (RS=1.4 TRS1=1e-3 TRS2=-5e-6) .MODEL DplcapMOD D (CJO=3.4e-10 IS=1e-30 N=10 M=0.39)

.MODEL Mmed MOD NM O S (VTO=1.75 KP=7 IS = 1 e-30 N=10 TO X=1 L=1u W=1u R G = 3.1 T_ABS=25) .MODEL MstroMOD NMOS (VTO=2.2 KP=100 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25) .MODEL Mwe akMOD NMOS (VTO =1.45 KP=0. 03 IS=1e-30 N= 10 TO X = 1 L=1u W=1u RG=31 RS=0.1 T_ABS =25)

.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7) .MODEL Rd rai nMOD RES (TC1=1e-4 TC2=7. 5e-6) .MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=1.3e-2 TC 2=2e-6) .MODEL RvthresMOD RES (TC1=-1.7e -3 T C2=-8e-6) .MODEL RvtempMOD RES (T C1=-2.2e-3 TC2=2e-7)

.MODEL S1AMOD VSWITC H (RON =1e- 5 ROF F= 0. 1 VON=- 4. 5 VOFF =-3 .5 ) .MODEL S1BMOD VSWITC H (RON =1e- 5 ROF F= 0. 1 VON=- 3. 5 VOFF =-4 .5 ) .MODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 2 VOFF =-1 ) .MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 1 VOFF =-2 ) .ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Rec o rds, 1991, writ ten by William J. Hepp and C. Frank Wheatley.

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DD8878 / FDU8878 Rev. A

4

9

www.

SABER Electrical Model

rev Februar y 2004 template FDD 8878 n2,n1,n3 =m_temp electrical n2,n1,n3 number m_temp=25 { var i iscl dp..model dbodymod = (isl=2.6e-12,ikf=8,nl=1.01,rs=6.4e-3,trs1=8e-4,trs2=2e-7,cjo=3.4e-10,m=0.53,tt=1e-17,xti=2) dp..model dbreakmod = (rs=1.4,trs1=1e-3 ,t rs 2=-5e-6) dp..model dplcapmod = (cjo=3.4e-10,isl=10e-30,nl=10,m=0.39) m..model mmedmod = (type=_n,vto=1.75,kp=7,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.2,kp=100,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.45,kp=0.03,is=1e-30, tox=1,rs=0.1) sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0.1,von=-4.5, vof f =-3.5) sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0.1,von=-3.5, vof f =-4.5) sw_vcsp.. mo del s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-1) sw_vcsp.. mo del s2bmod = (ron=1e-5,roff=0.1,von=-1,voff=-2) c.ca n12 n8 = 8. 6e-10 c.cb n15 n14 = 7.2e-10 c.cin n6 n8 = 8e-10

dp.dbody n7 n5 = model=dbodym od dp.dbreak n5 n11 = model=dbreakmod

ESG

dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 32.97

spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1

GATE

1

LGATE

RLGATE

RGATE

9

EVTEMP +

18 22

20

spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1 l.lgate n1 n9 = 5.4e-9

l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2e-9

CA

S1A

12

S1B

res.rlgate n1 n9 = 54 res.rldrai n n2 n5 = 10 res.rlsource n3 n7 = 20

m.mmed n16 n6 n8 n8 = m odel=mmedm od, l= 1u, w=1u, temp= m _t em p m.mstrong n16 n6 n8 n8 = model=mstrongmod, l= 1u, w=1u, temp=m _temp m.mweak n16 n21 n8 n8 = model=mwea kmod, l=1u, w=1u, te m p=m_temp

DPLCAP

10

RSLC2

6

8

EVTHRES

+

19

8

6

-

S2A

13814

13

S2B

13

+

6

EGS EDS

8

-

15

CIN

CB

-

+

-

5

MSTRO

14

5 8

RSLC1

51

ISCL

50 RDRAIN

16

21

8

MMED

8

DBREAK

11

MWEAK

EBREAK

+

RSOURCE

RBREAK

17 18

IT

RVTHRES

17 18

7

RVTEMP 19

-

+

22

RLSOURCE

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

FDD8878 / FDU8878 N-Channel PowerTrench

®

MOSFET

res.rbreak n17 n18 = 1, tc1=8.3e- 4, tc 2=-8e-7 res.rdrain n50 n16 = 6.9e-3, tc1=1e-4,tc2=7. 5e-6 res.rgat e n9 n20 = 3. 1 res.rslc1 n5 n51 = 1e-6, tc1=9e -4, tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsour ce n8 n7 = 2.7e-3, tc1= 1. 3e-2,tc2=2e- 6 res.rvthres n22 n8 = 1, tc1=-1.7e-3,tc2=-8e-6 res.rvtemp n18 n19 = 1, tc1=-2.2e-3,tc2=2e-7 sw_vcsp.s1 a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1 b n13 n12 n13 n8 = model = s1 bmod sw_vcsp.s2 a n6 n15 n14 n13 = model = s2 amod sw_vcsp.s2 b n13 n15 n14 n13 = model = s 2bmod

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5 ,n 51))))*((abs (v(n5,n51)* 1e6/125))** 5)) } }

DD8878 / FDU8878 Rev.

A4

10

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FDD8878 / FDU8878 N-Channel PowerTrench

PSPICE Thermal Model

REV 23 February 2004 FDD8878T CTHERM1 TH 6 3.5e-4

CTHERM2 6 5 5e-4 CTHERM3 5 4 2. 5e-3 CTHERM4 4 3 2. 7e-3 CTHERM5 3 2 5e-3 CTHERM6 2 TL 1e-2

RTHERM1 TH 6 2.9e-1 RTHERM2 6 5 3. 5e-1 RTHERM3 5 4 4. 5e-1 RTHERM4 4 3 5. 2e-1 RTHERM5 3 2 6. 9e-1 RTHERM6 2 TL 7e-1

SABER Thermal Model

SABER therm al m odel F DD8878T template thermal_model th tl thermal_ c th , tl { ctherm.c th erm 1 th 6 =3.5e -4 ctherm.ctherm2 6 5 =5e-4 ctherm.ctherm3 5 4 =2.5e-3 ctherm.ctherm4 4 3 =2.7e-3 ctherm.ctherm5 3 2 =5e-3 ctherm.ctherm6 2 tl =1e-2

rtherm.rtherm1 th 6 =2.9e-1 rtherm.rther m 2 6 5 =3.5e -1 rtherm.rther m 3 5 4 =4.5e -1 rtherm.rther m 4 4 3 =5.2e -1 rtherm.rther m 5 3 2 =6.9e -1 rtherm.rther m 6 2 tl =7e-1 }

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

®

MOSFET

RTHERM6

2

CTHERM6

tl

CASE

DD8878 / FDU8878 Rev. A

4

11

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Advance Information Formative or In Design

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data; supplementary data will be pub-

Preliminary First Production

lished at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

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Obsolete Not In Production

DD8878 / FDU8878 Rev. A

4

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.

This datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.

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Rev. I34