Datasheet FDD6685 Datasheet (Fairchild)

Page 1
May 2011
FDD
6685
FDD6685
30V P-Channel PowerTrench MOSFET
This P-Channel MOSFET is a rugged gate version of Fairchild Semiconductor’s advanced PowerTrench process. It has been optimized for power management applications requiring a wide range of gave drive voltage ratings (4.5V – 25V).
Features
• –40 A, –30 V. R R
• Fast switching speed
• High performance trench technology for extremely
low R
• High power and current handling capability
• Qualified to AEC Q101
DS(ON)
= 20 mΩ @ VGS = –10 V
DS(ON)
= 30 mΩ @ VGS = –4.5 V
DS(ON)
S
D
G
G
S
TO-252
Absolute Maximum Ratings T
D
o
=25
C unless otherwise noted
A
Symbol Parameter Ratings Units
V
Drain-Source Voltage
DSS
V
Gate-Source Voltage
GSS
ID
PD
TJ, T
STG
Continuous Drain Current @TC=25°C (Note 3) @TA=25°C (Note 1a) Pulsed, PW ≤ 100µs (Note 1b)
Power Dissipation for Single Operation (Note 1) 52 (Note 1a) (Note 1b)
Operating and Storage Junction Temperature Range
–30
±25
–40 –11
–100
3.8
1.6
–55 to +175
W
°C
V V
A
Thermal Characteristics
R
θJC
R
θJA
R
θJA
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
2011 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Case (Note 1) 2.9 Thermal Resistance, Junction-to-Ambient (Note 1a) 40 Thermal Resistance, Junction-to-Ambient (Note 1b) 96
For a copy of the requirements, see AEC Q101 at http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
certification.
°C/W °C/W °C/W
FDD6685 Rev D1
Page 2
FDD
6685
FDD
6685
Package Marking and Ordering Information
Device Marking Device Reel Size Tape Width Quantity
FDD6685 FDD6685 13” 12mm 2500 units
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units Drain-Source Avalanche Ratings (Note 4)
EAS Single Pulse Drain-Source
Avalanche Energy
IAS Maximum Drain-Source
Avalanche Current
ID = –11 A 42 mJ –11 A
Off Characteristics
BV
Drain–Source Breakdown Voltage
DSS
∆BVDSS ∆TJ
I
Zero Gate Voltage Drain Current VDS = –24 V, VGS = 0 V –1
DSS
I
Gate–Body Leakage VGS = ±25V, VDS = 0 V ±100 nA
GSS
Breakdown Voltage Temperature Coefficient
VGS = 0 V, ID = –250 µA ID = –250 µA, Referenced to 25°C
–30 V
–24
mV/°C
µA
On Characteristics (Note 2)
V
Gate Threshold Voltage
GS(th)
∆VGS(th) ∆TJ
R
DS(on)
I
On–State Drain Current VGS = –10 V, VDS = –5 V –20 A
D(on)
gFS Forward Transconductance VDS = –5 V, ID = –11 A 26 S
Gate Threshold Voltage Temperature Coefficient
Static Drain–Source
On–Resistance
VDS = VGS, ID = –250 µA ID = –250 µA, Referenced to 25°C
VGS = –10 V, ID = –11 A VGS = –4.5 V, ID = –9 A VGS = –10 V,ID = –11 A,TJ=125°C
–1 –1.8 –3 V
5
14
21 20
20 30
mV/°C
mΩ
Dynamic Characteristics
C
Input Capacitance 1715 pF
iss
C
Output Capacitance 440 pF
oss
C
Reverse Transfer Capacitance
rss
RG Gate Resistance VGS = 15 mV, f = 1.0 MHz 3.6
VDS = –15 V, V f = 1.0 MHz
= 0 V,
GS
225 pF
Ω
Switching Characteristics (Note 2)
t
Turn–On Delay Time 17 31 ns
d(on)
tr Turn–On Rise Time 11 21 ns t
Turn–Off Delay Time 43 68 ns
d(off)
tf Turn–Off Fall Time Qg Total Gate Charge 17 24 nC Qgs Gate–Source Charge 9 nC Qgd Gate–Drain Charge
VDD = –15 V, ID = –1 A, VGS = –10 V, R
VDS = –15V, ID = –11 A, VGS = –5 V
GEN
= 6 Ω
21 34 ns
4 nC
Drain–Source Diode Characteristics and Maximum Ratings
VSD Drain–Source Diode Forward
Trr Qrr
Voltage Diode Reverse Recovery Time Diode Reverse Recovery Charge
VGS = 0 V, IS = –3.2 A (Note 2) –0.8 –1.2 V
IF = –11 A, diF/dt = 100 A/µs
26 ns 13 nC
FDD6685 Rev D1
Page 3
FDD6685
Electrical Characteristics T
= 25°C unless otherwise noted
A
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
3. Maximum current is calculated as: where PD is maximum power dissipation at TC = 25°C and R
4. Starting TJ = 25°C, L = 0.69mH, IAS = –11A
is guaranteed by design while R
θJC
R
is determined by the user's board design.
θCA
a) R
= 40°C/W when mounted on a
θJA
1in2 pad of 2 oz copper
P
D
)ON(DS
b) R
θJA
on a minimum pad.
is at T
DS(on)
= 96°C/W when mounted
and VGS = 10V.
J(max)
FDD6685 Rev D1
Page 4
FDD
6685
Typical Characteristics
40
VGS = -10V
-6.0V -5.0V
30
20
, DRAIN CURRENT (A)
D
10
-I
0
0 1 2 3
-4.5V
-4.0V
-3.5V
-VDS, DRAIN-SOURCE VOLTAGE (V)
-3.0V
2.4
VGS = -3.5V
2.2
2
1.8
1.6
1.4
NORMALIZED
1.2
DRAIN-SOURCE ON-RESISTANCE
1
0.8
-4.0V
-4.5V
-5.0V
-6.0V
-8.0V
0 2 4 6 8 10
-ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6 ID = -11.0A VGS = -10V
1.4
1.2
1
NORMALIZED
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
-50 -25 0 25 50 75 100 125 150 175
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. On-Resistance Variation with
Temperature.
0.08
0.06
0.04
, ON-RESISTANCE (OHM)
0.02
DS(ON)
R
0
Figure 4. On-Resistance Variation with
TA = 125oC
TA = 25oC
2 4 6 8 10
-VGS, GATE TO SOURCE VOLTAGE (V)
Gate-to-Source Voltage.
-10V
ID = -5.5A
40
VDS = -5V
30
20
, DRAIN CURRENT (A)
D
10
-I
0
1 2 3 4 5
-VGS, GATE TO SOURCE VOLTAGE (V)
TA = -55oC
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation
25oC
125oC
100
VGS = 0V
10
1
0.1
0.01
, REVERSE DRAIN CURRENT (A)
0.001
S
-I
0.0001 0 0.2 0.4 0.6 0.8 1 1.2 1.4
with Source Current and Temperature.
TA = 125oC
25oC
-55oC
-VSD, BODY DIODE FORWARD VOLTAGE (V)
FDD6685 Rev D1
Page 5
FDD
6685
Typical Characteristics
10
ID = -11.0 A
8
6
4
, GATE-SOURCE VOLTAGE (V)
2
GS
-V
0
0 5 10 15 20 25 30
VDS = 10V
20V
Qg, GATE CHARGE (nC)
30V
2400
1800
1200
CAPACITANCE (pF)
C
iss
C
600
C
rss
0
0 5 10 15 20 25 30
oss
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.
1000
100
R
LIMIT
10
1
, DRAIN CURRENT (A)
D
I
0.1
0.01
DS(ON)
1
10s DC
VGS = 10V
SINGLE PULSE
R
= 96oC/W
θJA
TA = 25oC
0.01 0.10 1.00 10.00 100.00
VDS, DRAIN-SOURCE VOLTAGE (V)
10ms
100ms
1ms
100µs
100
80
60
40
20
P(pk), PEAK TRANSIENT POWER (W)
0
0.01 0.1 1 10 100 1000
t1, TIME (sec)
SINGLE PULSE
R
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
= 96°C/W
θJA
TA = 25°C
f = 1MHz VGS = 0 V
1
D = 0.5
0.2
0.1
0.01
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
0.001
0.0001 0.001 0.01 0.1 1 10 100 1000
0.1
0.05
0.02
0.01
SINGLE PULSE
t1, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design.
R
(t) = r(t) * R
qJA
R
= 96 °C/W
qJA
P(pk)
t
1
t
2
TJ- TA= P * R
Duty Cycle, D = t1 / t
qJA
(t)
qJA
2
FDD6685 Rev D1
Page 6
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tm
®
tm
tm
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®
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Advance Information Formative / In Design
Preliminary First Production
No Identification Needed Full Production
Obsolete Not In Production
Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
Datasheet contains preliminary data; supplement ary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.
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Rev. I54
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