Datasheet FDD6632 Datasheet (Fairchild Semiconductor)

FDD6632

N-Channel Logic Level UltraFET® Trench Power MOSFET
30V, 9A, 90mΩ

FDD6632

June 2002

General Description

This device employs a new advanced trench MOSFET

Features

•Fast switching
technology and features low gate charge while maintaining
low on-resistance.

Optim ized for swit ch ing appl icat ions , t his devi ce i mpr ove s
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.

Formerly developmental type 83317

Applications

•r

•r

•Q

•Q

•C

= 0.058Ω (Typ), VGS = 10V, ID = 9A

DS(ON)

= 0.090Ω (Typ), VGS = 4.5V, ID = 6A

DS(ON)

(Typ) = 2.6nC, VGS = 5V

g(TOT)

(Typ) = 0.8nC

gd

(Typ) = 255pF

ISS

• DC/DC converters

D

TO-252

D

G

S

= 25°C unless otherwise noted

C

G

S

D-PAK

(TO-252)

MOSFET Maximum Ratings T

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Sou r c e Voltage 30 V
Gate to Source Voltage ±20 V
Drain Curr e nt
Continuous (T

I

D

Continuous (T
Continuous (T

= 25oC, VGS = 10V)

C

= 100oC, VGS = 4.5V) 6 A

C

= 25oC, VGS = 10V, R

C

= 52oC/W) 4 A

θJA

9A

Pulsed Figure 4 A

P

D

, T

T

J

STG

Power dissipation 15 W
Derate above 25

o

C0.1W/

Operating and Storage Temperature -55 to 175

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

Thermal Resistance Junction to Case TO-252 10
Thermal Resistance Junction to Ambient TO-252 100
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad ar ea 52

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDD6632 FDD6632 TO-252AA 330mm 16mm 2500 units

©2002 Fairchild Semiconductor Corporation

o

C/W

o

C/W

o

C/W

FDD6632 Rev. B

FDD6632

Electrical Characteristics T

= 25°C unless otherwise noted

C

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B
I

DSS

I

GSS

VDSS

Drain to Sou r c e Br ea k down Voltag e ID = 250µA, VGS = 0V 30 - - V

V

= 25V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- -250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA1-3V

I

= 9A, VGS = 10V - 0.058 0.090

Drain to S ou r c e On Re si st ance

D

= 6A, VGS = 4.5V - 0.090 0.110

I

D

Dynamic Characteristics

C
C
C
Q
Q
Q
Q

ISS
OSS
RSS

g(TOT)
g(TH)
gs
gd

Input Capacitance
Output Capacitance - 73 - pF
Reverse Transfer Capacitance - 23 - pF
Total Gate Charge at 5V VGS = 0V to 5V
Threshold Gate Charge VGS = 0V to 1V - 0.3 0.5 nC
Gate to Source Gate Charg e - 0.8 - nC
Gate to Drain “Miller” Charge - 0.8 - nC

Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 10 - ns
Rise Time - 41 - ns
Turn-Off D elay Time - 10 - ns
Fall Time - 23 - ns
Turn-Off Time - - 50 ns

(VGS = 4.5V)

= 15V, VGS = 0V,

V

DS

f = 1MHz

V

= 15V, ID = 6A

DD

V

= 4.5V, RGS = 47Ω

GS

V

DD

I

= 9A

D

I

= 1.0m A

g

= 15V

-255- pF

-2.64.0nC

- - 77 ns

µA

Ω

Switching Characteristics (V

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 4 - ns
Rise Time - 2 - ns
Turn-Off D elay Time - 33 - ns
Fall Time - 20 - ns
Turn-Off Time - - 80 ns

GS

= 10V)

V

= 15V, ID = 6A

DD

V

= 10V, RGS = 47Ω

GS

--9ns

Unclamped Inductive Switching

t

AV

Avalanche Time ID = 2.3A, L = 3.0mH 153 - - µs

Drain-Source Diode Characteristics

I

= 9A - - 1.25 V

V

SD

t

rr

Q

RR

©2002 Fairchild Semiconductor Corporation FDD6632 Rev. B

Source to Drain Diode Voltage
Reverse Recovery Time ISD = 9A, dISD/dt = 100A/µs--18ns

Reverse Recovered Charge ISD = 9A, dISD/dt = 100A/µs--8nC

SD

I

= 5A - - 1.0 V

SD

FDD6632

Typical Characteristics T

= 25°C unless otherwise noted

C

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

-4

10

SINGLE PULSE

10

10

8

6

4

, DRAIN CURRENT (A)

D

I

2

150

0

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Curr ent vs

-3

t, RECTANGULAR PULSE DURATION (s)

-2

10

V

GS

V

GS

TC, CASE TEMPERATURE (oC)

Case Temperature

P

DM

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-1

10

θJC

10

1/t2

0

x R

= 10V

= 4.5V

θJC

t

+ T

1

t

2

C

1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

100

VGS = 5V

, PEAK CURRENT (A)
I

TRANSCONDUCTANCE

DM

MAY LIMIT CURRENT
IN THIS REGION

10

7

-5

10

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

TC = 25oC
FOR TEMPERATURES

o

ABOVE 25

C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

I = I

25

10

C

150

0

1

10

Figure 4. Peak Current Capability

©2002 Fairchild Semiconductor Corporation FDD6632 Rev. B

FDD6632

Typical Characteristics T

20

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

V

= 15V

DD

15

10

, DRAIN CURRENT (A)

D

I

5

TJ = 175oC

0

123456

TJ = 25oC

TJ = -55oC

VGS, GATE TO SOURCE VOLTAGE (V)

= 25°C unless otherwise noted

C

Figure 5. Transfer Characteristics Figure 6. Saturation Characteristics

150

125

ID = 6A

100

, DRAIN TO SOURCE

ON RESISTANCE (mΩ)

75

DS(ON)

r

50

246810

ID = 9A

V

, GATE TO SOURCE VOLTAGE (V)

GS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

20

VGS = 10V

15

10

, DRAIN CURRENT (A)

D

I

5

0

0 0.5 1.0 1.5 2.0 2.5

VDS, DRAIN TO SOURCE VOLTAGE (V)

2.0

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

VGS = 5V

VGS = 4.5V

VGS = 3.5V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = 10V, ID = 9A

TC = 25oC

Figure 7. Drain to Source O n Resistance vs Gate

Voltage and Drain Current

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

Figure 9. Normali zed Gate Threshold Voltage vs

Junction Temperatur e

©2002 Fairchild Semiconductor Corporation FDD6632 Rev. B

Figure 8. Normalized Drain to Source On

Resistance vs Junction Temperature

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200
T

, JUNCTION TEMPERATURE (oC)

J

Figure 10. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

FDD6632

Typical Characteristics T

= 25°C unless otherwise noted

C

500

C

= CGS + C

ISS

C

≅ C

DS

+ C

100

OSS

C

= C

RSS

GD

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

10

0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 11. Capacitance vs Drain to Sour ce

Voltage

50

VGS = 4.5V, VDD = 15V, ID = 6A

40

30

20

SWITCHING TIME (ns)

10

0

0 1020304050

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

d(OFF)

t

d(ON)

10

GD

VDD = 15V

8

GD

6

4

WAVEFORMS IN

, GATE TO SOURCE VOLTAGE (V)

2

GS

V

30

0

012345

Qg, GATE CHARGE (nC)

DESCENDING ORDER:

ID = 9A
I

= 4A

D

Figure 12. Gat e Charge Waveforms for Constant

Gate Currents

40

t

r

t

f

VGS = 10V, VDD = 15V, ID = 6A

30

t

d(OFF)

20

t

f

SWITCHING TIME (ns)

10

t

d(ON)

t

0

r

0 1020304050

RGS, GATE TO SOURCE RESISTANCE (Ω)

Figure 13. Switching Time vs Gate Resist ance Figure 14. Switching Time vs Gate Resistance

Test Circuits and Waveforms

V

DS

L

I

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

R

AS

G

+

V

DD

-

AS

DUT

t

0V

P

I

AS

0

0.01Ω

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Wavef orm s

©2002 Fairchild Semiconductor Corporation FDD6632 Rev. B

BV

DSS

t

P

t

AV

V

DS

V

DD

Test Circuits and Waveforms (Cont i nu ed )

V

DS

R

L

V

GS

+

V

DD

-

DUT

I

g(REF)

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

V

DD

V

0

I

g(REF)

0

GS

= 1V

Q

g(TOT)

V

DS

Q

g(TH)

Q

gs

Q

gd

FDD6632

V

GS

V

= 5V

GS

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

t

r

10%

PULSE WIDTH

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

d(OFF)

90%

t

OFF

t

f

90%

10%

50%50%

©2002 Fairchild Semiconductor Corporation FDD6632 Rev. B

Thermal Resistance vs. Mounting Pad Area

125

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maxi mum al lowab le de vice p ower di ssip ation, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

serve s as the basis for establ ishing the rating of the part.

TJMTA–()

P

----------------- ------------=

DM

R

θJA

DM

(oC/W)

θJA

(EQ. 1)

, in an

100

C/W)

o

(

θJA

R

FDD6632

R

= 33.32 + 23.84/(0.268+Area)

θJA

75

50

In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power d issipati on rating s. Precise d etermin ation of P
comple x and influenced by many factors:

DM

is

1. Mou nting pad area ont o which the device is attached and
whet her the re is copp er on one s ide or both side s of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For no n steady state applic ations, th e pulse widt h, the
duty cycle and the transient thermal response of the part,
the boa rd and the environment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 bo ar d with 1oz c opper af t er 1000 se c on ds
of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides
the necessary inf ormation for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice t hermal model or manu ally utilizin g the normal ized
maximum transient thermal impedance curve.

25

0.01 0.1 1 10
AREA, TOP COPPER AREA (in2)

Figure 21. Thermal Resistance vs Mounting

Pad Area

Therma l resi stances correspondi ng to other copper are as
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.

23.84

33.32

=

R

θJA

©2002 Fairchild Semiconductor Corporation FDD6632 Rev. B

-------------------------------------+

0.268 Area+()

(EQ. 2)

PSPICE Electrical Model

.SUBCKT FDD6632 2 1 3 ; rev March 2002
Ca 12 8 1.8e-10

Cb 15 14 1.9e-10
Cin 6 8 2.35e-1 0

Dbod y 7 5 DbodyMOD
Dbreak 5 11 Db reakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 32.05
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1
Lgat e 1 9 3.84e-9

Ldrain 2 5 1.00 e-9
Lsou rce 3 7 4e-9

RLgate 1 9 38.4
RLdr ai n 2 5 10
RLsource 3 7 40

Mmed 16 6 8 8 M m edMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 12e-3
Rgate 9 20 4.2
RSLC1 5 51 RSL CM OD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 3e-2
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BM OD
S2a 6 15 14 13 S2AM OD
S2b 13 15 14 13 S2BM OD

GATE

1

LGATE

RLGATE

RGATE

9

CA

-

ESG

+

EVTEMP

+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

6
8

13

10

RSLC2

6

14
13

+

+

6
8

-

-

DPLCAP

EVTHRES

+

19

8

S2A

S2B

FDD6632

+

17
18

-

7

RLSOURCE

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

5

RSLC1

51

+

5

ESLC

51

­50

RDRAIN

16

21

-

MSTRO

CIN

15

CB

14

+

5
8

-

8

MMED

8

DBREAK

11

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

DRAIN

2

SOURCE

3

Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,5 1)/ABS(V(5,51)))*(PWR (V (5,51)/(1e-6*40),3)) }

.MOD E L DbodyMOD D (IS=9.5E - 12 RS=2.3e-2 XTI = 1 I K F = 15.00 N= 1.15 TRS1 = 1.0e-3 TR S2=8.0 e- 7
+ CJO=1.7e-10 TT=7e-9 M=0.47)
.MODEL DbreakMOD D (RS= 1e-1 TRS1=1.12e-3 TRS2=1.25e-6)
.MODEL DplcapMOD D (CJO=8.1e-11 IS=1e-30 N=10 M=0.43)

.MODEL MmedM OD NMOS (VTO=1.76 KP=.6 IS=1e-30 N=10 TOX=1 L=1u W= 1u RG=4.2)
.MODEL MstroMOD NMOS (VTO=2. 08 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1 u)
.MODEL Mwe akMOD NMOS (VTO=1.52 KP=0.03 I S=1e-30 N=10 TOX =1 L=1u W=1u RG=42 RS=.1)

.MODEL Rb reakMOD RES (TC1=1.01e-3 TC2=1.00e-7)
.MODEL Rd rai nMOD RES (TC 1=9e-3 TC2=4e-5)
.MODEL RSLCMOD RES (TC1=5E-3 TC2=1E-6)
.MODEL RsourceMOD RES (TC 1=1.0e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-1.5e-3 TC 2=-7e-6)
.MODEL RvtempMOD RES (T C1=-1.8e-3 TC 2=1. 2e-6)

.MODEL S1AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 4 VOFF =-1 .5 )
.MODEL S1BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 1.5 VO FF=- 4)
.MODEL S2AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 0. 6 VOFF =-0 .1 )
.MODEL S2BMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 0. 1 VOFF =-0 .6 )

.ENDS
NOTE: For further discussio n of the PSPICE model, con sult A New PSPICE Sub-Circ uit for the P ower MOSFET Featu ring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2002 Fairchild Semiconductor Corporation FDD6632 Rev. B

SABER Electrical Model

REV March 2002
template FDD 6632 n2,n1,n3

electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=9.5e-12,rs=2.3e-2,xti=1,ikf=15.00,nl=1.15,trs1=1.0e-3,trs2=8.0e-7,cjo=1.7e-10,tt=7e-9,m=0.47)
dp..model dbreakmod = (rs=1e-1,trs1=1.12e-3,trs2=1.25e-6)
dp..model dplcapmod = (cjo=8.1e-11,isl=10e-30,nl=10,m=0.43)
m..model mmedmod = (type=_n,vto=1.76,kp=.6,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.08,kp=9,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.52,kp=0.03,is=1e-30, tox=1,rs=.1)
sw_vcsp.. mo del s1amod = (ron=1e- 5,roff=0.1,vo n=-4,voff=-1.5 )
sw_vcsp.. mo del s1bmod = (ron=1e- 5,roff=0.1,vo n=-1.5,voff=-4 )
sw_vcsp.. mo del s2amod = (ron=1e- 5,roff=0.1,vo n=-0.6,voff=-0 .1)
sw_vcsp.. mo del s2bmod = (ron=1e- 5,roff=0.1,vo n=-0.1,voff=-0 .6)
c.ca n12 n8 = 1.8e -10
c.cb n15 n14 = 1.9e-10
c.cin n6 n8 = 2.35 e-10

dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreak m od
dp.dplcap n10 n5 = model=dplca pm od

spe.ebreak n11 n7 n17 n18 = 32.05

ESG

spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1

GATE

1

LGATE

RLGATE

RGATE

9

EVTEMP

+

20

i.it n8 n17 = 1
l.lgate n1 n9 = 3.84e-9

l.ldrain n2 n5 = 1.00e-9
l.lsource n3 n7 = 4e-9

res.rlgate n1 n9 = 38.4
res.rldrai n n2 n5 = 10
res.rlsource n3 n7 = 40

CA

S1A

12

S1B

m.mmed n16 n6 n8 n8 = m odel=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=ms tr ongmod, l=1u, w=1 u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=1.01e-3,tc2=1.00e-7
res.rdrain n50 n16 = 12e-3, tc1= 9e-3,tc2=4e-5
res.rgate n9 n20 = 4.2
res.rslc1 n5 n51 = 1e-6, tc1=5e-3, tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsour ce n8 n7 = 3e-2, tc1=1.0e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-1.5e-3,tc2=-7e-6
res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=1.2e-6
sw_vcsp.s1 a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1 b n13 n12 n13 n8 = model= s1 bmod
sw_vcsp.s2 a n6 n15 n14 n13 = model= s2 amod
sw_vcsp.s2 b n13 n15 n14 n13 = model= s 2bmod

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

+

6

-

18
22

S2A

13

14

8

13

S2B

13

+

+

6

EGS EDS

8

-

-

5

RSLC1

51

ISCL

16

8

MMED

DBREAK

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

50
RDRAIN

21

-

19

8

MSTRO

CIN

15

CB

14

+

5
8

-

+

17
18

-

RLDRAIN

LSOURCE

7

RLSOURCE

RVTEMP
19

­VBAT

+

22

LDRAIN

DBODY

DRAIN

2

SOURCE

3

FDD6632

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5, n51)/(1e-9+abs (v(n5,n51))))*((abs(v(n5,n51)*1e6/ 40))** 3))
}
}

©2002 Fairchild Semiconductor Corporation FDD6632 Rev. B

FDD6632

SPICE Thermal Model

REV 23 March 2002

FDD6632T

CTHERM1 TH 6 2.7e-4
CTHERM2 6 5 2. 9e-4
CTHERM3 5 4 6. 4e-4
CTHERM4 4 3 7e-4
CTHERM5 3 2 8. 2e-4
CTHERM6 2 TL 1.1e-3

RTHERM1 TH 6 4.8e-1
RTHERM2 6 5 8. 2e-1
RTHERM3 5 4 9e-1
RTHERM4 4 3 1. 2
RTHERM5 3 2 2. 1
RTHERM6 2 TL 2.5

SABER Thermal Model

SABER therm al model FDD6632T
template thermal_model th tl

thermal_ c th , tl
{
ctherm.c th erm 1 th 6 =2.7e-4
ctherm.ctherm2 6 5 =2.9e-4
ctherm.ctherm3 5 4 =6.4e-4
ctherm.ctherm4 4 3 =7e-4
ctherm.ctherm5 3 2 =8.2e-4
ctherm.ctherm6 2 tl =1.1e-3

rtherm.rtherm1 th 6 =4.8e-1
rtherm.rt herm2 6 5 =8.2e-1
rtherm.rt he rm3 5 4 =9e-1
rtherm.rt herm4 4 3 =1.2
rtherm.rt herm5 3 2 =2.1
rthe r m.rtherm6 2 tl =2.5
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

2

RTHERM6

tl

©2002 Fairchild Semiconductor Corporation FDD6632 Rev. B

CTHERM6

CASE

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PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Inf or m ation Formati ve or In

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identificat ion Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Production This datasheet contains specifications on a product

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supplementary data will be published at a later date.
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that has been disc ontinued by Fairchild se miconductor.
The datasheet is printed f or refe rence information only.

FDD6632 Rev. H5