Page 1
FDD5690
60V N-Channel PowerTrenchTM MOSFET
FDD5690
June 1999
PRELIMINARY
General Description
This N-Channel MOSFET has been designed specifically
to improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers.
These MOSFETs feature faster switching and lower gate
charge than other MOSFETs with comparable R
specifications.
DS(ON)
Features
30 A, 60 V. R
R
DS(ON)
DS(ON)
= 0.027Ω @ V
= 0.032 Ω @ V
= 10 V
GS
= 6 V.
GS
Low gate charge (23nC typical).
Fast switching speed.
High performance trench technology for extremely
low R
DS(ON)
.
The result is a MOSFET that is easy and safer to drive
(even at very high frequencies), and DC/DC power supply
designs with higher overall efficiency.
D
D
G
G
S
TO-252
Absolute Maximum Ratings
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
TJ, T
stg
Drain-Source Voltage 60 V
Gate-Source Voltage
Maximum Dra in Cu rrent -C on tinuo u s
(Note 1 a )
Maximum Drain Current -Pulsed 100
Maximum Power Dissipation @ TC = 25oC
TA = 25oC
Operating and Storage Junction Temperature Range -55 to +150
TC=25oC unless otherwise noted
(Note 1)
(Note 1)
TA = 25oC
(Note 1a )
(Note 1b )
S
±20
30
9
50
3.2
1.3
V
A
W
°C
Thermal Characteristics
R
JC
θ
R
JA
θ
Therm al R es is tan ce , Ju nc tion -to- C as e
Thermal Resistance, Junction-to- Ambient
(Note 1 b )
Package Marking and Ordering Inform ation
Device Marking Device Reel Size Tape width Quantity
FDD5690 FDD5690 13’’ 16mm 2500
1999 Fairchild Semiconductor Corporation
(Note 1)
(Note 1a)
2.5
40
96
°
C/W
°C/W
°C/W
FDD5690, Rev. B
Page 2
FDD5690
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
W
DSS
I
AR
BV
DSS
∆BVDSS
∆T
J
I
DSS
I
GSSF
I
GSSR
Single Pulse Drain-Source
VDD = 30 V, ID = 30 A 90 mJ
Avalanche Energy
Maximum Drain-Source Avalanche Current 30 A
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
= 0 V, ID = 250 µA
V
GS
= 250µA, Referenced to 25°C
I
D
60 V
57
mV/°C
Zero Gate Voltage Drain Current VDS = 48 V, VGS = 0 V 1
Gate-Body Leakage Current,
VGS = 20V, VDS = 0 V 100 nA
Forward
Gate-Body Leakage Current,
VGS = -20 V, VDS = 0 V -100 nA
Reverse
µA
On Characteristics (Note 2)
V
GS(th)
∆VGS(th)
∆T
J
R
DS(on)
I
D(on)
g
FS
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain-Source
On-Resistance
= VGS, ID = 250 µA
V
DS
= 250 µA,Referenced to 25°C
I
D
VGS = 10 V, ID = 9 A
V
= 10 V, ID = 9 A, TJ = 125°C
GS
V
= 6 V, ID = 8 A
GS
On-State Drain Current VGS = 10 V, VDS = 5 V 25 A
Forward Transconductance VDS = 5 V, ID = 9 A 24 S
22.54 V
-6
0.023
0.032
0.026
0.027
0.048
0.032
mV/°C
Ω
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance 1110 pF
Output Capacitance 150 pF
Reverse Transfer Capacitance
V
= 25 V, VGS = 0 V
DS
f = 1.0 MHz
75 pF
Switching Characteristics (Note 2)
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
g
gs
gd
Turn-On Delay Time 10 18 ns
Turn-On Rise Time 9 18 ns
= 30 V, ID = 1 A
V
DD
V
= 10 V, R
GS
GEN
= 6 Ω
Turn-Off Delay Time 24 39 ns
Turn-Off Fall Time
Total Gate Charge 23 32 nC
Gate-Source Charge 4 nC
V
= 30 V, ID = 9 A
DS
= 10 V,
V
GS
Gate-Drain Charge
Drain-Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the drain tab.
θJA
R
θJC
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Maximum Continuous Drain-Source Di ode Forward Current 2.3 A
Drain-Source Diode Forward
VGS = 0 V, IS = 2.3 A (Note 2) 0.75 1.2 V
Voltage
is guaranteed by design while R
is determined by the user's board design.
θCA
a) R
= 40oC/W when mounted
θJA
on a 1in2 pad of 2oz copper.
b) R
= 96oC/W on a minimum
θJA
mounting pad.
10 18 ns
6.8 nC
FDD5690, Rev. B
Page 3
Typical Characteristics
6.0V
FDD5690
60
50
40
30
20
10
, DRAIN-SOURCE CURRENT (A)
D
I
0
VGS = 10V
5.0V
4.5V
4.0V
012345
V
, DRAIN-SOURCE VOLTAGE (V)
DS
Figure 1. On-Region Characteristics.
2
ID = 9A
1.8
= 10V
V
GS
1.6
1.4
1.2
, NORMALIZED
1
DS(ON)
R
0.8
0.6
DRAIN-SOURCE ON-RESISTANCE
0.4
-50 -25 0 25 50 75 100 125 150
, JUNCTION TEMPERATURE (oC)
T
J
2
1.8
1.6
VGS = 4.5V
1.4
, NORMALIZED
1.2
DS(ON)
R
1
DRAIN-SOURCE ON-RESISTANCE
0.8
0 102030405060
5.0V
I
, DRAIN CURRENT (A)
D
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage.
0.08
0.06
0.04
, ON-RESISTANCE (OHM)
0.02
DS(ON)
R
0
345678910
, GATE TO SOURCE VOLTAGE (V)
V
GS
TA = 125oC
TA = 25oC
ID = 15A
Figure 3. On-Resistance Variation
with Temperature.
60
VDS = 5V
50
40
30
20
10
0
23456
V
, GATE TO SOURCE VOLTAGE (V)
GS
TA = -55oC
25oC
125oC
Figure 4. On-Resistance Variation
with Gate-to-Source Voltage.
100
VGS = 0V
10
1
0.1
0.01
0.001
0.0001
0 0.2 0.4 0.6 0.8 1 1.2 1.4
TA = 125oC
25oC
-55oC
, BODY DIODE FORWARD VOLTAGE (V)
V
SD
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDD5690, Rev. B
Page 4
Typical Characteristics (continued)
FDD5690
10
ID = 9A
8
6
4
2
, GATE-SOURCE VOLTAGE (V)
GS
V
0
0 5 10 15 20 25
Q
, GATE CHARGE (nC)
g
VDS = 10V
30V
Figure 7. Gate-Charge Characteristics.
100
R
LIMIT
DS(ON)
10
1
10S
DC
, DRAIN CURRENT (A)
0.1
D
I
VGS = 10V
SINGLE PULSE
= 96oC/W
R
JA
θ
= 25oC
T
A
0.01
0.1 1 10 100
, DRAIN-SOURCE VOLTAGE (V)
V
DS
1ms
10ms
100ms
1S
100µs
20V
2500
2000
1500
1000
500
0
0 102030405060
C
ISS
C
OSS
C
RSS
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
f = 1MHz
= 0 V
V
GS
Figure 8. Capacitance Characteristics.
60
SINGLE PULSE
= 96oC/W
R
JA
θ
T
= 25oC
40
POWER (W)
20
0
0.01 0.1 1 10 100 1000
SINGLE PULSE TIME (SEC)
A
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
0.2
0.1
0.01
0.001
r(t), NORMA L IZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
0.0001
0.0001 0.001 0.01 0.1 1 10 100 300
0.1
0.05
0.01
0.02
Single Pulse
t , TIME (sec)
1
R (t) = r(t) * R
JA
θ
R =
JA
θ
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t / t
96°C/W
JA
θ
1
JA
θ
2
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient themal response will change depending on the circuit board design.
FDD5690, Rev. B
Page 5
D-PAK (TO-252) Packaging
Configuration: Figure 1.0
N
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC
ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS
TNR DATE
PT NUMBER
PEEL STRENGTH MIN ______________gms
MAX _____________ gms
ESD Label
F63TNR
Label
Antis tatic Cover Tape
Static Dissipative
Embossed Carrier Tape
Packaging Description:
TO-252 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2500 units per 13” or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (antistatic coated). This and some other options are further
described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in di ff e rent siz es depe nd in g on th e num ber of pa rts
shippe d.
D-PAK (TO-252) Pac kaging Information
Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Reel Size
Box Dimension (mm)
Max qty per Box
Weight per unit (gm)
Weight pe r Reel(k g)
Note/Comments
Standard
(no flow code)
TNR
2,500
13” Dia
359x359x57
5,000
0.300
1.200
F63TNR Label sample
LOT: CBVK741B019
CBVK741B019
FSID: FDD6680
FDD6680
D/C1: Z9942 QTY1: SPEC REV:
D/C2: QTY2: CPN:
QTY: 2500
3000
SPEC:
N/F: F (F63TNR)3
TO-252 (D-PAK) Tape Leader and
Trailer Configuration: Figure 2.0
6680
FDD
F
Z9935
D-PAK (TO-252) Unit Orientation
359mm x 359mm x 57mm
Stand ard Intermed ia t e box
6680
FDD
F
Z9935
ESD Label
F63TNR Label
6680
FDD
F
Z9935
6680
FDD
F
Z9935
Carrier Tape
Cover Tape
Trailer Tap e
640mm minimum or
80 empty pockets
Components
Leader Tape
1680mm minimum or
210 empty pockets
Page 6
D-PAK (TO-252) Embossed Carrier
Tape Co nfiguration: Figure 3.0
T
K0
Wc
Tc
B0
A0
P0
D0
P1
D1
User Direction of Feed
Dimensions are in millimeter
E1
F
W
E2
Pkg ty pe
TO252
(24mm)
A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc
6.90
10.50
16.0
1.55
1.5
1.75
14.25
+/-0.10
+/-0.10
+/-0.3
+/-0.05
+/-0.10
+/-0.10
min
7.50
+/-0.10
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
10 deg maximum
B0
10 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
D-PAK (TO-252) Reel
A0
Sketch B (Top View)
Component Rotation
Configuration: Figure 4.0
W1 Measured at Hub
Dim A
max
Dim N
8.0
+/-0.1
Typical
component
cavity
center line
Typical
component
center line
Dim A
Max
Dim D
min
4.0
+/-0.1
2.65
0.30
+/-0.10
+/-0.05
0.9mm
maximum
Sketch C (Top View)
Component lateral movement
13.0
+/-0.3
0.9mm
maximum
B Min
Dim C
0.06
+/-0.02
Tape Size
164mm 13” Dia
Reel
Option
DETAIL AA
13” Diameter Option
See detail AA
W2 max Measured at Hub
W3
Dimensions are in inches and millimeters
Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
13.00
330
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
4.00
100
0.646 +0.078/-0.000
16.4 +2/0
0.882
22.4
0.626 – 0.764
15.9 – 19.4
Page 7
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
CROSSVOLT™
2
E
CMOS
TM
FACT™
FACT Quiet Series™
®
FAST
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STA TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or
In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. D
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