Datasheet FDD3682 Datasheet (Fairchild Semiconductor)

FDD3682

N-Channel PowerTrench® MOSFET 100V, 32A, 36mΩ

FDD3682

September 2002

Features

• r

• Q

• Low Miller Charge

• Low Q

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

Formerly developmental type 82755

= 32mΩ (Typ.), V

DS(ON)

(tot) = 18.5nC (Typ.), V

g

Body Diode

RR

= 10V, ID = 32A

GS

= 10V

GS

Applications

• DC/DC converters and Off-Line UPS

• Distributed Power Architectures and VRMs

• Primary Switch for 24V and 48V Systems

• High Volt age Synchronous Rectifier

• Direct Injection / Diesel Injection System

• 42V Automo tive Load Co ntrol

• Electro nic Valve Train System

DRAIN

(FLANGE)

GATE

SOURCE

TO-252AA

FDD SERIES

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

C

D

G

S

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Source Voltage 100 V Gate to Source Voltage ±20 V Drain Curr e nt Continuous (T

I

D

Continuous (T Continuous (T

= 25oC, VGS = 10V)

C

= 100oC, VGS = 10V) 23 A

C

= 25oC, VGS = 10V, R

amb

= 52oC/W) 5.5 A

θJA

32 A

Pulsed Figure 4 A

E

AS

P

D

, T

T

J

STG

Single Pulse Avalanche Energy (Note 1) 55 mJ Power dissipation 95 W

o

Derate above 25

C0.63W/

Operating and Storage Temperature -55 to 175

o

C

o

C

Thermal Characteristi cs

R

θJC

R

θJA

R

θJA

This product ha s been des igned to me et the e xtr eme test c ondit ions and envir onment deman ded by the automot ive indus t ry. For a

All Fairchild Semiconductor prod ucts are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

Thermal Resistance Junction to Case TO-252 1.58 Thermal Resistance Junction to Ambient TO-252 100 Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad ar ea 52

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

certification.

FDD3682 Rev. B

o

C/W

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDD3682 FDD3682 TO-252AA 330mm 16mm 2500 units

FDD3682

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B I

DSS

I

GSS

VDSS

Drain t o Source Breakdown Volta ge ID = 250µA, VGS = 0V 100 - - V

V

= 80V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC = 150oC- - 250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

I

Drain to Source On Resistance

= 32A, V

D

I

= 16A, VGS = 6V - 0.040 0.060

D

I

= 32A, V

D

T

= 175oC

C

= 10V - 0.03 2 0.036

GS

= 10V ,

GS

- 0.080 0.090

Dynamic Characteristics

C C C Q Q Q Q Q

ISS OSS RSS

g(TOT) g(TH) gs gs2 gd

Input Capacitance Output Capacitance - 190 - pF Reverse Transfer Capacitance - 45 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total G ate Ch arg e at 10 V VGS = 0V to 10V Threshold Gate Charge VGS = 0V to 2V - 2.4 3.6 nC Gate to Source Gate Charge - 6.5 - nC Gate Charge Threshold to Plateau - 4.1 - nC

V

DD

I

= 32A

D

I

= 1.0m A

g

= 50V

Gate to Drain “Miller” Charge - 4.6 - nC

-1250- pF

-18.528nC

µA

Ω

Resistive Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time Turn-On Delay Time - 9 - ns Rise Time - 46 - ns T u rn-Off Delay Time - 24 - ns Fall Time - 26 - ns Turn-Off Time - - 75 ns

(VGS = 10V)

V

DD

V

GS

--83ns

= 50V, ID = 32A = 10V, RGS = 16Ω

Drain-Source Diode Characteristics

I

= 32A - - 1 .25 V

V

SD

t

rr

Q

RR

Notes: 1: Starting T

Source to Drain Di ode Voltage Reverse Recovery Time ISD = 32A, dISD/dt = 100A/µs- - 55 ns

Reverse Recovery Charge ISD = 32A, dISD/dt = 100A/µs- - 92 nC

= 25°C, L = 0.27mH, IAS = 20A.

J

SD

= 16A - - 1.0 V

I

SD

FDD3682

Typical Characteristics T

= 25°C unless otherwise noted

C

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

1

0.5

0.2

0.1

0.05

0.02

0.01

150

35

V

= 10V

30

GS

25

20

15

, DRAIN CURRENT (A)

10

D

I

5

0

25 50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

Figure 2. Maximum Continuous Drain Curr ent vs

Case Temperature

, NORMALIZED

θJC

Z

400

100

, PEAK CURRENT (A)

DM

I

0.1

THERMAL IMPEDANCE

0.01

30

10

-5

10

VGS = 10V

-5

SINGLE PULSE

-4

10

-3

10

-2

10

NOTES: DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

TC = 25oC

FOR TEMPERATURES ABOVE 25 CURRENT AS FOLLOWS:

I = I

P

DM

1/t2

x R

θJC

0

10

o

C DERATE PEAK

175 - T

25

0

10

t

θJC

150

1

t

2

+ T

C

1

10

C

1

10

Figure 4. Peak Current Capability

Typical Characteristics T

= 25°C unless otherwise noted

C

FDD3682

200

100

1ms

10

OPERATION IN THIS

AREA MAY BE

LIMITED BY r

1

, DRAIN CURRENT (A)

D

I

SINGLE PULSE TJ = MAX R ATED

T

= 25oC

C

0.1 1 10 100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

10ms

DC

10µs

100µs

Figure 5. Forward Bias Safe Operating Area

80

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

V

= 15V

DD

60

40

TJ = 175oC

100

If R = 0

200

tAV = (L)(IAS)/(1.3*RATED BV If R ≠ 0

t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

10

, AVALANCHE CURRENT (A)

AS

I

1

STARTING TJ = 150oC

0.001 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

80

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

60

TC = 25oC

40

VGS = 20V

- VDD) +1]

10

VGS = 10V

VGS = 6V

, DRAIN CURRENT (A)

D

I

20

0

TJ = 25oC

TJ = -55oC

3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 VGS, GATE TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

60

PULSE DURATION = 80ms DUTY CYCLE = 0.5% MAX

50

40

30

DRAIN TO SOURCE ON RESISTANCE (mΩ)

20

0 5 10 15 20 25 30 35

Id, DRAIN CURRENT (A)

VGS = 6V

VGS = 10V

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

, DRAIN CURRENT (A)

D

I

20

0

01234

VDS, DRAIN TO SOURCE VOLTAGE (V)

3.0

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

2.5

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

VGS = 5V

VGS = 10V, ID =32A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDD3682

Typical Characteristics T

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

= 25°C unless otherwise noted

C

VGS = VDS, ID = 250µA

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperatur e

2000

1000

C

≅ C

+ C

OSS

DS

GD

C

ISS

= CGS + C

GD

1.2 ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200 T

, JUNCTION TEMPERATURE (oC)

J

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 50V

8

6

C

= C

RSS

100

C, CAPACITANCE (pF)

20

0.1 1 10 100

GD

V

= 0V, f = 1MHz

GS

VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Sour ce

Voltage

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 5 10 15 20

Qg, GATE CHARGE (nC)

WAVEFORMS IN DESCENDING ORDER:

ID = 32A I

= 16A

D

Figure 14. Gate Charge Waveforms for Constant

Gate Currents

Test Circuits and Waveforms

FDD3682

BV

DSS

t

P

V

DS

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

V

DS

L

I

AS

R

AS

G

+

V

DD

-

DUT

t

0V

P

I

AS

0.01Ω

0

t

AV

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

I

g(REF)

DS

L

V

GS

+

V

DD

-

DUT

V

DD

V

GS

V

= 2V

GS

Q

0

Q

g(TH)

I

g(REF)

gs2

Q

gs

Q

g(TOT)

V

DS

Q

gd

0

V

DD

V

= 10V

GS

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

90%

PULSE WIDTH

50%50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maxi mum al lowab le de vice p ower di ssip ation, P application. Therefore the application’s ambient temperature, T must be reviewed to ensure that T Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

DM

θJA

, in an

(oC/W)

serve s as the basis for establ ishing the rating of the part.

P

DM

=

TJMTA–()

----------------- ------------

R

θJA

(EQ. 1)

125

100

C/W)

o

(

75

θJA

R

50

R

= 33.32+ 23.84/(0.268+Area) EQ.2

θJA

R

= 33.32+ 154/(1.73+Area) EQ.3

θJA

FDD3682

In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power d issipati on rating s. Precise d etermin ation of P comple x and influenced by many factors:

DM

is

1. Mou nting pad area ont o which the device is attached and whet her the re is copp er on one s ide or both side s of the board.

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For no n steady state applic ations, th e pulse widt h, the duty cycle and the transient thermal response of the part, the boa rd and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 board w i th 1 oz c opper af ter 100 0 se c on ds of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides the necessary inf ormation for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice t hermal model or manually u tilizing the normalized maximum transient thermal impedance curve.

25

0.01 0.1 1 10 (0.645) (6.45) (64.5)(0.0645)

AREA, TOP COPPER AREA in2 (cm2)

Figure 21. Thermal Resistance vs Mounting

Pad Area

Therma l resi stances correspondi ng to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeter square. The area, in square inches or square centimeters is the top copper area including the gate and source pads.

23.84

-------------------------------------

+

33.32

=

R

θJA

33.32

=

R

θJA

0.268 Area+()

Area in Inches Squared

154

----------------------------------

+

1.73 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

PSPICE Electrical Model

.SUBCKT FDD3682 2 1 3 ; rev Jun 2002 Ca 12 8 4e-10 Cb 15 14 6e-10 Cin 6 8 1.22e-9

Dbod y 7 5 DbodyMOD Dbreak 5 11 Db reakMOD Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 112 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1

It 8 17 1 Lgat e 1 9 4.88e-9

Ldrain 2 5 1.0e -9 Lsource 3 7 2.24e-9

RLgate 1 9 48.8 RLdr ai n 2 5 10 RLsource 3 7 22.4

Mmed 16 6 8 8 M m edMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 10.5e-3 Rgate 9 20 1.8 RSLC1 5 51 RSL CM OD 1.0e-6 RSLC2 5 50 1.0e 3 Rsource 8 7 RsourceMOD 11.9e-3 Rvthres 22 8 RvthresMO D 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BM OD S2a 6 15 14 13 S2AM OD S2b 13 15 14 13 S2BM OD

Vbat 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

-

18 22

20

S1A

12

13

8

S1B

EGS EDS

6

8

13

10

RSLC2

6

14 13

+

6 8

-

DPLCAP

EVTHRES

+

19

S2A

S2B

FDD3682

-

17 18

7

+

RVTEMP 19

-

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

5

RSLC1

51

+

5

ESLC

51

50

RDRAIN

16

21

-

8

MSTRO

CIN

15

CB

8

14

+

5 8

-

MMED

8

DBREAK

11

+

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

DRAIN

2

SOURCE

3

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51))) *(PWR(V(5,51)/(1e-6 *70),2.5)) } .MOD E L DbodyMOD D (IS=2.4E - 12 RS=4.4e -3 TRS1= 2 . 0 e-3 TRS2= 4 . 5 e-7

+ CJO=9e-10 M=0.58 TT=2.9e -8 X T I=4.0) .MODEL DbreakMOD D (RS=0.6 TRS1=1.4 e-3 TRS2=-5.0e-5) .MODEL Dpl capMOD D (CJO=2.75e-10 IS=1.0e-30 N=10 M=0.56)

.MODEL Mstro M OD NMOS (VTO=4.16 K P=32 IS=1e-30 N =10 T OX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=3.48 KP=2.7 IS=1e-30 N=10 TOX =1 L=1u W=1u RG=1.8 ) .MODEL MweakMOD NMOS (VTO=2.96 KP=0.068 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=18 RS=0.1)

.MODEL Rb reakMOD RES (T C1=1.1e-3 TC2=-1.1e-8) .MODEL Rd rai nMOD RES (TC1=1.5e-2 TC 2=4e-5) .MODEL RSLCMOD RES (TC1=3.0e-3 TC2=2.9e-6) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-3.9e -3 T C2=-1.4e-5 ) .MODEL RvtempMOD RES (T C1=-3.5e-3 TC2=1.3e-6)

.MODEL S1AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 5. 0 VOFF =-2 .0 ) .MODEL S1BMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 2. 0 VOFF =-5 .0 ) .MODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 0.4 VO FF=0.3) .MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= 0 .3 VOFF= -0.4)

.ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electroni cs Specialist Conference Records, 1991, written by Wil liam J. Hepp and C. F rank Wheatley.

SABER Electrical Model

REV Jun 2002 template FDD 3682 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.4e-12,rs=4.4e-3,trs1=2.0e-3,trs2=4.5e-7,cjo=9e-10,m=0.58,tt=2.9e-8,xti=4.0) dp..model dbreakmod = (rs=0.6,trs1=1.4e-3,trs2=-5e- 5) dp..model dplcapmod = (cjo=2.7e-10,isl=10e-30,nl=10,m=0.56) m..model mstrongmod = (type=_n,vto=4.16,kp=32,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=3.48,kp=2.7,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.96,kp=0.068,is=1e-30, tox=1,rs=0.1) sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0. 1, von=-5,voff=-2) sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0. 1, von=-2,voff=-5) sw_vcsp.. mo del s2amod = (ron=1e-5,roff=0.1,von=-0.4, vof f = 0. 3) sw_vcsp.. mo del s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.4) c.ca n12 n8 = 4e- 10 c.cb n15 n14 = 6e- 10 c.cin n6 n8 = 1.22 e-9

dp.dbody n7 n5 = model=dbodym od dp.dbreak n5 n11 = model=dbr eakmod dp.dplcap n10 n5 = model=dplcapmod

spe.ebreak n11 n7 n17 n18 = 112 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1

GATE

spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1

LGATE

1

9

RLGATE

RGATE

ESG

EVTEMP +

18 22

20

spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1

CA

S1A

12

S1B

l.lgate n1 n9 = 4.88e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.24e-9

res.rlgate n1 n9 = 48.8 res.rldrai n n2 n5 = 10 res.rlsource n3 n7 = 22.4

m.mmed n16 n6 n8 n8 = m odel=mmedm od, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l= 1u, w=1u m.mweak n16 n21 n8 n8 = model=mwea kmod, l=1u, w=1u

DPLCAP

10

RSLC2

-

6 8

EVTHRES

+

19

6

-

S2A

13

14

8

13

S2B

13

+

6

EGS EDS

8

-

5

RSLC1

51

ISCL

8

MMED

8

DBREAK

11

MWEAK

EBREAK

+

RSOURCE

RBREAK

17 18

IT

RVTHRES

-

50

RDRAIN

16

21

-

8

MSTRO

CIN

15

CB

14

+

5 8

-

17 18

7

RLSOURCE

RVTEMP 19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

FDD3682

res.rbreak n17 n18 = 1, tc1=1.1e- 3,tc2=-1.1e -8 res.rdrain n50 n16 = 10.5e-3, tc 1=1.5e-2,tc 2=4e-5 res.rgate n9 n20 = 1.8 res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2 =2.9e-6 res.rslc2 n5 n50 = 1.0e3 res.rsour ce n8 n7 = 11.9e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-3.9e-3,tc2=-1. 4e-5 res.rvtemp n18 n19 = 1, tc1=-3.5e-3,tc2=1.3e-6 sw_vcsp.s1 a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1 b n13 n12 n13 n8 = mode l= s1bmod sw_vcsp.s2 a n6 n15 n14 n13 = mode l= s2amod sw_vcsp.s2 b n13 n15 n14 n13 = model = s2bmod

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5 ,n51))))*(( abs(v(n5,n51)*1e6/70) )** 2. 5)) } }

FDD3682

SPICE Thermal Model

REV 20 Jun 200 2 FDD3682_J C T H TL CTHERM1 TH 6 1.6e-3

CTHERM2 6 5 4. 5e-3 CTHERM3 5 4 5. 0e-3 CTHERM4 4 3 8. 0e-3 CTHERM5 3 2 8. 2e-3 CTHERM6 2 TL 4.7e-2

RTHERM1 TH 6 3.3e-2 RTHERM2 6 5 7. 9e-2 RTHERM3 5 4 9. 5e-2 RTHERM4 4 3 1. 4e-1 RTHERM5 3 2 2. 9e-1 RTHERM6 2 TL 6.7e-1

SABER Thermal Model

SABER therm a l model FDD3682 template thermal_model th tl thermal_ c th , tl { ctherm.c th erm 1 th 6 =1.6e-3 ctherm.ctherm2 6 5 =4.5e-3 ctherm.ctherm3 5 4 =5.0e-3 ctherm.ctherm4 4 3 =8.0e-3 ctherm.ctherm5 3 2 =8.2e-3 ctherm.ctherm6 2 tl =4.7e-2

rtherm.rtherm1 th 6 =3.3e-2 rtherm.rt herm2 6 5 =7.9e-2 rtherm.rt herm3 5 4 =9.5e-2 rtherm.rt herm4 4 3 =1.4e-1 rtherm.rt herm5 3 2 =2.9e-1 rthe r m.rtherm6 2 tl =6.7 e-1 }

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

RTHERM6

2

CTHERM6

CASE

tl

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Rev. I1