Datasheet FDD3672 Datasheet (Fairchild Semiconductor)

FDD3672

N-Channel UltraFET® Trench MOSFET 100V, 44A, 28mΩ

FDD3672

June 2002

Features

•r

•Q

• Low Miller Charge

= 24mΩ (Typ.), V

DS(ON)

(tot) = 24nC (Typ.), V

g

= 10V, ID = 44A

GS

= 10V

GS

Applications

• DC/DC converters and Off-Line UPS

• Distributed Power Architectures and VRMs

• PrimarySwitch for 24V and 48V Systems

• Low Qrr Body Diode

• Optimized eff iciency at high frequ encies

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

• High Voltage Synchronous R ectifier

• Direct Injection / Diesel Injection System

• 42V Automotive Load Control

• Electronic Valve Train System

Formerly developmental type 82760

GATE

SOURCE

DRAIN

(FLANGE)

G

D

TO-252AB

FDDSERIES

MOSFET Maximum Ratings T

= 25°C unless otherwise noted

C

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Source Voltage 100 V Gate to Source Voltage ±20 V Drain Curr e nt Continuous (T

I

D

Continuous (T Continuous (T

= 25oC, VGS = 10V)

C

= 100oC, VGS = 10V) 31 A

C

= 25oC, VGS = 10V, R

amb

= 52oC/W) 6.5 A

θJA

Pulsed Figure 4 A

E

AS

P

D

, T

T

J

STG

Single Pulse Avalanche Energy (Note 1) 120 mJ Power dissipation 135 W Derate above 25

o

C0.9W/

Operating and Storage Temperature -55 to 175

S

44 A

o

C

o

C

Thermal Characteristics

R

θJC

R

θJA

R

θJA

This product ha s been des igned to me et the e xtr eme test c ondit ions and envir onment deman ded by the automot ive indus t ry. For a

All Fairchild Semiconductor prod ucts are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

Thermal Resistance Junction to Case TO-252 1.11 Thermal Resistance Junction to Ambient TO-252 100 Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad ar ea 52

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

certification.

FDD3672 Rev. A

o

C/W

o

C/W

o

C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDD3672 FDD3672 TO-252AA 330mm 16mm 2500 units

FDD3672

Electrical Characteristics

TC = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B I

DSS

I

GSS

VDSS

Drain t o Source Breakdown Volta ge ID = 250µA, VGS = 0V 100 - - V

V

= 80V - - 1

Zero Gate Voltage Drain Current

DS

= 0V TC= 150oC- - 250

V

GS

Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics

V

GS(TH)

r

DS(ON)

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

I

Drain to Source On Resistance

= 44A, V

D

= 21A, VGS = 6V, - 0.031 0.047

D

I

=44A, VGS=10V, TC=175oC - 0.054 0.068

D

= 10V - 0.024 0.028

GS

Dynamic Characteristics

C C C Q Q Q Q Q

ISS OSS RSS

g(TOT) g(TH) gs gs2 gd

Input Capacitance Output Capacitance - 247 - pF Reverse Transfer Capacitance - 62 - pF

= 25V, VGS = 0V,

V

DS

f = 1MHz

Total G ate Ch arg e at 10 V VGS = 0V to 10V Threshold Gate Charge VGS = 0V to 2V - 3 4.5 nC Gate to Source Gate Charge - 8.6 - nC Gate Charge Threshold to Plateau - 5.6 - nC

V

DD

I

= 44A

D

I

= 1.0m A

g

= 50V

Gate to Drain “Miller” Charge - 5.6 - nC

-1710- pF

-2436nC

µA

ΩI

Resistive Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time Turn-On Delay Time - 11 - ns Rise Time - 59 - ns T u rn-Off Delay Time - 26 - ns Fall Time - 44 - ns Turn-Off Time - - 104 ns

Drain-Source Diode Characteristics

V

SD

t

rr

Q

RR

Notes: 1: Starting T 2: Pulse Width = 100s

Source to Drain Di ode Voltage Reverse Recovery Time ISD = 44A, dISD/dt =100A/µs- - 52ns

Reverse Recovery Charge ISD = 44A, dISD/dt =100A/µs- - 80nC

= 25°C, L = 0.6mH, IAS = 20A.

J

(VGS = 10V)

V

DD

V

GS

I

SD

I

SD

--104ns

= 50V, ID = 44A = 10V, RGS = 11.0Ω

= 44A - - 1 .25 V

= 21A - - 1.0 V

FDD3672

Typical Characteristics T

= 25°C unless otherwise noted

C

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

125

TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

150

50

V

= 10V

GS

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

25 50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

Figure 2. Maximum Continuous Drain Curr ent vs

Case Temperature

, NORMALIZED Z

, PEAK CURRENT (A) I

θJC

DM

THERMAL IMPEDANCE

500

100

30

0.1

0.01

10

-5

10

VGS = 10V

-5

SINGLE PULSE

-4

10

-3

10

-2

10

NOTES: DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

-4

10

-3

10

t, PULSE WIDTH (s)

-2

10

-1

10

TC = 25oC

FOR TEMPERATURES ABOVE 25 CURRENT AS FOLLOWS:

I = I

P

DM

1/t2

x R

θJC

0

10

o

25

0

10

t

1

t

2

+ T

θJC

C

C DERATE PEAK

175 - T

C

150

1

10

1

10

Figure 4. Peak Current Capability

Typical Characteristics T

= 25°C unless otherwise noted

C

FDD3672

300

If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0 t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

100

10

, AVALANCHE CURRENT (A)

AS

I

STARTING TJ = 150oC

1

0.001 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 5. Unclamped Inductive Switching

Capability

80

TC = 25oC

60

40

, DRAIN CURRENT (A)

20

D

I

0

0 0.5 1.0 1.5 2.0 2.5 3.0

VGS = 10V

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

VGS = 5V

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 7V

VGS = 6V

80

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX V

= 15V

DD

60

40

TJ = 25oC

20

, DRAIN CURRENT (A)

D

I

0

10

3.5 4.0 4.5 5.0 5.5 6.0 6.5 VGS, GATE TO SOURCE VOLTAGE (V)

TJ = 175oC

TJ = -55oC

Figure 6. Transfer Characteristics

40

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

35

30

25

20

15

DRAIN TO SOURCE ON RESISTANCE (m Ω)

0 1020304050

VGS = 6V

VGS = 10V

I

, DRAIN CURRENT (A)

D

Figure 7. Saturation Characte risti cs Figure 8. Drain to Sou rce On Resistanc e vs Dr ain

Current

2.5

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 44A

Figure 9. Normalized Drain to Source On

Resistance vs Junction Temperature

1.2 VGS = VDS, ID = 250µA

1.0

0.8

NORMALIZED GATE

0.6

THRESHOLD VOLTAGE

0.4

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

Figure 10. Normalized Gat e Threshol d Voltage vs

Junction Temperatur e

FDD3672

Typical Characteristics T

1.2 ID = 250µA

1.1

1.0

BREAKDOWN VOLTA GE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200 T

, JUNCTION TEMPERATURE (oC)

J

= 25°C unless otherwise noted

C

Figure 11. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 50V

8

6

3000

C

= CGS + C

1000

C

≅ C

+ C

OSS

DS

GD

C

= C

RSS

100

C, CAPACITANCE (pF)

10

0.1 1 10 100

GD

V

= 0V, f = 1MHz

GS

VDS, DRAIN TO SOURCE VOLTAGE (V)

ISS

GD

Figure 12. Capacitance vs Drain to Source

Voltage

4

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 5 10 15 20 25

Qg, GATE CHARGE (nC)

WAVEFORMS IN DESCENDING ORDER:

ID = 44A I

= 21A

D

Figure 13. Gate Charge Waveforms for Constant Gate Currents

Test Circuits and Waveforms

FDD3672

BV

DSS

t

P

V

DS

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

V

DS

L

I

AS

R

AS

G

+

V

DD

-

DUT

t

0V

P

I

AS

0.01Ω

0

t

AV

Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Wavef orm s

V

I

g(REF)

DS

L

V

GS

+

V

DD

-

DUT

Q

V

0

g(TH)

I

g(REF)

0

DD

V

GS

V

= 2V

GS

Q

gs2

Q

gs

Q

g(TOT)

V

DS

Q

gd

V

DD

V

= 10V

GS

Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

90%

PULSE WIDTH

50%50%

Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maxi mum al lowab le de vice p ower di ssip ation, P application. Therefore the application’s ambient temperature, T must be reviewed to ensure that T Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

θJA

, in an

DM

(oC/W)

serve s as the basis for establ ishing the rating of the part.

P

DM

TJMTA–()

----------------- ------------=

R

θJA

(EQ. 1)

125

100

C/W)

o

(

75

θJA

R

50

R

= 33.32+ 23.84/(0.268+Area) EQ.2

θJA

R

= 33.32+ 154/(1.73+Area) EQ.3

θJA

FDD3672

In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power d issipati on rating s. Precise d etermin ation of P comple x and influenced by many factors:

DM

is

1. Mou nting pad area ont o which the device is attached and whet her the re is copp er on one s ide or both side s of the board.

2. The number of copper layers and the thickness of the board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For no n steady state applic ations, th e pulse widt h, the duty cycle and the transient thermal response of the part, the boa rd and the environment they are in.

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 20 defines the R copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 board w ith 1oz co pp er af ter 1000 secon ds of stea dy st ate pow er w ith n o air flow . Th is gr aph prov ides the necessary inf ormation for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice t hermal model or manu ally utilizing the no rmalized maximum transient thermal impedance curve.

25

0.01 0.1 1 10 (0.645) (6.45) (64.5)(0.0645)

AREA, TOP COPPER AREA in2 (cm2)

Figure 20. Thermal Resistance vs Mounting

Pad Area

Therma l resi stances correspondi ng to other copper are as can be obtained from Figure 20 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inch es squ are and equ ation 3 is for area in cent imeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads.

23.84

33.32

=

R

θJA

33.32

=

R

θJA

-------------------------------------+

0.268 Area+()

Area in Inches Squared

154

----------------------------------+

1.73 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

PSPICE Electrical Model

.SUBCKT FDD3672 2 1 3 ; rev May 2002 CA 12 8 5.8e -10 Cb 15 14 6.8e-10 Cin 6 8 1.6e-9

Dbod y 7 5 DbodyMOD Dbreak 5 11 Db reakMOD Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 105 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1

It 8 17 1 Lgat e 1 9 9.56e-9

Ldrain 2 5 1.0e -9 Lsource 3 7 4.45e-9

RLgate 1 9 95.6 RLdr ai n 2 5 10 RLsource 3 7 44.5

Mmed 16 6 8 8 M m edMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 6.0e-3 Rgate 9 20 1.5 RSLC1 5 51 RSL CM OD 1.0e-6 RSLC2 5 50 1.0e 3 Rsource 8 7 RsourceMOD 9.5e-3 Rvthres 22 8 RvthresMO D 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BM OD S2a 6 15 14 13 S2AM OD S2b 13 15 14 13 S2BM OD

Vbat 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

18 22

20

S1A

12

13

8

S1B

EGS EDS

FDD3672

17 18

-

7

RVTEMP 19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

DPLCAP

10

RSLC2

6

8

EVTHRES

+

6

-

S2A

14 13

S2B

13

+

6 8

-

5

RSLC1

51

+

5

ESLC

51

50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5 8

-

MMED

8

DBREAK

11

+

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

ESLC 51 50 VALUE={(V(5,51)/ABS(V (5, 51)))*(PWR (V(5,51)/(1e-6*98),3 ))} .MODEL DbodyMOD D (IS=1.0E-11 N=1.05 RS=3.7e-3 TRS1=2.5e-3 TRS2=1.0e-6

+ CJO=1.2e-9 M= 0.58 TT=3.75e -8 X T I=4.0) .MODEL Db reakMOD D (RS= 15 T RS 1=4.0e-3 TRS2=-5.0e-6) .MODEL DplcapMOD D (CJO=3.8e-10 IS=1.0e-30 N=10 M=0.60)

.MODEL MmedMOD NMOS (VTO=3.6 KP=3 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=1.5) .MODEL MstroMOD NMOS (VTO=4.3 KP=59 IS=1e-30 N=10 TOX=1 L= 1u W=1u) .MODEL Mwe akMOD NMOS (VTO=3.09 KP=0. 05 IS=1e-30 N=10 T OX=1 L=1u W=1u RG=15 RS=0.1)

.MODEL Rb reakMOD RES (T C1=9.0e-4 TC2 =-1.0e-7) .MODEL RdrainMOD RES (TC1=11.0e-3 TC2=5.0e-5) .MODEL RSLCMOD RES (TC1=3.0e-3 TC2=1.0e-6) .MODEL RsourceMOD RES (TC 1=4.0e-3 TC2=1 .0e-6) .MODEL RvthresMOD RES (T C1=-3.5e-3 TC 2=-1.5e-5) .MODEL RvtempMOD RES (TC1=-4.3e-3 TC2=1.5e-6)

.MODEL S1AMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 5. 0 VOFF =-3 .5 ) .MODEL S1BMOD VSWITC H (RON =1e - 5 ROFF= 0. 1 VON=- 3. 5 VOFF =-5 .0 ) .MODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 0.5 VO FF=0.3) .MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= 0 .3 VOFF= -0.5)

.ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, wri t ten by William J. Hepp and C. Frank Wheatley.

SABER Electrical Model

REV May 2002 template FDD 3672 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.0e-11,nl=1.05,rs=3.7e-3,trs1=2.5e-3,trs2=1.0e-6,cjo=1.2e-9,m=0.58,tt=3.75e-8,xti=4.0) dp..model dbreakmod = (rs=15 ,t rs 1=4.0e-3,tr s2=-5.0e-6) dp..model dplcapmod = (cjo=3.8e-10,isl=10.0e-30,nl=10,m=0.60) m..model mmedmod = (type=_n,vto=3.6,kp=3,is=1e-40, tox=1) m..model mstrongmod = (type=_n,vto=4.3,kp=59,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.09,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0.1, von=-5.0,voff =-3.5) sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0.1, von=-3.5,voff =-5.0)

DPLCAP

10

sw_vcsp.. mo del s2amod = (ron=1e-5,roff=0.1, von=-0.5,voff= 0. 3) sw_vcsp.. mo del s2bmod = (ron=1e-5,roff=0.1, von=0.3,voff= -0. 5) c.ca n12 n8 = 5.8e -10

RSLC2

c.cb n15 n14 = 6.8e-10 c.cin n6 n8 = 1.6e -9

dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplca pm od

spe.ebreak n11 n7 n17 n18 = 105

GATE

spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1

LGATE

1

RLGATE

RGATE

9

ESG

EVTEMP +

18 22

20

-

6 8

EVTHRES

+

6

-

spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1 l.lgate n1 n9 = 95 .6 e-9

l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 4.45e-9

res.rlgate n1 n9 = 9.56 res.rldrai n n2 n5 = 10 res.rlsource n3 n7 = 44.5

CA

S1A

12

S1B

S2A

13

14

8

13

S2B

13

+

6

EGS EDS

8

-

m.mmed n16 n6 n8 n8 = m odel=mmedm od, l= 1u, w=1u m.mstrong n16 n6 n8 n8 = model=ms trongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mwea kmod, l=1u, w=1u

5

RSLC1

51

ISCL

8

MMED

DBREAK

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

+

50 RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

14

+

5 8

-

17 18

7

RVTEMP 19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

FDD3672

res.rbreak n17 n18 = 1, tc1=9.0e-4,tc2=-1.0e -7 res.rdrain n50 n16 = 6.0e-3, tc1=11.0e-3,tc2=5.0e-5 res.rgate n9 n20 = 1.5 res.rslc1 n5 n51 = 1.0e-6, tc1=3. 0e-3,tc2=1. 0e-6 res.rslc2 n5 n50 = 1.0e3 res.rsour ce n8 n7 = 9.5e-3, tc1=4.0e-3,tc2=1.0e-6 res.rvthres n22 n8 = 1, tc1=-3.5e-3,tc2=-1.5e-5 res.rvtemp n18 n19 = 1, tc1=-4.3e-3,tc2=1.5e-6 sw_vcsp.s1 a n6 n12 n13 n8 = model= s1amod sw_vcsp.s1 b n13 n12 n13 n8 = model =s1bmod sw_vcsp.s2 a n6 n15 n14 n13 = model =s2amod sw_vcsp.s2 b n13 n15 n14 n13 = model =s2bmod

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5, n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/98))** 3) ) }

FDD3672

SPICE Thermal Model

REV May 2002 FDD3672 CTHERM1 TH 6 3.2e-3

CTHERM2 6 5 3. 3e-3 CTHERM3 5 4 3. 4e-3 CTHERM4 4 3 3. 5e-3 CTHERM5 3 2 6. 4e-3 CTHERM6 2 TL 1.9e-2

RTHERM1 TH 6 5.5e-4 RTHERM2 6 5 5. 0e-3 RTHERM3 5 4 4. 5e-2 RTHERM4 4 3 10.5e-2 RTHERM5 3 2 3. 4e-1 RTHERM6 2 TL 3.5e-1

SABER Thermal Model

SABER therm a l model FDD3672 template thermal_model th tl thermal_ c th , tl { cctherm.ctherm1 th 6 =3.2e-3 ctherm.ctherm2 6 5 =3.3e-3 ctherm.ctherm3 5 4 =3.4e-3 ctherm.ctherm4 4 3 =3.5e-3 ctherm.ctherm5 3 2 =6.4e-3 ctherm.ctherm6 2 tl =1.9e-2

rtherm.rtherm1 th 6 =5.5e-4 rtherm.rt herm2 6 5 =5.0e-3 rtherm.rt herm3 5 4 =4.5e-2 rtherm.rt he rm4 4 3 =10. 5 e-2 rtherm.rt herm5 3 2 =3.4e-1 rthe r m.rtherm6 2 tl =3.5 e-1 }

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

RTHERM6

2

CTHERM6

CASE

tl

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhausti ve list of all such trademarks.

ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DOME™ EcoSPARK™

2

E

CMOS™ EnSigna™ FACT™ FACT Quiet Series™

®

FAST FASTr™

FRFET™ GlobalOptoisolator™ GTO™ HiSeC™

2

I

C™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC

®

OPTOPLANAR™

PACMAN™ POP™ Power247™ PowerTrench

®

QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHE R SMART START™ SPM™ Stealth™

SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET

®

VCX™

®

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR D ESIGN. FAIRCHILD DOES NOT ASSUME A NY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) supp or t or s us ta in l if e, or ( c ) w hos e fa il ure to pe rf or m when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasona bl y ex pe cted to cau se t he fa il u re of th e lif e su pp ort device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Inf or m ation Form a t ive or In

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identificat ion Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Production This datasheet contains specifications on a product

This datasheet contains the design specifications for product development. Specifi cations may change in any manner without notice.

supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Semiconductor reserves the right to make changes at any time without notice in order to improve design.

that has been disc ontinued by Fairchild se miconductor. The datasheet is printed f or refe rence information only.

Rev. H7