Datasheet fdd2572_f085 Datasheet

FDD2572_F085

N-Channel PowerTrench® MOSFET
150V, 29A, 54mΩ

FDD2572_F085 N-Channel PowerTrench

S

November 2008

Features

•r

•Q

• Low Miller Charge

•Low Q

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

• RoHS Compliant

Formerly developmental type 82860

= 45mΩ (Typ.), V

DS(ON)

(tot) = 26nC (Typ.), V

g

Body Diode

RR

GS

= 10V

GS

GATE

SOURCE

= 10V, ID = 9A

DRAIN

(FLANGE)

Applications

• DC/DC converters and Off-Line UPS

• Distributed Power Architectures and VRMs

• Primary Switch for 24V and 48V Systems

• High Voltage Synchronous Rect ifier

• Direct Injection / Diesel Injection Systems

• 42V Automotiv e Load Cont rol

• Electronic Valve Train Systems

D

G

TO-252AA

FDD SERIES

MOSFET Maximum Ratings T

= 25°C unless ot herwise noted

C

Symbol Parameter Ratings Units

V

DSS

V

GS

Drain to Source Voltage 150 V
Gate to Source Voltage ±20 V
Drain Cur re nt
Continuous (T

I

D

Continuous (T
Continuous (T

= 25oC, VGS = 10V)

C

= 100oC, VGS = 10V) 20 A

C

= 25oC, VGS = 10V, R

amb

= 52oC/W) 4

θJA

Pulsed Figure 4 A

E

AS

P

D

T

, T

J

STG

Single Pulse Avalanche Energy (Note 1) 36 mJ
Power dissipation 135 W
Derate above 25

o

C0.9W/

Operating an d Stora ge Temper ature -55 t o 175

S

29 A

o

C

o

C

Thermal Charact eristi cs

R

θJC

R

θJA

R

θJA

This product ha s been des igned to me et the e xtr eme test c ondit ions and environme nt demande d by the automot ive indus t ry. For a

All Fairchild Semiconductor pr oducts are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

Thermal Resistance Junction to Case TO-2 52 1.11
Thermal Resistance Junction to Ambient TO-252 100
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad ar ea 52

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

certification.

o

C/W

o

C/W

o

C/W

®

MOSFET

©2008 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com
FDD2572_F085 Rev.A

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

2 FDD2572_F085 TO-252AA 330mm 16mm 2500 units

FDD257

Electrical Characteristics

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

B

VDSS

I

DSS

I

GSS

On Characteristics

V

GS(TH)

r

DS(ON)

Drain t o Source Br eakdown V oltage ID = 250µA, VGS = 0V 150 - - V
Zero Gate Voltage Drain Current
Gate to Source Leakage Current VGS = ±20V - - ±100 nA

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

Drain to Source On Resistance

TC = 25°C unless otherwise noted

V

= 120V - - 1

DS

= 0V TC = 150

V

GS

=9A, VGS=10V - 0.045 0.054

I

D

= 4A, VGS = 6V, - 0.050 0.075

D

I

=9A, VGS=10V, TC=175oC - 0.126 0.146

D

o

--250

FDD2572_F085 N-Channel PowerTrench

µA

ΩI

Dynamic Characteristics

C
C
C
Q
Q
Q
Q
Q

ISS
OSS
RSS

g(TOT)
g(TH)
gs
gs2
gd

Input Capacitance
Output Capacitance - 183 - pF
Reverse Transfer Capacitance - 40 - pF
Total Gate Ch arg e at 10V VGS = 0V to 10V
Threshold Gate Charge VGS = 0V to 2V - 3.3 4.3 nC
Gate to Source Gate Charge - 8 - nC
Gate Charge Thr eshold to Plateau - 5 - nC
Gate to Drain “Miller” Charge - 6 - nC

Resistive Switching Characteristics

t

ON

t

d(ON)

t

r

t

d(OFF)

t

f

t

OFF

Turn-On Time
Turn-On Delay Time - 11 - ns
Rise Time - 14 - ns
T u rn-Off Delay Time - 31 - ns
Fall Time - 14 - ns
Turn-Off Time - - 66 ns

Drain-Source Diode Characteristics

V

SD

t

rr

Q

RR

Notes:
1: Starting T

Source to Drain Diode Voltage
Reverse Recovery Time ISD = 9A, dISD/dt =100A/µs- -74ns

Reverse Re cove red Charge ISD = 9A, dISD/dt =100A/µs - - 169 nC

= 25°C, L = 0.2mH, IAS = 19A.

J

V

DS

f = 1MHz

(VGS = 10V)

V

DD

V

GS

I

SD

I

SD

= 25V, VGS = 0V,

-1770- pF

-2634nC

= 75V

V

DD

= 9A

I

D

= 1.0m A

I

g

--36ns

= 75V, ID = 9A
= 10V, RGS = 11.0Ω

= 9A - - 1.25 V

= 4A - - 1.0 V

®

MOSFET

FDD2572_F085 Rev.A 2 www.fairchildsemi.com

FDD2572_F085 N-Channel PowerTrench

Typical Characteristics T

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0255075100 175

TC, CASE TEMPERATURE (oC)

= 25°C unless otherwise noted

C

125

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

2.0

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.02

0.01

-5

10

-4

10

SINGLE PULSE

, NORMALIZED
Z

1.0

0.1

θJC

THERMAL IMPEDANCE

0.01

40

V

= 10V

GS

35

30

25

20

15

, DRAIN CURRENT (A)

10

D

I

5

150

0

25 50 75 100 125 150 175

Figure 2. Maximum Continuous Drain Curr ent vs

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

TC, CASE TEMPERATURE (oC)

Case Temperature

P

DM

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

θJC

10

1/t2

x R

0

®

MOSFET

t

1

t

2

+ T

θJC

C

1

10

Figure 3. Normalized Maximum Transient Thermal Impedance

500

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

100

, PEAK CURRENT (A)

DM

I

VGS = 10V

20

-5

10

-4

10

-3

10

t, PULSE WIDT H (s)

-2

10

-1

10

TC = 25oC
FOR TEMPERATURES

o

ABOVE 25
CURRENT AS FOLLOWS:

I = I

25

C DERATE PEAK

175 - T

150

0

10

C

1

10

Figure 4. Peak Current Capability

FDD2572_F085 Rev.A 3 www.fairchildsemi.com

Typical Characteristics T

= 25°C unless otherwise noted

C

FDD2572_F085 N-Channel PowerTrench

1000

10µs

100

10

OPERATION IN THIS

AREA MAY BE

, DRAIN CURRENT (A)

D

I

LIMITED BY r

1

SINGLE PULSE
TJ = MAX R ATED

T

= 25oC

C

0.1
1 10 100

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

100µs

1ms

10ms

DC

Figure 5. Forward Bias Safe Operating Area

60

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

50

V

= 15V

DD

40

30

TJ = 175oC

100

STARTING TJ = 25oC

10

STARTING TJ = 150oC

1

If R = 0

, AVALANCHE CURRENT (A)

200

tAV = (L)(IAS)/(1.3*RATED BV

AS

I

If R ≠ 0
t

= (L/R)ln[( IAS*R)/(1.3*RATED BV

AV

0.1

0.001 0.01 0.1 1
tAV, TIME IN AVALANCHE (ms)

DSS

- VDD)

DSS

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclamped Inductive Switching

Capability

60

TC = 25oC

50

40

30

VGS = 10V

VGS = 6V

- VDD) +1]

®

MOSFET

VGS = 7V

20

, DRAIN CURRENT (A)

D

I

10

0

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

TJ = 25oC

TJ = -55oC

VGS, GATE TO SOURCE VOLTAGE (V)

Figure 7. Transfer Charact eristics Figure 8. Saturation Characteristics

60

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

55

50

45

40

DRAIN TO SOURCE ON RESISTANCE (m Ω)

0102030

VGS = 6V

VGS = 10V

I

, DRAIN CURRENT (A)

D

Figure 9. Drain to So urce On Resistanc e v s Drai n

Current

20

, DRAIN CURRENT (A)

D

I

10

0

012345

3.0

2.5

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

TJ, JUNCTION TEMPERATURE (oC)

VGS = 5V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = 10V, ID =9A

Figure 10. Normalized Drain to Source On

Resistance vs Junction Temperature

FDD2572_F085 Rev.A 4 www.fairchildsemi.com

Typical Characteristics T

= 25°C unless otherwise noted

C

FDD2572_F085 N-Channel PowerTrench

1.4
VGS = VDS, ID = 250µA

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

0.4

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

Figure 11. Normalized G ate Threshol d Voltage vs

Junction Temperature

1000

C

= CGS + C

1000

100

ISS

C

≅ C

+ C

OSS

DS

GD

C

= C

RSS

GD

GD

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200
T

, JUNCTION TEMPERATURE (oC)

J

Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

10

VDD = 75V

8

6

4

®

MOSFET

C, CAPACITANCE (pF)

V

= 0V, f = 1MHz

GS

10

0.1 1 10 150
VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 13. Capacitance vs Drain to Sour ce

Voltage

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 5 10 15 20 25 30

Qg, GATE CHARGE (nC)

WAVEFORMS IN
DESCENDING ORDER:

ID = 9A
I

= 4A

D

Figure 14. Gat e Charge Waveforms for Constant

Gate Currents

FDD2572_F085 Rev. A 5 www.fairchildsemi.com

Test Circuits and Waveforms

FDD2572_F085 N-Channel PowerTrench

BV

DSS

t

P

V

DS

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

V

DS

L

I

AS

R

AS

G

+

V

DD

-

DUT

t

0V

P

I

AS

0.01Ω

0

t

AV

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

V

I

g(REF)

DS

L

V

GS

+

V

DD

-

DUT

Q

V

0

g(TH)

I

g(REF)

0

DD

V

GS

V

= 2V

GS

Q

gs2

Q

gs

Q

g(TOT)

V

DS

Q

gd

V

DD

®

MOSFET

V

= 10V

GS

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

V

GS

10%

t

d(ON)

90%

t

ON

t

r

t

d(OFF)

t

OFF

t

f

90%

10%

10%

90%

PULSE WIDTH

50%50%

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

FDD2572_F085 Rev. A 6 www.fairchildsemi.com

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maxi mum al lowab le de vice p ower di ssip atio n, P
application. Therefore the application’s ambient
temperature, T
must be reviewed to ensure that T
Equation 1 mathematically represents the relationship and

(oC), and th ermal res istance R

A

is never exceeded.

JM

DM

θJA

, in an

(oC/W)

serve s as the basis for est ablishing the rating of the part.

P

DM

TJMTA–()

----------------- ------------=

R

θJA

(EQ. 1)

125

100

C/W)

o

(

75

θJA

R

50

R

= 33.32+ 23.84/(0.268+Area) EQ.2

θJA

R

= 33.32+ 154/(1.73+Area) EQ.3

θJA

FDD2572_F085 N-Channel PowerTrench

In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power d issipati on rating s. Precise d etermin ation of P
comple x and influenced by many factors:

DM

is

1. Mounting pad area onto which the dev ice is a ttached and
whethe r the re is copp er on one s ide or both side s of the
board.

2. The number of copper layers and the thickness of the
board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air f low and board orientation.

6. For no n steady st ate applic ations, the pulse widt h, the
duty cycle and the tran sient thermal response of the part,
the boa rd and the enviro nment they are in.

Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
copper (component side) area. This is for a horizontally

for the device as a function of the top

θJA

positi on ed FR-4 board w ith 1oz c o pp er af t er 1000 se c onds
of stea dy st ate powe r w ith n o air flow . Th is gr aph prov ides
the necessary information for calc ulation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice t hermal model or manu ally utilizin g the normal ized
maximum transient thermal impedance curve.

25

0.01 0.1 1 10
(0.645) (6.45) (64.5)(0.0645)

AREA, TOP COPPER AREA in2 (cm2)

Figure 21. Thermal Resistance vs Mounting

Pad Area

®

MOSFET

Therma l resist ances corresp onding to other co pper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeter
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.

23.84

R

R

FDD2572_F085 Rev. A 7 www.fairchildsemi.com

θJA

θJA

=

=

33.32

33.32

-------------------------------------+

0.268 Area+()

Area in Inches Squared

154

----------------------------------+

1.73 Area+()

Area in Centimeters Squared

(EQ. 2)

(EQ. 3)

PSPICE Electrical Model

.SUBCKT FDD2572 2 1 3 ; rev April 2002
CA 12 8 5.5e -10
Cb 15 14 7.4e-10
Cin 6 8 1.7e-9

Dbod y 7 5 Dbody M OD
Dbreak 5 11 D breakMOD
Dplcap 10 5 DplcapMOD

Ebreak 11 7 17 18 160
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1

It 8 17 1
Lgat e 1 9 1.21e -9

Ldrain 2 5 1.0e -9
Lsource 3 7 4.45e-9

RLgate 1 9 12.1
RLdr ai n 2 5 10
RLsource 3 7 44.5

Mmed 16 6 8 8 M m edMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD

Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 35e-3
Rgate 9 20 1.6
RSLC1 5 51 RSL CM OD 1.0e-6
RSLC2 5 50 1.0e 3
Rsource 8 7 RsourceMOD 3.0e-3
Rvthres 22 8 RvthresMO D 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BM OD
S2a 6 15 14 13 S2AM OD
S2b 13 15 14 13 S2BM OD

Vbat 22 19 DC 1

GATE

1

LGATE

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

18
22

20

S1A

12

13

8

S1B

EGS EDS

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

-

S2A

14
13

S2B

13

+

+

6
8

-

-

5

RSLC1

51

+

5

ESLC

51

­50

RDRAIN

16

21

-

19

8

MMED

MSTRO

CIN

15

CB

8

14

+

5
8

-

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

FDD2572_F085 N-Channel PowerTrench

LDRAIN

RLDRAIN

11

+

17

DBODY

18

-

LSOURCE

7

RLSOURCE

RVTEMP
19

­VBAT

+

22

DRAIN

2

SOURCE

3

®

MOSFET

ESLC 51 50 VALUE={(V(5,51)/ABS(V (5,51)))*(PW R(V(5,51)/ (1e-6*52),3))}
.MODEL DbodyMOD D (IS=6.0E-11 N=1.14 RS=3.9e-3 TRS1=3.5e-3 TRS2=3.0e-6

+ CJO=1.1e-9 M= 0.63 TT=6.2e- 8 X T I=4.5)
.MODEL DbreakMOD D (RS=10 TRS1=5.0e-3 TRS2=-5.0e-6)
.MODEL DplcapMOD D (CJO=3.5e-10 IS=1.0e-30 N=10 M=0.65)

.MODEL MmedMOD NMOS (VTO= 3.55 KP=3 IS=1e-4 0 N=10 TOX=1 L=1u W=1u RG=1.6)
.MODEL MstroMOD NMOS (VTO =4. 0 KP=25 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL Mwe akMOD NMOS (VTO=2.95 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=16 RS=0.1)

.MODEL Rb reakMOD RES (T C1=1.15e-3 TC 2=-9.5e-7)
.MODEL Rd rai nMOD RES (TC 1=9.0e-3 TC2=2. 5e-5)
.MODEL RSLCMOD RES (TC1=3.0e-3 TC2=2.5e-6)
.MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1.0e-6)
.MODEL RvthresMOD RES (T C1=-4.1e-3 TC2=-1.0e-5)
.MODEL RvtempMOD RES (T C1=-4.0e-3 TC 2=1.0e-6)

.MODEL S1AMOD VSWITC H (RON =1e- 5 ROF F= 0. 1 VON=- 5. 0 VOFF =-3 .5 )
.MODEL S1BMOD VSWITC H (RON =1e- 5 ROF F= 0. 1 VON=- 3. 5 VOFF =-5 .0 )
.MODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 0. 5 VOFF =0. 3)
.MODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= 0 .3 VOFF= -0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Rec o rds, 1991, writ ten by William J. Hepp and C. Frank
Wheatley.

FDD2572_F085 Rev. A 8 www.fairchildsemi.com

SABER Electrical Model

REV April 2002
ttemplate F DD2572 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=6.0e-11,nl=1.14,rs=3.9e-3,trs1=3.5e-3,trs2=3.0e-6,cjo=1.1e-9,m=0.63,tt=6.2e-8,xti=4.5)
dp..model dbreakmod = (rs=10 ,t rs1=5.0e-3, trs2=-5.0e-6)
dp..model dplcapmod = (cjo=3.5e-10,isl=10.0e-30,nl=10,m=0.65)
m..model mmedmod = (type=_n,vto=3.55,kp=3,is=1e-40, tox=1)
m..model mstrongmod = (type=_n,vto=4.0,kp=25,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.95,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp.. mo del s1amod = (ron=1e-5,roff=0.1, von=-5.0,voff =-3.5)
sw_vcsp.. mo del s1bmod = (ron=1e-5,roff=0.1, von=-3.5,voff =-5.0)
sw_vcsp.. mo del s2amod = (ron=1e-5,roff=0.1, von=-0.5,voff =0.3)
sw_vcsp.. mo del s2bmod = (ron=1e-5,roff=0.1, von=0.3,voff=-0.5)
c.ca n12 n8 = 5. 5e-10
c.cb n15 n14 = 7.4e-10
c.cin n6 n8 = 1.7e -9

dp.dbody n7 n5 = model=dbodym od
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplca pm od

spe.ebreak n11 n7 n17 n18 = 160

GATE

spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1

LGATE

1

RLGATE

9

RGATE

ESG

EVTEMP
+

18
22

20

spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1

i.it n8 n17 = 1

S1A

12

l.lgate n1 n9 = 1.21e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 4.45e-9

S1B

CA

res.rlgate n1 n9 = 12.1
res.rldrai n n2 n5 = 10
res.rlsource n3 n7 = 44.5

m.mmed n16 n6 n8 n8 = m odel=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mwea kmod, l=1u, w=1u

DPLCAP

10

RSLC2

­6

8

EVTHRES

+

+

19

6

-

S2A

13

14

8

13

S2B

13

+

+

6

EGS EDS

8

-

-

5

RSLC1

51

ISCL

8

MMED

8

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

RVTHRES

50
RDRAIN

16

21

-

8

MSTRO

CIN

15

CB

14

+

5
8

-

RLDRAIN

DBODY

+

17
18

LSOURCE

­7

RLSOURCE

RVTEMP
19

­VBAT

+

22

LDRAIN

DRAIN

2

SOURCE

3

FDD2572_F085 N-Channel PowerTrench

®

MOSFET

res.rbreak n17 n18 = 1, tc1=1.15e -3,tc2=-9.5 e-7
res.rdrain n50 n16 = 35e-3, tc1=9.0e-3,tc2=2 .5e-5
res.rgat e n9 n20 = 1. 6
res.rslc1 n5 n51 = 1.0e-6, tc1=3. 0e-3,tc2=2. 5e-6
res.rslc2 n5 n50 = 1.0e3
res.rsour ce n8 n7 = 3.0e-3, tc1=4.0e-3,tc2=1 .0 e-6
res.rvthres n22 n8 = 1, tc1=-4.1e-3,tc2=-1.0e-5
res.rvtemp n18 n19 = 1, tc1=-4.0e-3,tc2=1.0e-6
sw_vcsp.s1 a n6 n12 n13 n8 = model= s1amod
sw_vcsp.s1 b n13 n12 n13 n8 = model =s1bmod
sw_vcsp.s2 a n6 n15 n14 n13 = model =s2amod
sw_vcsp.s2 b n13 n15 n14 n13 = model =s2bmod

v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n 51))))*((abs (v(n5,n51)*1e6/52))** 3))}
}

FDD2572_F085 Rev. A 9 www.fairchildsemi.com

FDD2572_F085 N-Channel PowerTrench

SPICE Thermal Model

REV 26 April 2002
FDD2572
CTHERM1 TH 6 3.8e-3

CTHERM2 6 5 4. 0e-3
CTHERM3 5 4 4. 2e-3
CTHERM4 4 3 4. 3e-3
CTHERM5 3 2 8. 5e-3
CTHERM6 2 TL 3.0e-2

RTHERM1 TH 6 5.5e-4
RTHERM2 6 5 5. 0e-3
RTHERM3 5 4 4. 5e-2
RTHERM4 4 3 10.5e-2
RTHERM5 3 2 3. 7e-1
RTHERM6 2 TL 3.8e-1

SABER Thermal Model

SABER therm al m odel F DD2572
template thermal_model th tl
thermal_ c th , tl
{
ctherm.c th erm 1 th 6 =3.8e -3
ctherm.ctherm2 6 5 =4.0e-3
ctherm.ctherm3 5 4 =4.2e-3
ctherm.ctherm4 4 3 =4.3e-3
ctherm.ctherm5 3 2 =8.5e-3
ctherm.ctherm6 2 tl =3.0e-2

rtherm.rtherm1 th 6 =5.5e-4
rtherm.rther m 2 6 5 =5.0e -3
rtherm.rther m 3 5 4 =4.5e -2
rtherm.rther m 4 4 3 =10.5 e- 2
rtherm.rther m 5 3 2 =3.7e -1
rtherm.rther m 6 2 tl =3.8e -1
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

®

MOSFET

CTHERM4

3

CTHERM5

RTHERM6

2

CTHERM6

CASE

tl

FDD2572_F085 Rev. A 10 www.fairchildsemi.com

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FDD2572_F085 N-Channel PowerTrench

®

MOSFET

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PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative / In Design

Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

FDD2572_F085 Rev.A 11

Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.

Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.

Rev. I37

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