Datasheet FDC855N Datasheet (Fairchild)

tm

FDC855N

Single N-Channel, Logic Level, PowerTrench® MOSFET
30V, 6.1A, 27mΩ

Features

 Max r
 Max r
 SuperSOTTM -6 package: small footprint (72% smaller than

standard SO-8; low profile (1mm thick).

 RoHS Compliant

= 27mΩ at V

DS(on)

= 36mΩ at V

DS(on)

SuperSOT

TM

GS

GS

D

-6

= 10V, ID = 6.1A
= 4.5V, ID = 5.3A

S

D

G

D

D

General Description

This N-Channel Logic Level MOSFET is an efficient solution for
low voltage and battery powered applications. Utilizing Fairchild
Semiconductor’s advanced PowerTrench
possesses minimized on-state resistance to optimize the power
consumption. They are ideal for applications where in-line power
loss is critical.

Application

 Power Management in Notebook, Hard Disk Drive

D

D

G

January 2008

®

process, this device

D

D

S

FDC855N N-Channel, Logic Level, PowerTrench

®

MOSFET

Pin 1

MOSFET Maximum Ratings T

Symbol Parameter Ratings Units

V

DS

V

GS

I

D

P

D

, T

T

J

STG

Drain to Source Voltage 30 V
Gate to Source Voltage ±20 V
Drain Current -Continuous TA = 25°C (Note 1a) 6.1

-Pulsed 20
Power Dissipation (Steady S t ate) (Note 1a) 1.6
Power Dissipation (Steady S t ate) (Note 1b) 0.8
Operating and Storage Junction Temperature Range -55 to +150 °C

= 25°C unless otherwise noted

A

Thermal Characteristics

R

θJC

R

θJA

Thermal Resistance, Junction to Case (Note 1) 30
Thermal Resistance, Junction to Ambient (Note 1a) 78

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

.855 FDC855N SuperSOT-6 7” 8 mm 3000 units

A

W

°C/W

©2008 Fairchild Semiconductor Corporation
FDC855N Rev.C

1

www.fairchildsemi.com

Electrical Characteristics T

= 25°C unless otherwise noted

J

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

BV

∆BV
∆T

I

DSS

I

GSS

DSS

DSS
J

Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 V
Breakdown Voltage Temperature

Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current VGS = ±20V, V

ID = 250µA, referenced to 25°C 24 mV/°C
V

= 0V, VDS = 24V, 1

GS

TC = 125°C 250

= 0V ±100 nA

DS

FDC855N N-Channel, Logic Level, PowerTrench

µA

On Characteristics

V

GS(th)

∆V
∆T

r

DS(on)

g

FS

GS(th)

J

Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1.0 2.0 3.0 V
Gate to Source Threshold Voltage

Temperature Coefficient

Static Drain to Source On Resistance

Forward Transconductance VDD = 10V, ID = 6.1A 20 S

Dynamic Characteristics

C

iss

C

oss

C

rss

R

g

Input Capacitance
Output Capacitance 108 145 pF
Reverse Transfer Capacitance 62 95 pF
Gate Resistance f = 1MHz 1.0 Ω

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q
Q
Q
Q

g
g
gs
gd

Turn-On Delay Time
Rise Time 2 10 ns
Turn-Off Delay Time 14 23 ns
Fall Time 2 10 ns
Total Gate Charge at 10V VGS = 0V to 1 0 V
Total Gate Charge at 5V VGS = 0V to 5V 4.9 7.0 nC
Gate to Source Charge 1.7 nC
Gate to Drain “Miller” Charge 3.1 nC

ID = 250µA, referenced to 25°C -6 mV/°C
VGS = 10V, ID = 6.1A 20.7 27.0

mΩVGS = 4.5V, ID = 5.3A 28.2 36.0

VGS = 10V, ID = 6.1A, TJ =125°C 30.1 39.3

VDS = 15V, VGS = 0V,

493 655 pF

f = 1MHz

6 12 ns

VDD = 15V, ID = 6.1A,
VGS = 10V, R

GEN

= 6Ω

9.2 13 nC

VDD = 15V,
ID = 6.1A

®

MOSFET

Drain-Source Diode Characteristics

V

SD

t

rr

Q

rr

Notes:
1: R

θJA

is guaranteed by design while R

R

θJC

2: Pulse Test: Pulse Width < 300 µs, Duty Cycle < 2.0%.

©2008 Fairchild Semiconductor Corporation
FDC855N Rev.C

Source to Drain Diode Forward Voltage V
Reverse Recovery Time
Reverse Recovery Charge 6 12 nC

is the sum of the junction-to-case and ca se-to- a mbien t ther mal r esistance wher e the case the rmal refer ence i s defi ned as the solder m ount ing sur face of the dr ain pi ns.

is determined by the user’s board design.

θCA

= 0V, IS = 1.3A (Note 2) 0.80 1.2 V

GS

IF = 6.1A, di/dt = 100A/µs

a. 78°C/W when mounted on a

2

1 in

pad of 2 oz copper.

17 31 ns

b. 156°C/W when mounted on a
minimum pad of 2 oz copper.

2

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FDC855N N-Channel, Logic Level, PowerTrench

Typical Characteristics T

20

16

12

8

, DRAIN CURRENT (A)

4

D

I

0

01234

Figure 1.

1.6

1.4

1.2

1.0

NORMALIZED

0.8

DRAIN TO SOURCE ON-RESISTANCE

0.6

-75 -50 -25 0 25 50 75 100 125 150

Fig u r e 3. Nor m a lized O n - Resis t a nce

VGS = 4.5V

VGS = 10V
VGS = 6V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5%MAX

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

On-Region Characteristics Figure 2.

ID = 6.1A
V

= 10V

GS

T

, JUNCTION TEMPERATURE (

J

vs Junction Temperature

= 25°C unless otherwise noted

J

VGS = 4.0V

VGS = 3.5V

o

C)

4.0

PULSE DURATION = 80µs

3.5

VGS = 3.5V

DUTY CYCLE = 0.5%MAX

3.0

2.5

VGS = 4.0V

2.0

NORMALIZED

1.5

1.0

V

DRAIN TO SOURCE ON-RESISTANCE

0.5
048121620

I

, DRAIN CURRENT(A)

D

GS

= 6V

V

GS

V

GS

Norma l i z e d O n - Resistanc e

vs Drain Current and Gate Voltage

60

PULSE DURATION = 300µs

(mΩ)

50

40

DRAIN TO

,

DS(on)

r

30

SOURCE ON-RESISTANCE

20

345678910

V

, GATE TO SO U RCE VOLTA G E (V)

GS

Figure 4.

On-Resistance vs Gate to

DUTY CYCLE = 2%MAX

ID = 6.1A

TJ = 125oC

TJ = 25oC

Source Voltage

= 4.5V

= 10V

®

MOSFET

20

PULSE DURATION = 80µs
DUTY CYCLE = 0.5%MAX

16

V

= 10V

DS

12

8

, DRAIN CURRENT (A)

4

D

I

0

12345

TJ = 150oC

VGS, GATE TO SOURCE VOLTAGE (V)

Figure 5. Transfer Characteristics

©2008 Fairchild Semiconductor Corporation
FDC855N Rev.C

TJ = 25oC

TJ = -55oC

20

10

V

= 0V

GS

1

TJ = 150oC

0.1

0.01

, REVERSE DRAIN CURRENT (A)

S

I

0.001

0.2 0.4 0.6 0.8 1.0 1.2

VSD, BODY DIODE FORWARD VOLTAGE (V)

Figure 6.

Source to Drain Diode

TJ = 25oC

TJ = -55oC

Forward Voltage vs Source Current

3

www.fairchildsemi.com

FDC855N N-Channel, Logic Level, PowerTrench

Typical Characteristics T

10

ID = 6.1A

8

6

4

2

, GATE TO SOURCE VOLTAGE(V)

GS

V

0

Figure 7.

30
10

1

0.1

, DRAIN CURRENT (A)

D

I

0.01

V

= 10V

DD

VDD = 20V

036912

Qg, GATE CHARGE(nC)

Gate Charge Characteristics Figure 8.

THIS AREA IS
LIMITED BY r

DS(on)

SINGLE PULSE

= MAX RATED

T

J

o

R

= 156

C/W

θJA

o

T

= 25

C

A

0.01 0.1 1 10 100

VDS, DRAIN to SOURCE VOLTAGE (V)

Figure 9. Forward Bias Safe

Operating Area

= 25°C unless otherwise noted

J

VDD = 15V

100µs

1ms

10ms

100ms

1s

DC

1000

100

CAPACITANCE (pF)

f = 1MHz

= 0V

V

GS

20

0.1 1 10

VDS, DRAIN TO SOURCE VOLTAGE (V)

Capacitance vs Drain

to Source Voltage

100

VGS = 10V

10

1

), PEAK TRANSIENT POWER (W)

PK

P(

0.5

-3

-2

10

Figure 10.

10

-1

10

t, PULSE WIDTH (s)

110

Sing le Pulse Maximum

Power Dissipation

C

iss

C

oss

C

rss

SINGLE PULSE
R

T

A

θJA

= 25

= 156

o

o

C/W

C

100 1000

30

®

MOSFET

2

1

θJA

Z

0.1

IMPEDANCE,

NORMALIZED THERMAL

0.01

©2008 Fairchild Semiconductor Corporation
FDC855N Rev.C

DUTY CYCLE-DESCENDING ORDER

D = 0.5

0.2

0.1

0.05

0.02

0.01

-3

10

10

SINGLE PULSE
R

= 156oC/W

θJA

-2

-1

10

t, RECTANGULAR PULSE DURATION (sec)

110

Figure 11. Transient Thermal Response Curve

4

P

DM

NOTES:
DUTY FACTOR: D = t1/t

PEAK TJ = PDM x Z

θJA

t

1

t

2

2

x R

+ T

θJA

A

100 1000

www.fairchildsemi.com

Dimensional Outline and Pad Layout

FDC855N N-Channel, Logic Level, PowerTrench

®

MOSFET

©2008 Fairchild Semiconductor Corporation
FDC855N Rev.C

5

www.fairchildsemi.com

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The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
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FDC855N N-Channel, Logic Level, PowerTrench

®

MOSFET

* EZSWITCH™ and FlashWriter

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICEN SE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRC HILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body or (b)
support or sustain life, and (c) whose failure to perform when
properly used in accordance with instructions for use provided

2. A critical component in any component of a life support, device
or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.

in the labeling, can be reasonably expected to result in a
significant injury to the user.

PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design

This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.

This datasheet contains preliminary data; supplementary data will be pub-

Preliminary First Production

lished at a later date. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve design.

No Identification Needed Full Production

This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve design.

This datasheet contains specifications on a product that has been discontin-

Obsolete Not In Production

ued by Fairchild Semiconductor. The datasheet is printed for reference infor­mation only.

Rev. I33

©2008 Fairchild Semiconductor Corporation
FDC855N Rev.C

www.fairchildsemi.com