Page 1
February 2004
FDC796N
30V N-Channel PowerTrench MOSFET
FDC796N
General Description
This N-Channel MOSFET has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers. It has been optimized for
low gate charge, low R
and fast switching speed.
DS(ON)
Applications
• DC/DC converter
• Power management
• Load switch
G
S
S
TM
SuperSOT-6
FLMP
Absolute Maximum Ratings T
S
S
S
o
=25
C unless otherwise noted
A
Features
• 12.5 A, 30 V. R
R
• High performance trench technology for extremely
DS(ON)
low R
• Low gate charge
• High power and current handling capability
• Fast switching speed.
1
2
3
= 9 mΩ @ VGS = 10 V
DS(ON)
= 12 mΩ @ VGS = 4.5 V
DS(ON)
Bottom Drain
6
5
4
Symbol Parameter Ratings Units
V
Drain-Source Voltage 30 V
DSS
V
Gate-Source Voltage
GSS
± 20
ID Drain Current – Continuous (Note 1a) 12.5 A
PD
TJ, T
STG
– Pulsed 40
Maximum Power Dissipation (Note 1a) 2 W
Operating and Storage Junction Temperature Range
(Note 1b)
1.1
−55 to +150 °C
Thermal Characteristics
R
θJA
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a) 60
(Note 1b) 111
0.5
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
2004 Fairchild Semiconductor Corpora tion
.796 FDC796N 7’’ 8mm 3000 units
°C/W
FDC796N Rev D (W)
Page 2
FDC796N
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
Drain–Source Breakdown Voltage
DSS
∆BVDSS
∆T
I
Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 10
DSS
I
Gate–Body Leakage
GSS
Breakdown Voltage Temperature
Coefficient
J
= 0 V, ID = 250 µA
V
GS
I
= 250 µA, Referenced to 25°C
D
= ± 20 V, VDS = 0 V
V
GS
30 V
25
mV/°C
µA
±100
nA
On Characteristics (Note 2)
V
Gate Threshold Voltage
GS(th)
∆VGS(th)
∆TJ
R
DS(on)
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On Resistance
= VGS, ID = 250 µA
V
DS
I
= 250 µA, Referenced to 25°C
D
= 10 V, ID = 12.5 A
V
GS
= 4.5 V, ID = 11 A
V
GS
= 10 V, ID = 12.5 A, TJ=125°C
V
GS
gFS Forward Transconductance VDS = 10 V, ID = 12.5 A 48.4 S
1 2 3 V
– 5.6
7.4
9.5
9
9
12
16
mV/°C
mΩ
Dynamic Characteristics
C
Input Capacitance 1444 pF
iss
C
Output Capacitance 342 pF
oss
C
Reverse Transfer Capacitance
rss
RG Gate Resistance VGS = 15 mV, f = 1.0 MHz 1.25
V
= 15 V, V
DS
f = 1.0 MHz
= 0 V,
GS
135 pF
Ω
Switching Characteristics (Note 2)
t
Turn–On Delay Time 10 20 ns
d(on)
tr Turn–On Rise Time 3.8 7.6 ns
t
Turn–Off Delay Time 26 42 ns
d(off)
tf Turn–Off Fall Time
Qg Total Gate Charge 14 20 nC
Qgs Gate–Source Charge 4 nC
Qgd Gate–Drain Charge
V
= 15 V, ID = 1 A,
DD
= 10 V, R
V
GS
V
= 15 V, ID = 12.5 A,
DS
= 5 V
V
GS
GEN
= 6 Ω
13 23 ns
5 nC
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current 1.5 A
VSD Drain–Source Diode Forward
VGS = 0 V, IS = 1.5 A (Note 2) 0.73 1.2 V
Voltage
trr Diode Reverse Recovery Time 25 nS
Qrr Diode Reverse Recovery Charge
Notes: 1. R
surface of the drain pins. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting
θJA
is guaranteed by design while R
θJC
a) 60°C/W when
mounted on a 1in
of 2 oz copper
= 12.5 A,
I
F
= 100 A/µs
d
iF/dt
is determined by the user's board design.
θCA
2
pad
15 nC
b) 111°C/W when mounted
on a minimum pad of 2 oz
copper
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDC796N Rev D (W)
Page 3
Typical Characteristics
FDC796N
50
VGS = 10V
40
30
20
, DRAIN CURRENT (A)
D
I
10
0
00.511.5
6.0V
4.5V
4.0V
, DRAIN-SOURCE VOLTAGE (V)
V
DS
3.5V
3.0V
2.4
2.2
VGS = 3.5V
2
1.8
1.6
, NORMALIZED
1.4
DS(ON)
R
1.2
1
DRAIN-SOURCE ON-RESISTANCE
0.8
0 1020304050
4.0V
4.5V
, DRAIN CURRENT (A)
I
D
5.0V
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6
ID = 12.5A
= 10V
V
1.4
1.2
, NORMALIZED
DS(ON)
R
0.8
DRAIN-SOURCE ON-RESISTANCE
0.6
GS
1
-50 -25 0 25 50 75 100 125 150
T
, JUNCTION TEMPERATURE (oC)
J
0.024
0.02
0.016
TA = 125oC
0.012
, ON-RESISTANCE (OHM)
TA = 25oC
0.008
DS(ON)
R
0.004
246810
, GATE TO SOURCE VOLTAGE (V)
V
GS
6.0V
10V
ID = 6.3 A
Figure 3. On-Resistance Variation with
Temperature.
50
VDS = 5V
40
30
20
, DRAIN CURRENT (A)
D
I
10
0
1.522.533.54
V
GS
TA = 125oC
25oC
-55oC
, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation
Figure 4. On-Resistance Variation with
100
10
1
0.1
0.01
0.001
, REVERSE DRAIN CURRENT (A)
S
I
0.0001
0 0.2 0.4 0.6 0.8 1 1.2
with Source Current and Temperature.
Gate-to-Source Voltage.
VGS = 0V
TA = 125oC
, BODY DIODE FORWARD VOLTAGE (V)
V
SD
25oC
-55oC
FDC796N Rev D (W)
Page 4
Typical Characteristics
FDC796N
10
ID = 12.5A
8
6
4
2
, GATE-SOURCE VOLTAGE (V)
GS
V
0
0 5 10 15 20 25 30
Q
g
VDS = 10V
20V
, GATE CHARGE (nC)
15V
2000
C
1600
1200
800
CAPACITANCE (pF)
400
0
0 5 10 15 20 25 30
C
OSS
C
RSS
V
DS
ISS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.
100
100ms
1s
10ms
100µs
1ms
R
LIMIT
DS(ON)
10
1
, DRAIN CURRENT (A)
I
VGS = 10V
SINGLE PULSE
0.1
D
0.01
= 111oC/W
R
θ
JA
T
= 25oC
A
0.01 0.1 1 10 100
, DRAIN-SOURCE VOLTAGE (V)
V
DS
10s
DC
10µs
50
40
30
20
10
P(pk), PEAK TRANSIENT POWER (W)
0
0.001 0.01 0. 1 1 10 100 1000
t
, TIME (sec)
1
SINGLE PULSE
R
= 111°C/W
θ
JA
T
= 25°C
A
f = 1MHz
V
= 0 V
GS
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
0.2
0.1
0.01
0.1
0.05
0.02
0.01
SINGLE PULSE
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
0.001
R
JA
θ
R
JA
θ
P(pk)
T
- TA = P * R
J
Duty Cycle, D = t
0.0001 0.001 0.01 0.1 1 10 100 1000
t
, TIME (sec)
1
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
(t) = r(t) * R
= 111 °C/W
t
1
t
2
JA
θ
(t)
JA
θ
/ t
1
2
FDC796N Rev D (W)
Page 5
Dimensional Outline and Pad Layout
FDC796N
FDC796N Rev D (W)
Page 6
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systems which, (a) are intended for surgical implant into
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failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
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PRODUCT STA TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Formative or
In Design
First Production
Full Production
2. A critical component is any component of a life
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be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
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changes at any time without notice in order to improve
design.
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Obsolete
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that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I8
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