Datasheet FDC658P Datasheet (Fairchild Semiconductor)

FDC658P Single P-Channel, Logic Level, PowerTrenchTM MOSFET

General Description Features

February 1999

This P-Channel Logic Level MOSFET is produced using Fairchild Semiconductor's advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain low gate charge for superior switching performance.

These devices are well suited for notebook computer applications: load switching and power management, battery charging circuits, and DC/DC conversion.

SOT-23

SuperSOTTM-8

S

D

.658

G

D

1

SuperSOT -6

TM

D

-4 A, -30 V. R R

= 0.050 Ω @ VGS = -10 V

DS(ON)

= 0.075 Ω @ VGS = -4.5 V.

DS(ON)

Low gate charge (8nC typical). High performance trench technology for extremely low

R

.

DS(ON)

SuperSOTTM-6 package: small footprint (72% smaller than standard SO-8); low profile (1mm thick).

SO-8

SOT-223SuperSOTTM-6

1

2

3

SOIC-16

6

5

4

Absolute Maximum Ratings T

Symbol Parameter Ratings Units

V V I

D

Drain-Source Voltage -30 V

DSS

Gate-Source Voltage - Continuous ±20 V

GSS

Drain Current - Continuous (Note 1a) -4 A

= 25°C unless otherwise note

A

- Pulsed -20

P

TJ,T

THERMAL CHARACTERISTICS

R R

Maximum Power Dissipation (Note 1a) 1.6 W

D

θ

θJC

STG

JA

(Note 1b)

0.8

Operating and Storage Temperature Range -55 to 150 °C

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W

FDC658P Rev.C

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS

BV

∆BV

I

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V Breakdown Voltage Temp. Coefficient ID = -250 µA, Referenced to 25 oC -22 mV/oC

/∆T

J

Zero Gate Voltage Drain Current VDS = -24 V, V

= 0 V -1 µA

GS

TJ = 55 oC -10 µA

I

GSSF

I

GSSR

Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA Gate - Body Leakage, Reverse VGS = -20 V, V

= 0 V -100 nA

DS

ON CHARACTERISTICS (Note 2)

V

∆V

R

GS(th)

DS(ON)

Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.7 -3 V Gate Threshold VoltageTemp.Coefficient ID = -250 µA, Referenced to 25 oC 4.1 mV/oC

/∆T

J

Static Drain-Source On-Resistance VGS = -10 V, ID = -4.0 A 0.041 0.05

TJ = 125 oC 0.058 0.08

VGS = -4.5 V, ID = -3.4 A 0.06 0.075 I g

D(on)

FS

On-State Drain Current VGS = -10 V, VDS = -5 V -20 A Forward Transconductance VDS = -5V, ID = -4 A 9 S

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance VDS = -15 V, VGS = 0 V, 750 pF Output Capacitance f = 1.0 MHz 220 pF Reverse Transfer Capacitance 100 pF

SWITCHING CHARACTERISTICS (Note 2)

t t

t t Q Q Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time VDD = -15 V, ID = -1 A, 12 22 ns Turn - On Rise Time

VGS = -10 V, R

GEN

= 6 Ω

Turn - Off Delay Time 24 38 ns Turn - Off Fall Time 16 27 ns Total Gate Charge VDS = -15 V, ID = -4.0 A, 8 12 nC Gate-Source Charge VGS = -5 V 1.8 nC Gate-Drain Charge 3 nC

DRAIN-SOURCE DIODE CHARACTERISTICS

I

S

V

SD

Notes:

1. R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

by design while R

a. 78oC/W when mounted on a 1 in b. 156oC/W when mounted on a minimum pad of 2oz Cu on FR-4 board.

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

Continuous Source Diode Current -1.3 A Drain-Source Diode Forward Voltage VGS = 0 V, IS = -1.3 A (Note 2) -0.76 -1.2 V

is determined by the user's board design.

CA

θ

2

pad of 2oz Cu on FR-4 board.

14 25 ns

is guaranteed

JC

θ

Ω

FDC658P Rev.C

Typical Electrical Characteristics

20

V = -10V

GS

-6.0V

16

12

-4.5V

-4.0V

-3.5V

8

4

D

- I , DRAIN-SOURCE CURRENT (A) 0

0 1 2 3 4

-V , DRAIN-SOURCE VOLTAGE (V)

DS

-3.0V

Figure 1. On-Region Characteristics.

1.6

I = -4A

D

V = -10V

GS

1.4

1.2

1

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

2

1.8

V = -4.0 V

GS

1.6

-4.5V

1.4

1.2

DS(on)

R , NORMALIZED

1

DRAIN-SOURCE ON-RESISTANCE

0.8 0 4 8 12 16 20

-5.0V

-6.0V

-8.0V

-10.0V

- I , DRAIN CURRENT (A)

D

Figure 2. On-Resistance Variation with

Drain Current and Gate Voltage.

0.16

0.12

0.08

0.04

DS(ON)

R , ON-RESISTANCE (OHM)

0

2 4 6 8 10

-V , GATE TO SOURCE VOLTAGE (V)

GS

T = 125°C

J

T = 25°C

J

I = -2A

D

Figure 3. On-Resistance Variation

with Temperature.

20

V = -5V

DS

16

12

8

D

- I , DRAIN CURRENT (A)

4

0

1 2 3 4 5 6

Figure 5. Transfer Characteristics.

T = -55°C

J

125°C

25°C

-V , GATE TO SOURCE VOLTAGE (V)

GS

Figure 4. On-Resistance Variation with

Gate-to-Source Voltage.

20

V = 0V

10

GS

T = 125°C

1

0.1

0.01

0.001

S

-I , REVERSE DRAIN CURRENT (A)

0.0001 0 0.2 0.4 0.6 0.8 1 1.2 1.4

J

25°C

-55°C

-V , BODY DIODE FORWARD VOLTAGE (V)

SD

Figure 6. Body Diode Forward Voltage

Variation with Source Current

and Temperature.

FDC658P Rev.C

Typical Electrical Characteristics (continued)

10

I = -4A

D

8

6

4

2

GS

-V , GATE-SOURCE VOLTAGE (V) 0

0 3 6 9 12 15

Q , GATE CHARGE (nC)

g

V = -5V

DS

-15V

Figure 7. Gate Charge Characteristics.

80 30

10

RDS(ON) LIMIT

3 1

0.3

V = -10V

0.1

D

-I , DRAIN CURRENT (A)

0.03

0.01

GS

SINGLE PULSE

R = 156°C/W

JA

θ

T = 25°C

A

0.1 0.2 0.5 1 2 5 10 20 50

-V , DRAIN-SOURCE VOLTAGE (V)

DS

1ms

10ms

100ms

1s

DC

-10V

100us

3000

1000

300

CAPACITANCE (pF)

100

f = 1 MHz V = 0 V

GS

30

0.1 0.3 1 3 7 15 30

-V , DRAIN TO SOURCE VOLTAGE (V)

DS

C

Figure 8. Capacitance Characteristics.

5

4

3

2

POWER (W)

1

0

0.01 0.1 1 10 100 300 SINGLE PULSE TIME (SEC)

SINGLE PULSE

R =156°C/W

JA

θ

T = 25°C

A

iss

oss

rss

Figure 9. Maximum Safe Operating Area.

1

D = 0.5

0.5

0.2

0.1

0.05

0.02

r(t), NORMALIZED EFFECTIVE

0.01

TRANSIENT THERMAL RESISTANCE

0.005

0.00001 0.0001 0.001 0.01 0.1 1 10 100 300

0.05

0.02

0.01 Single Pulse

t , TIME (sec)

1

Figure 10. Single Pulse Maximum Power

Dissipation.

R (t) = r(t) * R

JA

θ

R = 156°C/W

JA

θ

P(pk)

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t / t

Figure 11. Transient Thermal Response Curve.

Transient thermal response will change depending on the circuit board design.

Thermal characterization performed using the conditions described in Note 1b.

JA

θ

JA

θ

1 2

FDC658P Rev.C

SuperSOTTM-6 Tape and Reel Data and Package Dimensions

SSOT-6 Packaging Configuration: Figure 1.0

Customize Label

Antistatic Cover Tape

Conductive Embossed

Carrier Tape

F63TNR Label

SSOT-6 Packaging Information

Packaging Option Packaging type

Qty per Reel/Tube/Bag 3,000 10,000 Reel Size Box Dimension (mm) 184x187x47 343x343x64 Max qty per Box 9,000 20,000 Weight per unit (gm) 0.0158 0.0158 Weight per Reel (kg) 0.1440 0.4700

Note/Comments

184mm x

Pizza Box for

184mm x 47mm

Standard Option

SSOT-6 Tape Leader Configuration: Figure 2.0

Standard

(no flow code)

TNR

7” Dia

F63TNR Label

D87Z

TNR

13”

F63TNR Label

Trailer

Pin 1

SSOT-6 Unit Orientation

343mm x 342mm x 64mm

Intermediate box for D87Z Option

F63TNR Label sample

LOT: CBVK741B019

FSID: FDC633N

D/C1: D9842 QTY1: SPEC REV: QARV: D/C2: QTY2: CPN:

631

631631

631

F63TNR Label

QTY: 3000

SPEC:

(F63TNR)2

Carrier

Tape

Cover Tape

 1998 Fairchild Semiconductor Corporation

Trailer Tape 160mm minimum

Components

Leader Tape 390mm minimum

December 1998, Rev. B

SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued

SSOT-6 Embossed Carrier Tape Configuration: Figure 3.0

T

K0

Wc

B0

P0

D0

E1

F

W

E2

Tc

A0

P1

D1

User Direction of Feed

Dimensions are in millimeter

Pkg type

SSOT-6

(8mm)

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481

SSOT-6 Reel Configuration: Figure 4.0

A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc

3.23

3.18

8.0

1.55

1.00

1.75

6.25

+/-0.10

+/-0.3

+/-0.05

+/-0.125

+/-0.10

rotational and lateral movement requirements (see sketches A, B, and C).

B0

20 deg maximum component rotation

Sketch A (Side or Front Sectional View)

Component Rotation

3.50

min

+/-0.05

20 deg maximum

A0

Sketch B (Top View)

Component Rotation

W1 Measured at Hub

4.0 +/-0.1

Typical component cavity center line

Typical component center line

Dim A

Max

4.0 +/-0.1

1.37

0.255 +/-0.150

5.2 +/-0.3

0.5mm maximum

+/-0.10

0.5mm maximum

Sketch C (Top View)

Component lateral movement

0.06 +/-0.02

Dim A

max

Tape Size

8mm 7” Dia

8mm 13” Dia

Reel

Option

Dim N

See detail AA

7” Diameter Option

B Min

Dim C

13” Diameter Option

See detail AA

W2 max Measured at Hub

W3

Dim D

min

DETAIL AA

Dimensions are in inches and millimeters

Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)

7.00

0.059

177.8

13.00 330

1.5

0.059

1.5

512 +0.020/-0.008 13 +0.5/-0.2

0.795

2.165550.331 +0.059/-0.000

20.2

0.795

4.00

20.2

100

8.4 +1.5/0

0.331 +0.059/-0.000

8.4 +1.5/0

0.567

14.4

0.567

14.4

0.311 – 0.429

7.9 – 10.9

0.311 – 0.429

7.9 – 10.9

December 1998, Rev. B

[

]

SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued

SuperSOT-6 (FS PKG Code 31, 33)

1 : 1

Scale 1:1 on letter size paper

Dimensions shown below are in:

Part Weight per unit (gram): 0.0158

inc hes

m illime te rs

 1998 Fairchild Semiconductor Corporation

September 1998, Rev. A

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ CoolFET™ CROSSVOLT™ E2CMOS

TM

FACT™ FACT Quiet Series™

®

FAST FASTr™ GTO™ HiSeC™

ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 TinyLogic™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Obsolete

Formative or In Design

First Production

Full Production

Not In Production

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.