Datasheet FDC653N Datasheet (Fairchild Semiconductor)

FDC653N N-Channel Enhancement Mode Field Effect Transistor

General Description Features

This N-Channel enhancement mode power field effect transistors is produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package.

5 A, 30 V. R R

Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low R Exceptional on-resistance and maximum DC current

capability.

November 1997

= 0.035 Ω @ VGS = 10 V

DS(ON)

= 0.055 Ω @ VGS = 4.5 V.

DS(ON)

.

SOT-23

SuperSOTTM-6

D

SuperSOTTM-8

S

SO-8

1

SOT-223

SOIC-16

6

D

.653

2

5

G

SuperSOT -6

TM

Absolute Maximum Ratings T

D

1

D

= 25°C unless otherwise note

A

Symbol Parameter FDC653N Units

V V I

D

Drain-Source Voltage 30 V

DSS

Gate-Source Voltage - Continuous ±20 V

GSS

Drain Current - Continuous (Note 1a) 5 A

- Pulsed 15

P

TJ,T

Maximum Power Dissipation (Note 1a) 1.6 W

D

STG

(Note 1b)

Operating and Storage Temperature Range -55 to 150 °C

THERMAL CHARACTERISTICS

R R

Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W

θJA

Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W

θJC

3

4

0.8

FDC653N Rev.C

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

A

Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS

BV

∆BV

I

DSS

I

GSSF

I

GSSR

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V Breakdown Voltage Temp. Coefficient

/∆T

J

Zero Gate Voltage Drain Current

ID = 250 µA, Referenced to 25 o C VDS = 24 V, V

GS

= 0 V

31

1 µA

TJ = 55oC Gate - Body Leakage, Forward Gate - Body Leakage, Reverse

VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V

mV /oC

10 µA

100 nA

-100 nA

ON CHARACTERISTICS (Note 2)

V

∆V

R

GS(th)

DS(ON)

Gate Threshold Voltage Gate Threshold VoltageTemp.Coefficient

/∆T

J

Static Drain-Source On-Resistance

VDS = VGS, ID = 250 µA ID = 250 µA, Referenced to 25 o C VGS = 10 V, ID = 5 A

1 1.7 2 V

-4.2

mV /oC

0.027 0.035

TJ = 125oC 0.042 0.056

0.046 0.055

6.2 S

I g

D(on)

VGS = 4.5 V, ID = 4.2 A

On-State Drain Current VGS = 10 V, VDS = 5 V 8 A

FS

Forward Transconductance

VDS = 10 V, ID= 5 A

DYNAMIC CHARACTERISTICS

C

iss

C

oss

C

rss

Input Capacitance

VDS = 15 V, VGS = 0 V, Output Capacitance f = 1.0 MHz 220 pF Reverse Transfer Capacitance 80 pF

350 pF

SWITCHING CHARACTERISTICS (Note 2)

t t

t t Q Q Q

D(on)

r

D(off)

f

g

gs

gd

Turn - On Delay Time VDD = 10 V, ID = 1 A, 7.5 15 ns Turn - On Rise Time

VGS = 4.5 V, R

GEN

= 6 Ω

12 25 ns

Turn - Off Delay Time 13 25 ns Turn - Off Fall Time 6 15 ns Total Gate Charge

VDS = 15 V, ID = 5 A,

12 17 nC Gate-Source Charge VGS = 10 V 2.1 nC Gate-Drain Charge 2.6 nC

DRAIN-SOURCE DIODE CHARACTERISTICS

I

S

V

SD

Continuous Source Diode Current 1.3 A Drain-Source Diode Forward Voltage

VGS = 0 V, IS = 1.3 A (Note 2)

0.75 1.2 V

TJ = 125oC 0.6 1

Notes:

1. R

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

design while R

a. 78oC/W when mounted on a minimum on a 1 in b. 156oC/W when mounted on a minimum pad of 2oz Cu in FR-4 board.

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

is determined by the user's board design.

CA

θ

2

pad of 2oz Cu in FR-4 board.

is guaranteed by

JC

θ

Ω

FDC653N Rev.C

Typical Electrical Characteristics

15

V = 10V

12

6.0

GS

5.0

4.5

4.0

9

6

3

D

I , DRAIN-SOURCE CURRENT (A)

0

0 0.5 1 1.5 2

V , DRAIN-SOURCE VOLTAGE (V)

DS

3.5

3.0

Figure 1. On-Region Characteristics.

1.8

I = 5.0A

D

1.6

V = 10V

GS

1.4

1.2

1

DS(ON)

R , NORMALIZED

0.8

DRAIN-SOURCE ON-RESISTANCE

0.6

-50 -25 0 25 50 75 100 125 150 T , JUNCTION TEMPERATURE (°C)

J

3.5

V =3.5V

3

GS

2.5

2

DS(ON)

1.5

R , NORMALIZED

1

DRAIN-SOURCE ON-RESISTANCE

0.5 0 3 6 9 12 15

4.0

4.5

I , DRAIN CURRENT (A)

D

5.0

Figure 2. On-Resistance Variation with

Drain Current and Gate Voltage.

0.18

0.15

0.12

0.09

0.06

T = 25°C

A

0.03

DS(ON)

R , ON-RESISTANCE (OHM)

0

2 4 6 8 10

T = 125°C

A

V , GATE TO SOURCE VOLTAGE (V)

GS

6.0

I =2A

D

10

Figure 3. On-Resistance Variation

with Temperature.

15

V = 5V

DS

12

9

6

D

I , DRAIN CURRENT (A)

3

0

1.5 2 2.5 3 3.5 4 4.5 V , GATE TO SOURCE VOLTAGE (V)

GS

Figure 5. Transfer Characteristics.

T = -55°C

A

125°C

25°C

Figure 4. On Resistance Variation with

Gate-To- Source Voltage.

15

V =0V

GS

1

0.1

0.01

0.001

S

I , REVERSE DRAIN CURRENT (A)

0.0001 0 0.2 0.4 0.6 0.8 1 1.2

V , BODY DIODE FORWARD VOLTAGE (V)

T = 125°C

A

25°C

-55°C

SD

Figure 6. Body Diode Forward Voltage

Variation with Source Current and

Temperature.

FDC653N Rev.B

Typical Electrical And Thermal Characteristics

10

I = 5.0A

D

8

V = 5V

DS

10V

6

4

2

GS

V , GATE-SOURCE VOLTAGE (V)

0

0 2 4 6 8 10 12 14

Q , GATE CHARGE (nC)

g

15V

Figure 7. Gate Charge Characteristics.

30

10

RDS(ON) LIMIT

3

1

0.3

V = 10V

0.1

D

I , DRAIN CURRENT (A)

0.03

0.01

GS

SINGLE PULSE

R = See Note 1b

JA

θ

T = 25°C

A

0.1 0.2 0.5 1 2 5 10 30 50 V , DRAIN-SOURCE VOLTAGE (V)

DS

1ms

10ms

100ms

1s

DC

100us

1000

500

200

CAPACITANCE (pF)

100

f = 1 MHz V = 0V

GS

50

0.1 0.3 1 3 10 30 V , DRAIN TO SOURCE VOLTAGE (V)

DS

C

iss

oss

rss

Figure 8. Capacitance Characteristics.

5

4

3

2

POWER (W)

1

0

0.01 0.1 1 10 100 300 SINGLE PULSE TIME (SEC)

SINGLE PULSE

R =See note 1b

JA

θ

T = 25°C

A

Figure 9. Maximum Safe Operating Area.

1

D = 0.5

0.5

0.2

0.1

0.05

r(t), NORMALIZED EFFECTIVE

0.02

TRANSIENT THERMAL RESISTANCE

0.01

0.05

0.02

0.01 Single Pulse

0.0001 0.001 0.01 0.1 1 10 100 300

Figure 11. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1b.Transient thermal response will change depending on the circuit board design.

t , TIME (sec)

1

Figure 10. Single Pulse Maximum Power

Dissipation.

R (t) = r(t) * R

JA

θ

R = See Note 1b

JA

θ

P(pk)

t

1

t

2

T - T = P * R (t)

J

A

Duty Cycle, D = t / t

JA

θ

JA

θ

2

1

FDC653N Rev.B