Page 1
FDC37C669
PC 98/99 Compliant Super I/O Floppy
Disk Controller with Infrared Support
FEATURES
5 Volt Operation
!"
Intelligent Auto Power Management
!"
16 Bit Address Qualification (Optional)
!"
2.88MB Super I/O Floppy Disk Controller
!"
- Licensed CMOS 765B Floppy Disk
Controller
- Software and Register Compatible with
SMSC's Proprietary 82077AA Compatible
Core
- Supports Two Floppy Drives Directly
- Supports Vertical Recording Format
- 16 Byte Data FIFO
- 100% IBM Compatibility
- Detects All Overrun and Underrun
Conditions
- Sophisticated Power Control Circuitry
(PCC) Including Multiple Powerdown
Modes for Reduced Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
- Swap Drives A and B
- Non-Burst Mode DMA option
- 48 Base I/O Address,
Three DMA Options
Floppy Disk Available on Parallel Port Pins
!"
Enhanced Digital Data Separator
!"
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps,
250 Kbps Data Rates
- Programmable Precompensation Modes
Serial Ports
!"
- Two High Speed NS16C550 Compatible
UARTs with Send/Receive 16 Byte FIFOs
- Supports 230k and 460k Baud
- Programmable Baud Rate Generator
Seven
IRQ and
- Modem Control Circuitry
- Infrared - IrDA (HPSIR) and Amplitude
Shift Keyed IR (ASKIR)
- Alternate IR Pins (Optional)
- 96 Base I/O Address and Eight IRQ
Options
Multi-Mode Parallel Port with ChiProtect
!"
- Standard Mode
- IBM PC/XT, PC/AT, and PS/2 Compatible
Bidirectional Parallel Port
Enhanced Parallel Port (EPP) Compatible
-
- EPP 1.7 and EPP 1.9 (IEEE 1284
Compliant)
- Enhanced Capabilities Port (ECP)
Compatible (IEEE 1284 Compliant)
- Incorporates ChiProtect Circuitry for
Protection Against Damage Due to Printer
Power-On
- 192 Base I/O Address, Seven IRQ and
Three DMA Options
ISA Host Interface
!"
IDE Interface (Optional)
!"
- On-Chip Decode and Select Logic
Compatible with IBM PC/XT and PC/AT
Embedded Hard Disk Drives
- 48 Base I/O Address and
Options
Game Port Select Logic
!"
- 48 Base I/O Addresses
General Purpose Address Decoder
!"
- 16 Byte Block decode
- 48 Base I/O Address Options
100 Pin QFP and TQFP Package
!"
Seven
IRQ
Page 2
TABLE OF CONTENTS
FEATURES............................................................................................................................................ 1
GENERAL DESCRIPTION..................................................................................................................... 3
PIN CONFIGURATION........................................................................................................................... 4
DESCRIPTION OF PIN FUNCTIONS..................................................................................................... 6
FUNCTIONAL DESCRIPTION............................................................................................................. 17
SUPER I/O REGISTERS.................................................................................................................. 17
HOST PROCESSOR INTERFACE.................................................................................................. 17
FLOPPY DISK CONTROLLER........................................................................................................ 18
FLOPPY DISK CONTROLLER INTERNAL REGISTERS ................................................................ 18
COMMAND SET/DESCRIPTIONS....................................................................................................... 41
INSTRUCTION SET.............................................................................................................................. 45
PARALLEL PORT FLOPPY DISK CONTROLLER................................................................................ 71
SERIAL PORT (UART) ......................................................................................................................... 73
INFRARED INTERFACE........................................................................................................................87
PARALLEL PORT................................................................................................................................ 88
IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES................................................... 90
EXTENDED CAPABILITIES PARALLEL PORT.............................................................................. 96
AUTO POWER MANAGEMENT..........................................................................................................109
INTEGRATED DRIVE ELECTRONICS INTERFACE......................................................................... 114
CONFIGURATION.............................................................................................................................. 118
OPERATIONAL DESCRIPTION......................................................................................................... 137
MAXIMUM GUARANTEED RATINGS........................................................................................... 137
DC ELECTRICAL CHARACTERISTICS....................................................................................... 137
TIMING DIAGRAMS............................................................................................................................ 140
ECP PARALLEL PORT TIMING.....................................................................................................157
2
Page 3
GENERAL DESCRIP TION
The SMSC FDC37C669 PC 95 Compatible Super
I/O Floppy Disk Controller with Infrared Support
utilizes SMSC's proven SuperCell technology for
increased product reliability and functionality. The
FDC37C669 is PC95 compliant and is optimized
for motherboard applications. The FDC37C669
supports both 1 Mbps and 2 Mbps data rates and
vertical vertical recording operation at 1 Mbps
Data Rate.
The FDC37C669 incorporates SMSC's true
CMOS 765B floppy disk controller, advanced
digital data separator, 16 byte data FIFO, two
16C550 compatible UARTs, one Multi-Mode
parallel port which includes ChiProtect circuitry
plus EPP and ECP support, IDE interface, on-chip
12 mA AT bus drivers, game port chip select and
two floppy direct drive support. The true CMOS
765B core provides 100% compatibility with IBM
PC/XT and PC/AT architectures in addition to
providing data overflow and underflow protection.
The SMSC advanced digital data separator
incorporates SMSC's patented data separator
technology, allowing for ease of testing and use.
Both on-chip UARTs are compatible with the
NS16C550. One UART includes additional
support for a Serial Infrared Interface, complying
with IrDA, HPSIR, and ASKIR
formats (used by Sharp, Apple Newton, and other
PDAs). The parallel port, the IDE interface, and
the game port select logic are compatible with
IBM PC/AT architectures. The FDC37C669
incorporates sophisticated power control circuitry
(PCC). The PCC supports multiple low power
down modes.
The FDC37C669 Floppy Disk Controller
incorporates Software Configurable Logic (SCL)
for ease of use. Use of the SCL feature allows
programmable system configuration of key
functions such as the FDC, parallel port, and
UARTs. The parallel port ChiProtect prevents
damage caused by the printer being powered
when the FDC37C669 is not powered.
The FDC37C669 does not require any external
filter components, and is, therefore easy to use
and offers lower system cost and reduced board
area. The FDC37C669 is software and register
compatible with SMSC's proprietary 82077AA
core.
3
Page 4
DRVDEN0
nMTR0
nDS1
nDS0
nMTR1
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
VCC
nRDATA
nDSKCHG
DRVDEN1
IRQ_A
CLK14
DRQ_A
nDACK_A
IRQIN
nIDEEN/IRQ_H
nHDCS0/IRRX2
nHDCS1/IRTX2
nCS
A0
A1
A2
1234567891011121314151617181920212223242526272829
30
nDSR1
TXD1
RXD1
nSTROBE
nAUTOFD
nERROR
nINIT
nSLCTIN
VCC
PD0
PD1
PD2
PD3
VSS
PD4
PD5
PD6
PD7
nACK
BUSYPESLCT
PWRGD/GAMECS
RESETD7D6D5D4
DRQ_B
D3
8079787776757473727170696867666564636261605958575655545352
51
nRTS1
nCTS1
nDTR1
nRI1
nDCD1
nRI2
nDCD2
RXD2/IRRX
TXD2/IRTX
nDSR2
nRTS2
nCTS2
nDTR2
DRV2/ADRX/IRQ_B
VSS
nDACK_C
A10
NC
DRQ_C
IOCHRDY
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PIN CONFIGURATION
FDC37C669
100 PIN QFP
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
D2
D1
D0
VSS
AEN
nIOW
nIOR
A9
A8
A7
IRQ_F
IRQ_E
IRQ_D
IRQ_C
nDACK_B
TC
A6
A5
A4
A3
4
Page 5
DRVDEN0
262728
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47 4849
50
nHDCS1/IRTX2
nCS
A0A1A2A3A4A5A6
TC
nDACK_B
IRQ_C
IRQ_D
IRQ_E
IRQ_F
A7A8A9
nIOR
nIOW
AEN
VSS
D0D1D2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
IOCHRDY
DRQ_CNCA10
nDACK_C
VSS
DRV2/ADRX/IRQ_B
nDTR2
nCTS2
nRTS2
nDSR2
TXD2/IRTX
RXD2/IRRX
nDCD2
nRI2
nDCD1
nRI1
nDTR1
nCTS1
nRTS1
nDSR1
TXD1
RXD1
nSTROBE
nAUTOFD
nMTR0
nDS1
nDS0
nMTR1
VSS
nDIR
nSTEP
nWDATA
nWGATE
nHDSEL
nINDEX
nTRK0
nWRTPRT
VCC
nRDATA
nDSKCHG
DRVDEN1
IRQ_A
CLK14
DRQ_A
nDACK_A
IRQIN
nIDEEN/IRQ_H
nHDCS0/IRRX2
23
75
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
24
25
FDC37C669
100 PIN TQFP
nERROR
74
nINIT
73
nSLCTIN
72
VCC
71
PD0
70
PD1
69
PD2
68
PD3
67
VSS
66
PD4
65
PD5
64
PD6
63
PD7
62
nACK
61
BUSY
60
PE
59
SLCT
58
PWRGD/GAMECS
57
RESET
56
D7
55
D6
54
D5
53
D4
52
DRQ_B
51
D3
5
Page 6
DESCRIPTION OF PIN FUNCTIONS
QFP/
TQFP
PIN NO.
48-51
53-56
44 nI/O Read nIOR I This active low signal is issued by the host
45 nI/O Write nIOW I This active low signal is issued by the host
46 Address Enable AEN I Active high Address Enable indicates DMA
28-34
41-43,
97
21,52,99DMA Request
22,36,96nDMA
35 Terminal Count TC I This signal indicates to the chip that DMA
NAME SYMBOL
HOST PROCESSOR INTERFACE
Data Bus 0-7 D0-D7
I/O Address A0-A10 I These host address bits determine the I/O
DRQ_A
A, B, C
Acknowledge
A, B, C
DRQ_B
DRQ_C
nDACK_A
nDACK_B
nDACK_C
BUFFER
TYPE
I/O24
O24
The data bus connection used by the host
microprocessor to transmit data to and from
the chip. These pins are in a highimpedance state when not in the output
mode.
microprocessor to indicate a read operation.
microprocessor to indicate a write operation.
operations on the host data bus. Used
internally to qualify appropriate address
decodes.
address to be accessed during nIOR and
nIOW cycles. These bits are latched
internally by the leading edge of nIOR and
nIOW. All internal address decodes use the
full A0 to A10 address bits.
This active high output is the DMA request
for byte transfers of data between the host
and the chip. This signal is cleared on the
last byte of the data transfer by the nDACK
signal going low (or by nIOR going low if
nDACK was already low as in demand
mode).
I An active low input acknowledging the
request for a DMA transfer of data between
the host and the chip. This input enables
the DMA read or write internally.
data transfer is complete. TC is only
accepted when nDACK_x is low. In AT and
PS/2 model 30 modes, TC is active high
and in PS/2 mode, TC is active low.
DESCRIPTION
6
Page 7
DESCRIPTION OF PIN FUNCTIONS
QFP/
TQFP
PIN NO.
19,
37-40,
27 Chip Select Input nCS I When enabled, this active low pin serves as
57 Reset RESET IS This active high signal resets the chip and
16 nRead Disk Data nRDATA IS Raw serial bit stream from the disk drive,
10 nWrite
9 nWrite
11 nHead
NAME SYMBOL
Interrupt
Request
A, C, D,
E, F,
Gate
Data
Select
IRQ_A
IRQ_C
IRQ_D
IRQ_E
IRQ_F
FLOPPY DISK INTERFACE
nWGATE
nWDATA
nHDSEL
BUFFER
TYPE
O24
OD24
OD48
OD48
OD48
DESCRIPTION
The interrupt request from the logical device
or IRQIN is output on one of the IRQA-G
signals. Refer to the configuration registers
for more information.
If EPP or ECP Mode is enabled, this output
is pulsed low, then released to allow sharing
of interrupts.
an input for an external decoder circuit
which is used to qualify address lines above
A10.
must be valid for 500 ns minimum. The
effect on the internal registers is described
in the appropriate section. The
configuration registers are not affected by
this reset.
low active. Each falling edge represents a
flux transition of the encoded data.
This active low high current driver allows
current to flow through the write head. It
becomes active just prior to writing to the
diskette.
This active low high current driver provides
the encoded data to the disk drive. Each
falling edge causes a flux transition on the
media.
This high current output selects the floppy
disk side for reading or writing. A logic "1"
on this pin means side 0 will be accessed,
while a logic "0" means side 1 will be accessed.
7
Page 8
DESCRIPTION OF PIN FUNCTIONS
QFP/
TQFP
PIN NO.
7 Direction
8 nStep Pulse nSTEP
17 Disk Change nDSKCHG IS This input senses that the drive door is open
4,3 nDrive Select
2,5 nMotor On 0,1 nMTR0,1
1 DRVDEN0 DRVDEN0
14 nWrite
13 wTrack 00 nTRK00 IS This active low Schmitt Trigger input senses
12 nIndex nINDEX IS This active low Schmitt Trigger input senses
18 DRVDEN1 DRVDEN 1
88 Receive Data 2 RXD2/IRRX I Receiver serial data input for port 2. IR
NAME SYMBOL
nDIR
Control
nDS0,1
O,1
nWRTPRT IS This active low Schmitt Trigger input senses
Protected
SERIAL PORT INTERFACE
BUFFER
TYPE
OD48
OD48
OD48
OD48
OD48
OD48
DESCRIPTION
This high current low active output
determines the direction of the head
movement. A logic "1" on this pin means
outward motion, while a logic "0" means
inward motion.
This active low high current driver issues a
low pulse for each track-to-track movement
of the head.
or that the diskette has possibly been
changed since the last drive selection. This
input is inverted and read via bit 7 of I/O
address 3F7H.
Active low open drain outputs select drives
0-1.
These active low open drain outputs select
motor drives 0-1.
Indicates the drive and media selected.
Refer to configuration registers CR03,
CR0B, CR1F.
from the disk drive that a disk is write
protected. Any write command is ignored.
from the disk drive that the head is
positioned over the outermost track.
from the disk drive that the head is
positioned over the beginning of a track, as
marked by an index hole.
Indicates the drive and media selected.
Refer to configuration registers CR03,
CR0B, CR1F.
Receive Data
8
Page 9
DESCRIPTION OF PIN FUNCTIONS
QFP/
TQFP
PIN NO.
89 Transmit Data 2 TXD2/IRTX
78 Receive Data 1 RXD1 I Reciever serial data input for port 1.
79 Transmit Data 1 TXD1
81,91 nRequest to
NAME SYMBOL
nRTS1
Send
nRTS2
(SYSOPT)
(System Option)
BUFFER
TYPE
O24
024
O4
DESCRIPTION
Transmit serial data output for port 2. IR
transmit data.
Transmit serial data output for port 1.
Active low Request to Send outputs for the
Serial Port. Handshake output signal
notifies modem that the UART is ready to
transmit data. This signal can be
programmed by writing to bit 1 of Modem
Control Register (MCR). The hardware
reset will reset the nRTS signal to inactive
mode (high). Forced inactive during loop
mode operation.
At the trailing edge of hardware reset, the
nRTS2 input is latched to determine the
configuration base address.
0 : INDEX Base I/O Address = 3F0 Hex
1 : INDEX Base I/O Address = 370 Hex
83,93 nData Terminal
Ready
nDTR1
nDTR2
O4
Active low Data Terminal Ready outputs for
the serial port. Handshake output signal
notifies modem that the UART is ready to
establish data communication link. This
signal can be programmed by writing to bit
0 of Modem Control Register (MCR). The
hardware reset will reset the nDTR signal to
inactive mode (high). Forced inactive
during loop mode operation.
9
Page 10
DESCRIPTION OF PIN FUNCTIONS
QFP/
TQFP
PIN NO.
82,92 nClear to Send nCTS1
80,90 nData Set Ready nDSR1
85,87 nData Carrier
NAME SYMBOL
nCTS2
nDSR2
nDCD1
Detect
nDCD2
BUFFER
TYPE
I Active low Clear to Send inputs for the serial
port. Handshake signal which notifies the
UART that the modem is ready to receive
data. The CPU can monitor the status of
nCTS signal by reading bit 4 of Modem
Status Register (MSR). A nCTS signal state
change from low to high after the last MSR
read will set MSR bit 0 to a 1. If bit 3 of
Interrupt Enable Register is set, the interrupt
is generated when nCTS changes state.
The nCTS signal has no effect on the
transmitter. Note: Bit 4 of MSR is the
complement of nCTS.
I Active low Data Set Ready inputs for the
serial port. Handshake signal which notifies
the UART that the modem is ready to
establish the communication link. The CPU
can monitor the status of nDSR signal by
reading bit 5 of Modem Status Register
(MSR). A nDSR signal state change from
low to high after the last MSR read will set
MSR bit 1 to a 1. If bit 3 of Interrupt Enable
Register is set, the interrupt is generated
when nDSR changes state. Note: Bit 5 of
MSR is the complement of nDSR.
I Active low Data Carrier Detect inputs for the
serial port. Handshake signal which notifies
the UART that carrier signal is detected by
the modem. The CPU can monitor the
status of nDCD signal by reading bit 7 of
Modem Status Register (MSR). A nDCD
signal state change from low to high after
the last MSR read will set MSR bit 3 to a 1.
If bit 3 of Interrupt Enable Register is set,
the interrupt is generated when nDCD
changes state. Note: Bit 7 of MSR is the
complement of nDCD.
DESCRIPTION
10
Page 11
DESCRIPTION OF PIN FUNCTIONS
QFP/
TQFP
PIN NO.
84,86 nRing Indicator nRI1
73 nPrinter Select
NAME SYMBOL
nRI2
nSLCTIN OD24
Input
BUFFER
TYPE
I Active low Ring Indicator inputs for the
serial port. Handshake signal which notifies
the UART that the telephone ring signal is
detected by the modem. The CPU can
monitor the status of nRI signal by reading
bit 6 of Modem Status Register (MSR). A
nRI signal state change from low to high
after the last MSR read will set MSR bit 2 to
a 1. If bit 3 of Interrupt Enable Register is
set, the interrupt is generated when nRI
changes state. Note: Bit 6 of MSR is the
complement of nRI.
PARALLEL PORT INTERFACE
This active low output selects the printer.
This is the complement of bit 3 of the Printer
Control Register.
DESCRIPTION
0P24
74 nInitiate Output nINIT OD24
0P24
76 nAutofeed
Output
nAUTOFD OD24
0P24
11
Refer to Parallel Port description for use of
this pin in ECP and EPP mode.
This output is bit 2 of the printer control
register. This is used to initiate the printer
when low.
Refer to Parallel Port description for use of
this pin in ECP and EPP mode.
This output goes low to cause the printer to
automatically feed one line after each line is
printed. The nAUTOFD output is the
complement of bit 1 of the Printer Control
Register.
Refer to Parallel Port description for use of
this pin in ECP and EPP mode.
Page 12
DESCRIPTION OF PIN FUNCTIONS
QFP/
TQFP
PIN NO.
77 nStrobe Output nSTROBE OD24
61 Busy BUSY I This is a status output from the printer, a
62 nAcknowledge nACK I A low active output from the printer
60 Paper End PE I Another status output from the printer, a
59 Printer Selected
75 nError nERROR I A low on this input from the printer indicates
NAME SYMBOL
SLCT I This high active output from the printer
Status
BUFFER
TYPE
0P24
DESCRIPTION
An active low pulse on this output is used to
strobe the printer data into the printer. The
nSTROBE output is the complement of bit 0
of the Printer Control Register.
Refer to Parallel Port description for use of
this pin in ECP and EPP mode.
high indicating that the printer is not ready
to receive new data. Bit 7 of the Printer
Status Register is the complement of the
BUSY input. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode.
indicating that it has received the data and
is ready to accept new data. Bit 6 of the
Printer Status Register reads the nACK
input. Refer to Parallel Port description for
use of this pin in ECP and EPP mode.
high indicating that the printer is out of
paper. Bit 5 of the Printer Status Register
reads the PE input. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode.
indicates that it has power on. Bit 4 of the
Printer Status Register reads the SLCT
input. Refer to Parallel Port description for
use of this pin in ECP and EPP mode.
that there is a error condition at the printer.
Bit 3 of the Printer Status register reads the
nERR input. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode.
12
Page 13
QFP/
TQFP
PIN NO.
63-66
68-71
DESCRIPTION OF PIN FUNCTIONS
NAME SYMBOL
Port Data PD0-PD7
BUFFER
TYPE
I/O24
DESCRIPTION
The bi-directional parallel data bus is used
to transfer information between CPU and
peripherals.
100 IOCHRDY IOCHRDY
24 nIDE Enable
Interrupt
Request H
25 nIDE Chip
Select 0
IRRX2
26 nIDE Chip
Select 1
nIDEEN
IRQ_H
nHDCS0
IRRX2
nHDCS1
OD24P
IDE/ALT IR PINS
O24P
(Note 1)
024
OD24
O24P
(Note 1)
O24P
(Note 1)
In EPP mode, this pin is pulled low to
extend the read/write command. This pin
has an internal pull-up.
This active low signal is active when the IDE
is enabled and the I/O address is accessing
an IDE register.
The interrupt request from a logical device
or IRQIN may be output on the IRQH signal.
Refer to the configuration registers for more
information.
If EPP or ECP Mode is enabled, this output
is pulsed low, then released to allow sharing
of interrupts.
This is the Hard Disk Chip select
corresponding to the eight control block
addresses.
I
Alternate IR Receive input
This is the Hard Disk Chip select
corresponding to the alternate status
register.
IR Transmit 2
20 CLOCK 14 CLK14 ICLK The external connection to a single source
IRTX2
O24P
MISCELLANEOUS
Alternate IR transmit output
14.318 MHz clock.
13
Page 14
QFP/
TQFP
PIN NO.
94 Drive 2
DESCRIPTION OF PIN FUNCTIONS
NAME SYMBOL
DRV2
BUFFER
TYPE
I
DESCRIPTION
In PS/2 mode, this input indicates whether a
second drive is connected; DRV2 should be
low if a second drive is connected. This
status is reflected in a read of Status
Register A.
Address X
Interrupt
Request B
23 IRQIN I This pin is used to steer an interrupt signal
58 PWRGD
nADRX
IRQ_B
OD24
024
(OD24)
I
Active low address decode out: used to
decode a 1, 8, or 16 byte address block. (An
external pull-up is required). Refer to
Configuration registers CR03, CR08 and
CR09 for more information. This pin has a
30ua internal pull-up. The interrupt request
from a logical device or IRQIN may be
output on IRQ_B. Refer to the configuration
registers for more information.
(If EPP or ECP Mode is enabled, this output
is pulsed low, then released to allow sharing
of interrupts.)
from an external device onto one of eight
IRQ outputs IRQA-H.
This active high input indicates that the
power (VCC) is valid. For device operation,
PWRGD must be active. When PWRGD is
inactive, all inputs to Mercury are
disconnected and put into a low power
mode; all outputs are put into high
impedance. The contents of all registers are
preserved as long as VCC has a valid value.
The driver current drain in this mode drops
to ISTBY - standby current. This input has
an internal 30ua pull-up.
98 I/O Power
nGAMECS
NC
O4
This is the Game Port Chip Select output active low. It will go active when the I/O
address, qualified by AEN, matches that
selected in Configuration register CR1E.
No Connect
14
Page 15
DESCRIPTION OF PIN FUNCTIONS
QFP/
TQFP
PIN NO.
NAME SYMBOL
15,72 Power V
6,47,
Ground GND Ground Supply.
CC
BUFFER
TYPE
DESCRIPTION
Positive Supply Voltage.
67,95
Note 1: Refer to Configuration Register 00 for information on the pull-ups for these pins!
Note IDE does not decode for 377, 3F7
Note RI and the Serial interrupt is always active if system power is applied to the chip.
BUFFER TYPE DESCRIPTIONS
BUFFER TYPE
DESCRIPTION
I/O24 Input/Output. 24 mA sink; 12 mA source
O24 Output. 24 mA sink; 12 mA source
OD48 Open drain. 48 mA sink
O4 Output. 4 mA sink; 2 mA source
OD24
OD24P
Output. 24 mA sink
Open drain. 24 mA sink; 30µA source
OP24 Output. 24 mA sink; 4 mA source
024P
Output. 24 mA sink; 12 mA source; with 30µA pull-up
OCLK Output to external crystal
ICLK Input to Crystal Oscillator Circuit (CMOS levels)
I Input TTL compatible.
IS Input with Schmitt Trigger.
15
Page 16
DRV2(nADRX)(IRQB)
nCS
nIOR
nIOW
AEN
A0-A10
D0-D7
DRQ_A-C
nDACK_A-C
TC
IRQA
IRQ_C-F
RESET
IRQIN
IOCHRDY
5 V
Vcc (2)
HOST
CPU
INTERFACE
14.318
CLOCK
Vss (4)
CLOCK
GEN
PWRGD
POWER
MANAGEMENT
ADDRESS BUS
PROPRIETARY
82077 COMPATIBLE
FLOPPYDISK
CONTROLLER
nINDEX
nTRK0
nDSKCHG
nWRPRT
nWGATE
SMSC
VERTICAL
CORE
nDIR
nSTEP
DRVDEN0
DRVDEN1
DATA BUS
CONFIGURATION
REGISTERS
CONTROL BUS
WDATA
WCLOCK
RCLOCK
RDATA
nDS0,1,2
nMTR0,1,2
DIGITAL
DATA
SEPARATOR
WITH WRITE
PRECOM-
PENSATION
nWDATA nRDATA
MULTI-MODE
PARALLEL
PORT/FDC
MUX
GENERAL
PURPOSE
ADDRESS
DECODER
16C550
COMPATIBLE
SERIAL
PORT 1
16C550
COMPATIBLE
SERIAL
PORT 2 WITH
INFRARED
IDE
INTERFACE
GAME
PORT
DECODER
PD0-7
BUSY, SLCT, PE,
nERROR, nACK
nSTROBE, nSLCTIN,
nINIT, nAUTOFD
ADRX
TXD1, nCTS1, nRTS1
RXD1
nDSR1, nDCD1, nRI, nDTR1
TXD2(IRTX),nCTS2,nRTS2
RXD2(IRRX)
nDSR2,nDCD2,nRI2,nDTR2
nIDEEN(IRQH)
nHDCSO(IRRX2)
nHDCS1(IRTX2)
nGAMECS
FIGURE 1 - FDC37C669 BLOCK DIAGRAM
16
Page 17
FUNCTIONAL DESCRIPTION
SUPER I/O REGISTERS
The address map, shown below in Table 1,
shows the addresses of the different blocks of
the Super I/O immediately after power up. The
base addresses of the FDC, IDE, serial and
parallel ports can be moved via the
configuration registers. Some addresses are
used to access more than one register.
Table 1 - FDC37C669 Block Addresses
ADDRESS BLOCK NAME NOTES
3F0, 3F1 or 370, 371 Configuration Write only; Note 1, 2
Base +0,1 Floppy Disk Read only; Disabled at power
Base +[2:5, 7] Floppy Disk Disabled at power up; Note 2
Base +[0:7] Serial Port Com 1 Disabled at power up; Note 2
Base +[0:7] Serial Port Com 2 Disabled at power up; Note 2
Base +[0:3] all modes
Base +[4:7] for EPP
Base +[400:403] for ECP
Base1 +[0:7]
Base2 +[6]
Parallel Port Disabled at power up; Note 2
IDE Disabled at power up; Note 2
HOST PROCESSOR INTERFACE
The host processor communicates with the
FDC37C669 through a series of read/write
registers. The port addresses for these registers
are shown in Table 1. Register access is
accomplished through programmed I/O or DMA
transfers. All registers are 8 bits wide except
the IDE data register at port 1F0H which is 16
bits wide. All host interface output buffers are
capable of sinking a minimum of 12 mA.
up; Note 2
Note 1: Configuration registers can only be modified in configuration mode, refer to the
configuration register description for more information. Access to status registers A and B
of the floppy disk is disabled in configuration mode.
Note 2: The base addresses must be set in the configuration registers before accessing the logical
devices.
17
Page 18
FLOPPY DISK CONTROLLER
The Floppy Disk Controller (FDC) provides the
interface between a host microprocessor and
the floppy disk drives. The FDC integrates the
functions of the Formatter/Controller, Digital
Data Separator, Write Precompensation and
Data Rate Selection logic for an IBM XT/AT
compatible FDC. The true CMOS 765B core
guarantees 100% IBM PC XT/AT compatibility
in addition to providing data overflow and
underflow protection.
The FDC37C669 is compatible to the
82077AA using SMSC's proprietary floppy disk
controller core.
Table 2 - Status, Data and Control Registers
BASE I/O
ADDRESS
+0
+1
+2
+3
+4
+4
+5
+6
+7
+7
R
R
R/W
R/W
R
W
R/W
R
W
Status Register A
Status Register B
Digital Output Register
Tape Drive Register
Main Status Register
Data Rate Select Register
Data (FIFO)
Reserved
Digital Input Register
Configuration Control Register
FLOPPY DISK CONTROLLER INTERNAL
REGISTERS
The Floppy Disk Controller contains eight
internal registers which facilitate the interfacing
between the host microprocessor and the disk
drive. Table 2 shows the addresses required to
access these registers. Registers other than the
ones shown are not supported. The rest of the
FDC description assumes the Base I/O Address
is 3F0.
REGISTER
SRA
SRB
DOR
TSR
MSR
DSR
FIFO
DIR
CCR
For information on the floppy disk on Parallel Port pins, refer to Configuration Register CR4
and Parallel Port Floppy Disk Controller description.
18
Page 19
STATUS REGISTER A (SRA)
Address 3F0 READ ONLY
This register is read-only and monitors the state
of the FINTR pin and several disk interface pins,
PS/2 Mode
7 6 5 4 3 2 1 0
INT
nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR
PENDING
RESET
0 N/A 0 N/A 0 N/A N/A 0
COND.
in PS/2 and Model 30 modes. The SRA can be
accessed at any time when in PS/2 mode. In
the PC/AT mode the data bus pins D0 - D7 are
held in a high impedance state for a read of
address 3F0.
BIT 0 DIRECTION
Active high status indicating the direction of
head movement. A logic "1" indicating inward
direction a logic "0" outward.
BIT 1 nWRITE PROTECT
Active low status of the WRITE PROTECT disk
interface input. A logic "0" indicating that the
disk is write protected.
BIT 2 nINDEX
Active low status of the INDEX disk interface
input.
BIT 3 HEAD SELECT
Active high status of the HDSEL disk interface
input. A logic "1" selects side 1 and a logic "0"
selects side 0.
BIT 4 nTRACK 0
Active low status of the TRK0 disk interface
input.
BIT 5 STEP
Active high status of the STEP output disk
interface output pin.
BIT 6 nDRV2
Active low status of the DRV2 disk interface
input pin, indicating that a second drive has
been installed.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy
Disk Interrupt output.
19
Page 20
PS/2 Model 30 Mode
PENDING
RESET
COND.
7 6 5 4 3 2 1 0
INT
0 0 0 N/A 1 N/A N/A 1
DRQ STEP
F/F
TRK0 nHDSEL INDX WP nDIR
BIT 0 nDIRECTION
Active low status indicating the direction of head
movement. A logic "0" indicating inward
direction a logic "1" outward.
BIT 1 WRITE PROTECT
Active high status of the WRITE PROTECT disk
interface input. A logic "1" indicating that the
disk is write protected.
BIT 2 INDEX
Active high status of the INDEX disk interface
input.
BIT 3 nHEAD SELECT
Active low status of the HDSEL disk interface
input. A logic "0" selects side 1 and a logic "1"
selects side 0.
BIT 4 TRACK 0
Active high status of the TRK0 disk interface
input.
BIT 5 STEP
Active high status of the latched STEP disk
interface output pin. This bit is latched with the
STEP output going active, and is cleared with a
read from the DIR register, or with a hardware
or software reset.
BIT 6 DMA REQUEST
Active high status of the DRQ output pin.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy
Disk Interrupt output.
20
Page 21
STATUS REGISTER B (SRB)
Address F1 READ ONLY
This register is read-only and monitors the state
of several disk interface pins, in PS/2 and Model
PS/2 Mode
7 6 5 4 3 2 1 0
RESET
1 1 DRIVE
SEL0
1 1 0 0 0 0 0 0
WDATA
TOGGLE
COND.
30 modes. The SRB can be accessed at any
time when in PS/2 mode. In the PC/AT mode
the data bus pins D0 - D7 are held in a high
impedance state for a read of address 3F1.
RDATA
TOGGLE
WGATE MOT
EN1
MOT
EN0
BIT 0 MOTOR ENABLE 0
Active high status of the MTR0 disk interface
output pin. This bit is low after a hardware reset
and unaffected by a software reset.
BIT 1 MOTOR ENABLE 1
Active high status of the MTR1 disk interface
output pin. This bit is low after a hardware reset
and unaffected by a software reset.
BIT 2 WRITE GATE
Active high status of the WGATE disk interface
output.
BIT 3 READ DATA TOGGLE
Every inactive edge of the RDATA input causes
this bit to change state.
BIT 4 WRITE DATA TOGGLE
Every inactive edge of the WDATA input causes
this bit to change state.
BIT 5 DRIVE SELECT 0
Reflects the status of the Drive Select 0 bit of
the DOR (address 3F2 bit 0). This bit is cleared
after a hardware reset, it is unaffected by a
software reset.
BIT 6 RESERVED
Always read as a logic "1".
BIT 7 RESERVED
Always read as a logic "1".
21
Page 22
PS/2 Model 30 Mode
nDRV2 nDS1 nDS0 WDATA
RESET
COND.
7 6 5 4 3 2 1 0
F/F
RDATA
F/F
WGATE
F/F
nDS3 nDS2
N/A 1 1 0 0 0 1 1
BIT 0 nDRIVE SELECT 2
Active low status of the DS2 disk interface
output.
BIT 1 nDRIVE SELECT 3
Active low status of the DS3 disk interface
output.
BIT 2 WRITE GATE
Active high status of the latched WGATE output
signal. This bit is latched by the active going
edge of WGATE and is cleared by the read of
the DIR register.
BIT 3 READ DATA
Active high status of the latched RDATA output
signal. This bit is latched by the inactive going
edge of RDATA and is cleared by the read of the
DIR register.
BIT 4 WRITE DATA
Active high status of the latched WDATA output
signal. This bit is latched by the inactive going
edge of WDATA and is cleared by the read of
the DIR register. This bit is not gated with
WGATE.
BIT 5 nDRIVE SELECT 0
Active low status of the DS0 disk interface
output.
BIT 6 nDRIVE SELECT 1
Active low status of the DS1 disk interface
output.
BIT 7 nDRV2
Active low status of the DRV2 disk interface
input.
22
Page 23
DIGITAL OUTPUT REGISTER (DOR)
Address 3F2 READ/WRITE
The DOR controls the drive select and motor
enables of the disk interface outputs. It also
7 6 5 4 3 2 1 0
MOT
EN3
RESET
MOT
EN2
MOT
EN1
0 0 0 0 0 0 0 0
COND.
contains the enable for the DMA logic and
contains a software reset bit. The contents of
the DOR are unaffected by a software reset.
The DOR can be written to at any time.
MOT
EN0
DMAEN nRESET DRIVE
SEL1
DRIVE
SEL0
BIT 0 and 1 DRIVE SELECT
These two bit a are binary encoded for the four
drive selects DS0-DS3, thereby allowing only
one drive to be selected at one time.
BIT 2 nRESET
A logic "0" written to this bit resets the Floppy
disk controller. This reset will remain active
until a logic "1" is written to this bit. This
software reset does not affect the DSR and CCR
registers, nor does it affect the other bits of the
DOR register. The minimum reset duration
required is 100ns, therefore toggling this bit by
consecutive writes to this register is a valid
method of issuing a software reset.
BIT 3 DMAEN
PC/AT and Model 30 Mode:
Writing this bit to logic "1" will enable the DRQ,
nDACK, TC and FINTR outputs. This bit being
a logic "0" will disable the nDACK and TC
inputs, and hold the DRQ and FINTR outputs in
a high impedance state. This bit is a logic "0"
after a reset and in these modes.
PS/2 Mode: In this mode the DRQ, nDACK, TC
and FINTR pins are always enabled. During a
reset, the DRQ, nDACK, TC, and FINTR pins
will remain enabled, but this bit will be cleared to
a logic "0".
BIT 4 MOTOR ENABLE 0
This bit controls the MTR0 disk interface output.
A logic "1" in this bit will cause the output pin to
go active.
BIT 5 MOTOR ENABLE 1
This bit controls the MTR1 disk interface output.
A logic "1" in this bit will cause the output pin to
go active.
BIT 6 MOTOR ENABLE 2
This bit controls the MTR2 disk interface output.
A logic "1" in this bit will cause the output pin to
go active.
BIT 7 MOTOR ENABLE 3
This bit controls the MTR3 disk interface output.
A logic "1" in this bit causes the output to go
active.
Table 3 - Drive Activation Values
DRIVE DOR VALUE
0
1
2
3
1CH
2DH
4EH
8FH
23
Page 24
TAPE DRIVE REGISTER (TDR)
Address 3F3 READ/WRITE
This register is included for 82077 software
Table 4- Tape Select Bits
compatability. The robust digital data separator
used in the FDC37C669 does not require its
characteristics modified for tape support. The
contents of this register are not used internal to
the device. The TDR is unaffected by a
software reset. Bits 2-7 are tri-stated when
read in this mode.
TAPE SEL1 TAPE SEL2
0
0
1
1
0
1
0
1
DRIVE
SELECTED
None
1
2
3
Table 5 - Internal 4 Drive Decode - Normal
DRIVE SELECT OUTPUTS
DIGITAL OUTPUT REGISTER
Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS3 nDS2 nDS1 nDS0 nMTR3 nMTR2 nMTR1 nMTR0
X X X 1 0 0 1 1 1 0 nBIT 7 nBIT 6 nBIT 5 nBIT 4
X X 1 X 0 1 1 1 0 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4
X 1 X X 1 0 1 0 1 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4
1 X X X 1 1 0 1 1 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4
0 0 0 0 X X 1 1 1 1 nBIT 7 nBIT 6 nBIT 5 nBIT 4
(ACTIVE LOW)
MOTOR ON OUTPUTS
(ACTIVE LOW)
Table 6 - Internal 4 Drive Decode - Drives 0 and 1 Swapped
DRIVE SELECT OUTPUTS
DIGITAL OUTPUT REGISTER
Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS3 nDS2 nDS1 nDS0 nMTR3 nMTR2 nMTR1 nMTR0
X X X 1 0 0 1 1 0 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5
X X 1 X 0 1 1 1 1 0 nBIT 7 nBIT 6 nBIT 4 nBIT 5
X 1 X X 1 0 1 0 1 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5
1 X X X 1 1 0 1 1 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5
0 0 0 0 X X 1 1 1 1 nBIT 7 nBIT 6 nBIT 4 nBIT 5
(ACTIVE LOW)
MOTOR ON OUTPUTS
(ACTIVE LOW)
24
Page 25
Table 7 - External 2 to 4 Drive Decode - Normal
DRIVE SELECT
DIGITAL OUTPUT REGISTER
Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0
X X X 1 0 0 0 0 1 0
X X 1 X 0 1 0 1 1 0
X 1 X X 1 0 1 0 1 0
1 X X X 1 1 1 1 1 0
X X X 0 0 0 0 0 1 1
X X 0 X 0 1 0 1 1 1
X 0 X X 1 0 1 0 1 1
0 X X X 1 1 1 1 1 1
OUTPUTS
(ACTIVE LOW)
MOTOR ON OUTPUTS
(ACTIVE LOW)
Table 8 - External 2 to 4 Drive Decode - Drives 0 and 1 Swapped
DRIVE SELECT
DIGITAL OUTPUT REGISTER
Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0
X X X 1 0 0 0 1 1 0
X X 1 X 0 1 0 0 1 0
X 1 X X 1 0 1 0 1 0
1 X X X 1 1 1 1 1 0
X X X 0 0 0 0 1 1 1
X X 0 X 0 1 0 0 1 1
X 0 X X 1 0 1 0 1 1
0 X X X 1 1 1 1 1 1
OUTPUTS
(ACTIVE LOW)
MOTOR ON OUTPUTS
(ACTIVE LOW)
25
Page 26
Normal Floppy Mode
Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a
high impedance.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
REG 3F3 Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state tape sel1 tape sel0
Enhanced Floppy Mode 2 (OS2)
Register 3F3 for Enhanced Floppy Mode 2 operation.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive tape sel1 tape sel0
For this mode, DRATE0 and DRATE1 pins are
inputs, and these inputs are gated into bits 6
and 7 of the 3F3 register. These two bits are
not affected by a hard or soft reset.
BIT 7 Reserved
BIT 6 Reserved
BITS 5 and 4 Drive Type ID - These Bits reflect
two of the bits of configuration register 6.
Table 9 - Drive Type ID
Digital Output Register Register 3F3 - Drive Type ID
Bit 1 Bit 0 Bit 5 Bit 4
0 0 CR6 - Bit 1 CR6 - Bit 0
0 1 CR6 - Bit 3 CR6 - Bit 2
1 0 CR6 - Bit 5 CR6 - Bit 4
1 1 CR6 - Bit 7 CR6 - Bit 6
Which two bits depends on the last drive
selected in the Digital Output Register (3F2).
(See Table 11)
BITS 3 and 2 Floppy Boot Drive - These bits
reflect the value of configuration register 7 bits
1, 0. Bit 3 = CR7 Bit DB1. Bit 2 = CR7 Bit DB0.
Bits 1 and 0 - Tape Drive Select
(READ/WRITE). Same as in Normal and
Enhanced Floppy Mode. 1.
26
Page 27
DATA RATE SELECT REGISTER (DSR)
Address 3F4 WRITE ONLY
This register is write only. It is used to program
the data rate, amount of write precompensation,
power down status, and software reset. The
data rate is programmed using the
Configuration Control Register (CCR) not the
DSR, for PC/AT and PS/2 Model 30 and
7 6 5 4 3 2 1 0
S/W
RESET
RESET
POWER
0 PRE-
DOWN
0 0 0 0 0 0 1 0
COND.
Microchannel applications. Other applications
can set the data rate in the DSR. The data rate
of the floppy controller is the most recent write
of either the DSR or CCR. The DSR is
unaffected by a software reset. A hardware
reset will set the DSR to 02H, which
corresponds to the default precompensation
setting and 250 kbps.
COMP2
PRE-
COMP1
PRE-
COMP0
DRATE
SEL1
DRATE
SEL0
BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy
controller. See Table 13 for the settings
corresponding to the individual data rates. The
data rate select bits are unaffected by a
software reset, and are set to 250 kbps after a
hardware reset.
BIT 2 through 4 PRECOMPENSATION
SELECT
These three bits select the value of write
precompensation that will be applied to the
WDATA output signal. Table 12 shows the
precompensation values for the combination of
these bits settings. Track 0 is the default
starting track number to start precompensation.
this starting track number can be changed by
the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy
controller into Manual Low Power mode. The
floppy controller clock and data separator
circuits will be turned off. The controller will
come out of manual low power mode after a
software reset or access to the Data Register or
Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the
DOR RESET (DOR bit 2) except that this bit is
self clearing.
Table 10 - Precompensation Delays
PRECOMP
432 PRECOMPENSATION DELAY
111
001
010
011
100
101
110
000
0.00 ns-DISABLED
41.67 ns
83.34 ns
125.00 ns
166.67 ns
208.33 ns
250.00 ns
Default (See Table 14)
27
Page 28
Table 11 - Data Rates
DRIVE RATE DATA RATE DATA RATE DENSEL (1) DRATE (2)
DRT1 DRT0 SEL1 SEL0 MFM FM IDENT=1 IDENT=0 1 2
0 0 1 1 1Meg --- 1 0 1 1
0 0 0 0 500 250 1 0 0 0
0 0 0 1 300 150 0 1 0 1
0 0 1 0 250 125 0 1 1 0
0 1 1 1 1Meg --- 1 0 1 1
0 1 0 0 500 250 1 0 0 0
0 1 0 1 500 250 0 1 0 1
0 1 1 0 250 125 0 1 1 0
1 0 1 1 1Meg --- 1 0 1 1
1 0 0 0 500 250 1 0 0 0
1 0 0 1 2Meg --- 0 1 0 1
1 0 1 0 250 125 0 1 1 0
Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
Note 1: This is for DENSEL in normal mode.
Note 2: This is for DRATE0, DRATE1 when Drive Opt are 00.
Table 12 - Default Precompensation Delays
PRECOMPENSATION
DATA RATE
2 Mbps
1 Mbps
500 Kbps
300 Kbps
250 Kbps
*The 2 Mbps data rate is only available if VCC = 5V.
28
DELAYS
125 ns
41.67 ns
125 ns
125 ns
125 ns
Page 29
MAIN STATUS REGISTER
Address 3F4 READ ONLY
The Main Status Register is a read-only register
and indicates the status of the disk controller.
The Main Status Register can be read at any
7 6 5 4 3 2 1 0
RQM DIO NON
DMA
CMD
BUSY
time. The MSR indicates when the disk
controller is ready to receive data via the Data
Register. It should be read before each byte
transferring to or from the data register except in
DMA mode. NO delay is required when reading
the MSR after a data transfer.
DRV3
BUSY
DRV2
BUSY
DRV1
BUSY
DRV0
BUSY
BIT 0 - 3 DRV x BUSY
These bits are set to 1s when a drive is in the
seek portion of a command, including implied
and overlapped seeks and recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a 1 when a command is in
progress. This bit will go active after the
command byte has been accepted and goes
inactive at the end of the results phase. If there
is no result phase (Seek, Recalibrate
commands), this bit is returned to a 0 after the
last command byte.
BIT 5 NON-DMA
This mode is selected in the SPECIFY
command and will be set to a 1 during the
execution phase of a command. This is for
polled data transfers and helps differentiate
between the data transfer phase and the reading
of result bytes.
BIT 6 DIO
Indicates the direction of a data transfer once a
RQM is set. A 1 indicates a read and a 0
indicates a write is required.
BIT 7 RQM
Indicates that the host can transfer data if set to
a 1. No access is permitted if set to a 0.
29
Page 30
DATA REGISTER (FIFO)
Address 3F5 READ/WRITE
All command parameter information, disk data
and result status are transferred between the
host processor and the floppy disk controller
through the Data Register.
Data transfers are governed by the RQM and
DIO bits in the Main Status Register.
The Data Register defaults to FIFO disabled
mode after any form of reset. This maintains
PC/AT hardware compatibility. The default
values can be changed through the Configure
command (enable full FIFO operation with
threshold control). The advantage of the FIFO
is that it allows the system a larger DMA latency
without causing a disk error. Table 15 gives
several examples of the delays with a
Table 13- FIFO Service Delay
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
1 x 4 µs - 1.5 µs = 2.5 µs
2 x 4 µs - 1.5 µs = 6.5 µs
8 x 4 µs - 1.5 µs = 30.5 µs
15 x 4 µs - 1.5 µs = 58.5 µs
FIFO. The data is based upon the following
formula:
Threshold # x 1
DATA RATE
At the start of a command, the FIFO action is
always disabled and command parameters
must be sent based upon the RQM and DIO bit
settings. As the command execution phase is
entered, the FIFO is cleared of any data to
ensure that invalid data is not transferred.
An overrun or underrun will terminate the
current command and the transfer of data. Disk
writes will complete the current sector by
generating a 00 pattern and valid CRC. Reads
require the host to remove the remaining data
so that the result phase may be entered.
MAXIMUM DELAY TO SERVICING
AT 2 Mbps* DATA RATE
-1.5 µs = DELAY
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
MAXIMUM DELAY TO SERVICING
AT 1 Mbps DATA RATE
1 x 8 µs - 1.5 µs = 6.5 µs
2 x 8 µs - 1.5 µs = 14.5 µs
8 x 8 µs - 1.5 µs = 62.5 µs
15 x 8 µs - 1.5 µs = 118.5 µs
MAXIMUM DELAY TO SERVICING
AT 500 Kbps DATA RATE
1 x 16 µs - 1.5 µs = 14.5 µs
2 x 16 µs - 1.5 µs = 30.5 µs
8 x 16 µs - 1.5 µs = 126.5 µs
15 x 16 µs - 1.5 µs = 238.5 µs
*The 2 Mbps data rate is only available if VCC = 5V.
30
Page 31
DIGITAL INPUT REGISTER (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
7 6 5 4 3 2 1 0
DSK
CHG
RESET
N/A N/A N/A N/A N/A N/A N/A N/A
COND.
BIT 0 - 6 UNDEFINED
The data bus outputs D0 - 6 will remain in a
high impedance state during a read of this
register.
PS/2 Mode
7 6 5 4 3 2 1 0
DSK
1 1 1 1 DRATE
CHG
RESET
N/A N/A N/A N/A N/A N/A N/A 1
COND.
BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps
data rates are selected, and high when 250
Kbps and 300 Kbps are selected.
BITS 1 - 2 DATA RATE SELECT
These bits control the data rate of the floppy
controller. See Table 13 for the settings
corresponding to the individual data rates. The
data rate select bits are unaffected by a
BIT 7 DSKCHG
This bit monitors the pin of the same name and
reflects the opposite value seen on the disk
cable.
SEL1
DRATE
SEL0
HIGH
DENS
software reset, and are set to 250 Kbps after a
hardware reset.
BITS 3 - 6 UNDEFINED
Always read as a logic "1"
BIT 7 DSKCHG
This bit monitors the pin of the same name and
reflects the opposite value seen on the disk
cable.
31
Page 32
Model 30 Mode
RESET
COND.
7 6 5 4 3 2 1 0
DSK
CHG
N/A 0 0 0 0 0 1 0
0 0 0 DMAEN NOPREC DRATE
SEL1
DRATE
SEL0
BITS 0 - 1 DATA RATE SELECT
These bits control the data rate of the floppy
controller. See Table 13 for the settings
corresponding to the individual data rates. The
data rate select bits are unaffected by a
software reset, and are set to 250kb/s after a
hardware reset.
BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in
the CCR register.
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in
the DOR register bit 3.
BITS 4 - 6 UNDEFINED
Always read as a logic "0"
BIT 7 DSKCHG
This bit monitors the pin of the same name and
reflects the opposite value seen on the pin.
32
Page 33
CONFIGURATION CONTROL REGISTER (CCR)
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
7 6 5 4 3 2 1 0
RESET
N/A N/A N/A N/A N/A N/A 1 0
COND.
DRATE
SEL1
DRATE
SEL0
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy
controller. See Table 13 for the appropriate
values.
PS/2 Model 30 Mode
7 6 5 4 3 2 1 0
RESET
N/A N/A N/A N/A N/A N/A 1 0
COND.
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy
controller. See Table 13 for the appropriate
values.
BIT 2 NO PRECOMPENSATION
This bit can be set by software, but it has no
functionality. It can be read by bit 2 of the DSR
when in Model 30 register mode. Unaffected by
software reset.
BIT 2 - 7 RESERVED
Should be set to a logical "0"
NOPREC DRATE
SEL1
DRATE
SEL0
BIT 3 - 7 RESERVED
Should be set to a logical "0"
Table 13 shows the state of the DENSEL pin.
The DENSEL pin is set high after a hardware
reset and is unaffected by the DOR and the
DSR resets.
33
Page 34
STATUS REGISTER ENCODING
During the Result Phase of certain commands, the Data Register contains data bytes that give the
status of the command just executed.
Table 14 - Status Register 0
BIT NO. SYMBOL NAME DESCRIPTION
7,6 IC Interrupt
Code
5 SE Seek End The FDC completed a Seek, Relative Seek or
4 EC Equipment
Check
3 Unused. This bit is always "0".
2 H Head
Address
1,0 DS1,0 Drive Select The current selected drive.
00 - Normal termination of command. The specified
command was properly executed and completed
without error.
01 - Abnormal termination of command. Command
execution was started, but was not successfully
completed.
10 - Invalid command. The requested command
could not be executed.
11 - Abnormal termination caused by Polling.
Recalibrate command (used during a Sense Interrupt
Command).
The TRK0 pin failed to become a "1" after:
1. 80 step pulses in the Recalibrate command.
2. The Relative Seek command caused the FDC to
step outward beyond Track 0.
The current head address.
34
Page 35
Table 15 - Status Register 1
BIT NO. SYMBOL NAME DESCRIPTION
7 EN End of
Cylinder
6 Unused. This bit is always "0".
5 DE Data Error The FDC detected a CRC error in either the ID field or
4 OR Overrun/
Underrun
3 Unused. This bit is always "0".
2 ND No Data Any one of the following:
1 NW Not Writeable WP pin became a "1" while the FDC is executing a
0 MA Missing
Address Mark
The FDC tried to access a sector beyond the final
sector of the track (255D). Will be set if TC is not
issued after Read or Write Data command.
the data field of a sector.
Becomes set if the FDC does not receive CPU or DMA
service within the required time interval, resulting in
data overrun or underrun.
1. Read Data, Read Deleted Data command - the
FDC did not find the specified sector.
2. Read ID command - the FDC cannot read the ID
field without an error.
3. Read A Track command - the FDC cannot find the
proper sector sequence.
Write Data, Write Deleted Data, or Format A Track
command.
Any one of the following:
1. The FDC did not detect an ID address mark at the
specified track after encountering the index pulse
from the IDX pin twice.
2. The FDC cannot detect a data address mark or a
deleted data address mark on the specified track.
35
Page 36
Table 16 - Status Register 2
BIT NO. SYMBOL NAME DESCRIPTION
7 Unused. This bit is always "0".
6 CM Control Mark Any one of the following:
1. Read Data command - the FDC encountered a
deleted data address mark.
2. Read Deleted Data command - the FDC
encountered a data address mark.
5 DD Data Error in
Data Field
4 WC Wrong
Cylinder
3 Unused. This bit is always "0".
2 Unused. This bit is always "0".
1 BC Bad Cylinder The track address from the sector ID field is different
0 MD Missing Data
Address Mark
The FDC detected a CRC error in the data field.
The track address from the sector ID field is different
from the track address maintained inside the FDC.
from the track address maintained inside the FDC and
is equal to FF hex, which indicates a bad track with a
hard error according to the IBM soft-sectored format.
The FDC cannot detect a data address mark or a
deleted data address mark.
36
Page 37
Table 17 - Status Register 3
BIT NO. SYMBOL NAME DESCRIPTION
7 Unused. This bit is always "0".
6 WP Write
Indicates the status of the WP pin.
Protected
5 Unused. This bit is always "1".
4 T0 Track 0 Indicates the status of the TRK0 pin.
3 Unused. This bit is always "1".
2 HD Head
Indicates the status of the HDSEL pin.
Address
1,0 DS1,0 Drive Select Indicates the status of the DS1, DS0 pins.
RESET
There are three sources of system reset on the
FDC: The RESET pin of the FDC37C669, a
reset generated via a bit in the DOR, and a reset
generated via a bit in the DSR. At power on, a
Power On Reset initializes the FDC. All resets
take the FDC out of the power down state.
All operations are terminated upon a RESET,
and the FDC enters an idle state. A reset while
a disk write is in progress will corrupt the data
and CRC.
On exiting the reset state, various internal
registers are cleared, including the Configure
command information, and the FDC waits for a
new command. Drive polling will start unless
disabled by a new Configure command.
RESET Pin (Hardware Reset)
The RESET pin is a global reset and clears all
registers except those programmed by the
Specify command. The DOR reset bit is
enabled and must be cleared by the host to exit
the reset state.
DOR Reset vs. DSR Reset (Software Reset)
These two resets are functionally the same.
Both will reset the FDC core, which affects drive
status information and the FIFO circuits. The
DSR reset clears itself automatically while the
DOR reset requires the host to manually clear it.
DOR reset has precedence over the DSR reset.
The DOR reset is set automatically upon a pin
reset. The user must manually clear this reset
bit in the DOR to exit the reset state.
MODES OF OPERATION
The FDC has three modes of operation, PC/AT
mode, PS/2 mode and Model 30 mode. These
are determined by the state of the IDENT and
MFM bits 6 and 5 respectively of configuration
register 3.
PC/AT mode
- (IDENT high, MFM a "don't
care")
The PC/AT register set is enabled, the DMA
enable bit of the DOR becomes valid (FINTR
and DRQ can be hi Z), and TC and DENSEL
become active high signals.
37
Page 38
PS/2 mode
- (IDENT low, MFM high)
This mode supports the PS/2 models 50/60/80
configuration and register set. The DMA bit of
the DOR becomes a "don't care", (FINTR and
DRQ are always valid), TC and DENSEL
become active low.
set of command code bytes and parameter
bytes has to be written to the FDC before the
command phase is complete. (Please refer to
Table 18 for the command set descriptions).
These bytes of data must be transferred in the
order prescribed.
Model 30 mode
- (IDENT low, MFM low)
This mode supports PS/2 Model 30
configuration and register set. The DMA enable
bit of ther DOR becomes valid (FINTR and DRQ
can be hi Z), TC is active high and DENSEL is
active low.
DMA TRANSFERS
DMA transfers are enabled with the Specify
command and are initiated by the FDC by
activating the FDRQ pin during a data transfer
command. The FIFO is enabled directly by
asserting nDACK and addresses need not be
valid.
Note that if the DMA controller (i.e. 8237A) is
programmed to function in verify mode, a
pseudo read is performed by the FDC based
only on nDACK. This mode is only available
when the FDC has been configured into byte
mode (FIFO disabled) and is programmed to do
a read. With the FIFO enabled, the FDC can
perform the above operation by using the new
Verify command; no DMA operation is needed.
CONTROLLER PHASES
For simplicity, command handling in the FDC
can be divided into three phases: Command,
Execution, and Result. Each phase is described
in the following sections.
Command Phase
After a reset, the FDC enters the command
phase and is ready to accept a command from
the host. For each of the commands, a defined
Before writing to the FDC, the host must
examine the RQM and DIO bits of the Main
Status Register. RQM and DIO must be equal
to "1" and "0" respectively before command
bytes may be written. RQM is set false by the
FDC after each write cycle until the received
byte is processed. The FDC asserts RQM again
to request each parameter byte of the command
unless an illegal command condition is
detected. After the last parameter byte is
received, RQM remains "0" and the FDC
automatically enters the next phase as defined
by the command definition.
The FIFO is disabled during the command
phase to provide for the proper handling of the
"Invalid Command" condition.
Execution Phase
All data transfers to or from the FDC occur
during the execution phase, which can proceed
in DMA or non-DMA mode as indicated in the
Specify command.
After a reset, the FIFO is disabled. Each data
byte is transferred by an FINT or FDRQ
depending on the DMA mode. The Configure
command can enable the FIFO and set the
FIFO threshold value.
The following paragraphs detail the operation of
the FIFO flow control. In these descriptions,
<threshold> is defined as the number of bytes
available to the FDC when service is requested
from the host and ranges from 1 to 16. The
parameter FIFOTHR, which the user programs,
is one less and ranges from 0 to 15.
38
Page 39
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host reads (writes)
from (to) the FIFO until empty (full), then the
transfer request goes inactive. The host must
be very responsive to the service request. This
is the desired case for use with a "fast" system.
A high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in
more frequent service requests.
Non-DMA Mode - Transfers from the FIFO to
the Host
DMA Mode - Transfers from the FIFO to the
Host
The FDC activates the DDRQ pin when the
FIFO contains (16 - <threshold>) bytes, or the
last byte of a full sector transfer has been
placed in the FIFO. The DMA controller must
respond to the request by reading data from the
FIFO. The FDC will deactivate the DDRQ pin
when the FIFO becomes empty. FDRQ goes
inactive after nDACK goes active for the last
byte of a data transfer (or on the active edge of
nIOR, on the last byte, if no edge is present on
nDACK). A data underrun may occur if FDRQ
is not removed in time to prevent an unwanted
cycle.
The FINT pin and RQM bits in the Main Status
Register are activated when the FIFO contains
(16-<threshold>) bytes or the last bytes of a full
sector have been placed in the FIFO. The FINT
pin can be used for interrupt-driven systems,
and RQM can be used for polled systems. The
host must respond to the request by reading
data from the FIFO. This process is repeated
until the last byte is transferred out of the FIFO.
The FDC will deactivate the FINT pin and RQM
bit when the FIFO becomes empty.
Non-DMA Mode - Transfers from the Host to the
FIFO
The FINT pin and RQM bit in the Main Status
Register are activated upon entering the
execution phase of data transfer commands.
The host must respond to the request by writing
data into the FIFO. The FINT pin and RQM bit
remain true until the FIFO becomes full. They
are set true again when the FIFO has
<threshold> bytes remaining in the FIFO. The
FINT pin will also be deactivated if TC and
nDACK both go inactive. The FDC enters the
result phase after the last byte is taken by the
FDC from the FIFO (i.e. FIFO empty condition).
DMA Mode - Transfers from the Host to the
FIFO
The FDC activates the FDRQ pin when entering
the execution phase of the data transfer
commands. The DMA controller must respond
by activating the nDACK and nIOW pins and
placing data in the FIFO. FDRQ remains active
until the FIFO becomes full. FDRQ is again set
true when the FIFO has <threshold> bytes
remaining in the FIFO. The FDC will also
deactivate the FDRQ pin when TC becomes true
(qualified by nDACK), indicating that no more
data is required. FDRQ goes inactive after
nDACK goes active for the last byte of a
data transfer (or on the active edge of nIOW of
the last byte, if no edge is present on nDACK).
A data overrun may occur if FDRQ is not
removed in time to prevent an unwanted cycle.
Data Transfer Termination
The FDC supports terminal count explicitly
through the TC pin and implicitly through the
underrun/overrun and end-of-track (EOT)
functions. For full sector transfers, the EOT
parameter can define the last sector to be
transferred in a single or multi-sector transfer.
39
Page 40
If the last sector to be transferred is a partial
sector, the host can stop transferring the data in
mid-sector, and the FDC will continue to
complete the sector as if a hardware TC was
received. The only difference between these
implicit functions and TC is that they return
"abnormal termination" result status. Such
status indications can be ignored if they were
expected.
Note that when the host is sending data to the
FIFO of the FDC, the internal sector count will
be complete when the FDC reads the last byte
from its side of the FIFO. There may be a delay
in the removal of the transfer request signal of
up to the time taken for the FDC to read the last
16 bytes from the FIFO. The host must tolerate
this delay.
Result Phase
The generation of FINT determines the
beginning of the result phase. For each of the
commands, a defined set of result bytes has to
be read from the FDC before the result phase is
complete. These bytes of data must be read out
for another command to start.
RQM and DIO must both equal "1" before the
result bytes may be read. After all the result
bytes have been read, the RQM and DIO bits
switch to "1" and "0" respectively, and the CB bit
is cleared, indicating that the FDC is ready to
accept the next command.
40
Page 41
COMMAND SET/DESCRIPTIONS
is issued. The user sends a Sense Interrupt
Status command which returns an invalid
Commands can be written whenever the FDC is
in the command phase. Each command has a
unique set of needed parameters and status
results. The FDC checks to see that the first
byte is a valid command and, if valid, proceeds
command error. Refer to Table 18 or
explanations of the various symbols used.
Table 19 lists the required parameters and the
results associated with each command that the
FDC is capable of performing.
with the command. If it is invalid, an interrupt
Table 18 - Description of Command Symbols
SYMBOL NAME DESCRIPTION
C Cylinder Address The currently selected address; 0 to 255.
D Data Pattern The pattern to be written in each sector data field during
formatting.
D0, D1, D2,D3Drive Select 0-3 Designates which drives are perpendicular drives on the
Perpendicular Mode Command. A "1" indicates a perpendicular
drive.
DIR Direction Control If this bit is 0, then the head will step out from the spindle during a
relative seek. If set to a 1, the head will step in toward the spindle.
DS0, DS1 Disk Drive Select
DS1 DS0 DRIVE
0 0 drive 0
0 1 drive 1
1 0 drive 2
1 1 drive 3
DTL Special Sector
Size
By setting N to zero (00), DTL may be used to control the number
of bytes transferred in disk read/write commands. The sector size
(N = 0) is set to 128. If the actual sector (on the diskette) is larger
than DTL, the remainder of the actual sector is read but is not
passed to the host during read commands; during write
commands, the remainder of the actual sector is written with all
zero bytes. The CRC check code is calculated with the actual
sector. When N is not zero, DTL has no meaning and should be
set to FF HEX.
EC Enable Count When this bit is "1" the "DTL" parameter of the Verify command
becomes SC (number of sectors per track).
EFIFO Enable FIFO This active low bit when a 0, enables the FIFO. A "1" disables the
FIFO (default).
EIS Enable Implied
Seek
When set, a seek operation will be performed before executing any
read or write command that requires the C parameter in the
command phase. A "0" disables the implied seek.
EOT End of Track The final sector number of the current track.
41
Page 42
Table 18 - Description of Command Symbols
SYMBOL NAME DESCRIPTION
GAP Alters Gap 2 length when using Perpendicular Mode.
GPL Gap Length The Gap 3 size. (Gap 3 is the space between sectors excluding
the VCO synchronization field).
H/HDS Head Address Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector
ID field.
HLT Head Load Time The time interval that FDC waits after loading the head and before
initializing a read or write operation. Refer to the Specify
command for actual delays.
HUT Head Unload
Time
LOCK Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters
MFM MFM/FM Mode
Selector
MT Multi-Track
Selector
The time interval from the end of the execution phase (of a read or
write command) until the head is unloaded. Refer to the Specify
command for actual delays.
of the CONFIGURE COMMAND can be reset to their default
values by a "Software Reset". (A reset caused by writing to the
appropriate bits of either the DSR or DOR)
A one selects the double density (MFM) mode. A zero selects
single density (FM) mode.
When set, this flag selects the multi-track operating mode. In this
mode, the FDC treats a complete cylinder under head 0 and 1 as
a single track. The FDC operates as this expanded track started
at the first sector under head 0 and ended at the last sector under
head 1. With this flag set, a multitrack read or write operation will
automatically continue to the first sector under head 1 when the
FDC finishes operating on the last sector under head 0.
42
Page 43
Table 18 - Description of Command Symbols
SYMBOL NAME DESCRIPTION
N Sector Size Code This specifies the number of bytes in a sector. If this parameter is
"00", then the sector size is 128 bytes. The number of bytes
transferred is determined by the DTL parameter. Otherwise the
sector size is (2 raised to the "N'th" power) times 128. All values
up to "07" hex are allowable. "07"h would equal a sector size of
16k. It is the user's responsibility to not select combinations that
are not possible with the drive.
N SECTOR SIZE
00 128 bytes
01 256 bytes
02 512 bytes
03 1024 bytes
.. …
07 16 kbytes
NCN New Cylinder
The desired cylinder number.
Number
ND Non-DMA Mode
Flag
When set to 1, indicates that the FDC is to operate in the nonDMA mode. In this mode, the host is interrupted for each data
transfer. When set to 0, the FDC operates in DMA mode,
interfacing to a DMA controller by means of the DRQ and nDACK
signals.
OW Overwrite The bits D0-D3 of the Perpendicular Mode Command can only be
modified if OW is set to 1. OW id defined in the Lock command.
PCN Present Cylinder
Number
The current position of the head at the completion of Sense
Interrupt Status command.
POLL Polling Disable When set, the internal polling routine is disabled. When clear,
polling is enabled.
PRETRK Precompensation
Programmable from track 00 to FFH.
Start Track
Number
R Sector Address The sector number to be read or written. In multi-sector transfers,
this parameter specifies the sector number of the first sector to be
read or written.
RCN Relative Cylinder
Number
Relative cylinder offset from present cylinder as used by the
Relative Seek command.
43
Page 44
Table 18 - Description of Command Symbols
SYMBOL NAME DESCRIPTION
SC Number of
Sectors Per Track
SK Skip Flag When set to 1, sectors containing a deleted data address mark will
SRT Step Rate Interval The time interval between step pulses issued by the FDC.
ST0
ST1
ST2
ST3
WGATE Write Gate Alters timing of WE to allow for pre-erase loads in perpendicular
Status 0
Status 1
Status 2
Status 3
The number of sectors per track to be initialized by the Format
command. The number of sectors per track to be verified during a
Verify command when EC is set.
automatically be skipped during the execution of Read Data. If
Read Deleted is executed, only sectors with a deleted address
mark will be accessed. When set to "0", the sector is read or
written the same as the read and write commands.
Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms
at the 1 Mbit data rate. Refer to the SPECIFY command for actual
delays.
Registers within the FDC which store status information after a
command has been executed. This status information is available
to the host during the result phase after command execution.
drives.
44
Page 45
INSTRUCTION SET
Table 19 - Instruction Set
READ DATA
DATA BUS
PHASE R/W
Command W MT MFM SK 0 0 1 1 0 Command Codes
Execution Data transfer between the
Result R
D7 D6 D5 D4 D3 D2 D1 D0
W 0 0 0 0 0 HDS DS1 DS0
W
W
W
W
W
W
W
R
R
R
R
R
R
C
H
R
N
EOT
GPL
DTL
ST0
ST1
ST2
C
H
R
N
Sector ID information prior to
Command execution.
FDD and system.
Status information after
Command execution.
Sector ID information after
Command execution.
REMARKS
45
Page 46
READ DELETED DATA
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W MT MFM SK 0 1 1 0 0 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W
C
Sector ID information prior to
Command execution.
W
W
W
W
W
W
H
R
N
EOT
GPL
DTL
Execution Data transfer between the
FDD and system.
Result R
ST0
Status information after
Command execution.
R
R
R
ST1
ST2
C
Sector ID information after
Command execution.
R
R
R
H
R
N
46
Page 47
WRITE DATA
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W MT MFM 0 0 0 1 0 1 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W
C
Sector ID information prior to
Command execution.
W
W
W
W
W
W
H
R
N
EOT
GPL
DTL
Execution Data transfer between the
FDD and system.
Result R
ST0
Status information after
Command execution.
R
R
R
ST1
ST2
C
Sector ID information after
Command execution.
R
R
R
H
R
N
47
Page 48
WRITE DELETED DATA
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W MT MFM 0 0 1 0 0 1 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W
C
Sector ID information
prior to Command
execution.
W
W
W
W
W
W
H
R
N
EOT
GPL
DTL
Execution Data transfer between
the FDD and system.
Result R
ST0
Status information after
Command execution.
R
R
R
ST1
ST2
C
Sector ID information
after Command
execution.
R
R
R
H
R
N
48
Page 49
READ A TRACK
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W 0 MFM 0 0 0 0 1 0 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W
C
Sector ID information
prior to Command
execution.
W
W
W
W
W
W
H
R
N
EOT
GPL
DTL
Execution Data transfer between
the FDD and system.
FDC reads all of
cylinders' contents from
index hole to EOT.
Result R
ST0
Status information after
Command execution.
R
R
R
ST1
ST2
C
Sector ID information
after Command
execution.
R
R
R
H
R
N
49
Page 50
VERIFY
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W MT MFM SK 1 0 1 1 0 Command Codes
W EC 0 0 0 0 HDS DS1 DS0
W
C
Sector ID information
prior to Command
execution.
W
W
W
W
W
W
H
R
N
EOT
GPL
DTL/SC
Execution No data transfer takes
place.
Result R
ST0
Status information after
Command execution.
R
R
R
ST1
ST2
C
Sector ID information
after Command
execution.
R
R
R
H
R
N
VERSION
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W 0 0 0 1 0 0 0 0 Command Code
Result R 1 0 0 1 0 0 0 0 Enhanced Controller
50
Page 51
FORMAT A TRACK
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W 0 MFM 0 0 1 1 0 1 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W
W
W
W
N
SC
GPL
D
Bytes/Sector
Sectors/Cylinder
Gap 3
Filler Byte
Execution for
Each Sector
Repeat:
Result R
W
W
W
W
C
Input Sector
Parameters
H
R
N
FDC formats an entire
cylinder
ST0
Status information after
Command execution
R
R
R
R
R
R
Undefined
Undefined
Undefined
Undefined
ST1
ST2
51
Page 52
RECALIBRATE
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W 0 0 0 0 0 1 1 1 Command Codes
W 0 0 0 0 0 0 DS1 DS0
Execution Head retracted to Track 0
Interrupt.
SENSE INTERRUPT STATUS
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W 0 0 0 0 1 0 0 0 Command Codes
Result R
ST0
Status information at the end
of each seek operation.
R
PCN
SPECIFY
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W 0 0 0 0 0 0 1 1 Command Codes
W
W
SRT
HLT
HUT
ND
52
Page 53
SENSE DRIVE STATUS
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W 0 0 0 0 0 1 0 0 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
Result R
ST3
Status information about
FDD
SEEK
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W 0 0 0 0 1 1 1 1 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W
NCN
Execution Head positioned over
proper cylinder on
diskette.
CONFIGURE
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W 0 0 0 1 0 0 1 1 Configure
Information
W 0 0 0 0 0 0 0 0
W 0 EIS EFIFO POLL
Execution W
FIFOTHR
PRETRK
53
Page 54
RELATIVE SEEK
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W 1 DIR 0 0 1 1 1 1
W 0 0 0 0 0 HDS DS1 DS0
W
RCN
DUMPREG
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W 0 0 0 0 1 1 1 0 *Note:
Registers
placed in
FIFO
Execution
Result R
R
R
R
R
R
SRT
R
PCN-Drive 0
PCN-Drive 1
PCN-Drive 2
PCN-Drive 3
HLT
SC/EOT
HUT
ND
R LOCK 0 D3 D2 D1 D0 GAP WGATE
R 0 EIS EFIFO POLL
R
PRETRK
FIFOTHR
54
Page 55
READ ID
DATA BUS
PHASE R/W
D7 D6 D5 D4 D3 D2 D1 D0
REMARKS
Command W 0 MFM 0 0 1 0 1 0 Commands
W 0 0 0 0 0 HDS DS1 DS0
Execution The first correct ID
information on the
Cylinder is stored in
Data Register
Result R
ST0
Status information after
Command execution.
Disk status after the
Command has
completed
R
R
R
R
R
R
ST1
ST2
C
H
R
N
55
Page 56
PERPENDICULAR MODE
DATA BUS
PHASE R/W
Command W 0 0 0 1 0 0 1 0 Command Codes
PHASE R/W
Command W
Result R
PHASE R/W
Command W LOCK 0 0 1 0 1 0 0 Command Codes
Result R 0 0 0 LOCK 0 0 0 0
SC is returned if the last command that was issued was the Format command. EOT is returned if the
last command was a Read or Write.
D7 D6 D5 D4 D3 D2 D1 D0
OW 0 D3 D2 D1 D0 GAP WGATE
INVALID CODES
DATA BUS
D7 D6 D5 D4 D3 D2 D1 D0
Invalid Codes
D7 D6 D5 D4 D3 D2 D1 D0
ST0
DATA BUS
LOCK
Invalid Command Codes (No
Op - FDC37C669 goes into
Standby State)
ST0 = 80H
REMARKS
REMARKS
REMARKS
These bits are used internally only. They are not reflected in the Drive Select pins. It is the
NOTE:
user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).
56
Page 57
DATA TRANSFER COMMANDS
All of the Read Data, Write Data and Verify type
commands use the same parameter bytes and
return the same results information, the only
difference being the coding of bits 0-4 in the first
byte.
An implied seek will be executed if the feature
was enabled by the Configure command. This
seek is completely transparent to the user. The
Drive Busy bit for the drive will go active in the
Main Status Register during the seek portion of
the command. If the seek portion fails, it will be
reflected in the results status normally returned
for a Read/Write Data command. Status
Register 0 (ST0) would contain the error code
and C would contain the cylinder on which the
seek failed.
Read Data
A set of nine (9) bytes is required to place the
FDC in the Read Data Mode. After the Read
Data command has been issued, the FDC loads
the head (if it is in the unloaded state), waits the
specified head settling time (defined in the
Specify command), and begins reading ID
Address Marks and ID fields. When the sector
address read off the diskette matches with the
sector address specified in the command, the
FDC reads the sector's data field and transfers
the data to the FIFO.
After completion of the read operation from the
current sector, the sector address is
incremented by one and the data from the next
logical sector is read and output via the FIFO.
This continuous read function is called "MultiSector Read Operation". Upon receipt of TC, or
an implied TC (FIFO overrun/underrun), the
FDC stops sending data but will continue to
read data from the current sector, check the
CRC bytes, and at the end of the sector,
terminate the Read Data Command.
N determines the number of bytes per sector
(see Table 22 below). If N is set to zero, the
sector size is set to 128. The DTL value
determines the number of bytes to be
transferred. If DTL is less than 128, the FDC
transfers the specified number of bytes to the
host. For reads, it continues to read the entire
128-byte sector and checks for CRC errors. For
writes, it completes the 128-byte sector by filling
in zeros. If N is not set to 00 Hex, DTL should
be set to FF Hex and has no impact on the
number of bytes transferred.
Table 20 - Sector Sizes
N SECTOR SIZE
00
01
02
03
..
07
128 bytes
256 bytes
512 bytes
1024 bytes
...
16 Kbytes
The amount of data which can be handled with
a single command to the FDC depends upon
MT (multi-track) and N (number of bytes/sector).
The Multi-Track function (MT) allows the FDC to
read data from both sides of the diskette. For a
particular cylinder, data will be transferred
starting at Sector 1, Side 0 and completing the
last sector of the same track at Side 1.
If the host terminates a read or write operation
in the FDC, the ID information in the result
phase is dependent upon the state of the MT bit
and EOT byte. Refer to Table 23.
At the completion of the Read Data command,
the head is not unloaded until after the Head
Unload Time Interval (specified in the Specify
command) has elapsed. If the host issues
another command before the head unloads,
then the head settling time may be saved
between subsequent reads.
57
Page 58
If the FDC detects a pulse on the nINDEX pin
twice without finding the specified sector
(meaning that the diskette's index hole passes
through index detect logic in the drive twice), the
FDC sets the IC code in Status Register 0 to
"01" indicating abnormal termination, sets the
ND bit in Status Register 1 to "1" indicating a
sector not found, and terminates the Read Data
Command.
After reading the ID and Data Fields in each
Table 21 - Effects of MT and N Bits
MAXIMUM TRANSFER
MT N
0
1
0
1
0
1
1
1
2
2
3
3
CAPACITY
256 x 26 = 6,656
256 x 52 = 13,312
512 x 15 = 7,680
512 x 30 = 15,360
1024 x 8 = 8,192
1024 x 16 = 16,384
Table 22 - Skip Bit vs Read Data Command
DATA ADDRESS
SK BIT
VALUE
MARK TYPE
ENCOUNTERED
SECTOR
READ?
0
Normal Data
0
Deleted Data
1
Normal Data
1
Deleted Data
sector, the FDC checks the CRC bytes. If a
CRC error occurs in the ID or data field, the
FDC sets the IC code in Status Register 0 to
"01" indicating abnormal termination, sets the
DE bit flag in Status Register 1 to "1", sets the
DD bit in Status Register 2 to "1" if CRC is
incorrect in the ID field, and terminates the Read
Data Command. Table 22 describes the effect
of the SK bit on the Read Data command
execution and results. Except where noted in
Table 22, the C or R value of the sector
address is automatically incremented (see Table
24).
FINAL SECTOR READ
FROM DISK
26 at side 0 or 1
26 at side 1
15 at side 0 or 1
15 at side 1
8 at side 0 or 1
16 at side 1
RESULTS
Yes
CM BIT OF
ST2 SET?
No
DESCRIPTION
OF RESULTS
Normal
termination.
Yes
Yes
Address not
incremented.
Next sector not
searched for.
Yes
No
Normal
termination.
No
Yes
Normal
termination.
Sector not read
("skipped").
58
Page 59
Read Deleted Data
This command is the same as the Read Data
command, only it operates on sectors that
contain a Deleted Data Address Mark at the
beginning of a Data Field.
Table 23 - Skip Bit vs. Read Deleted Data Command
DATA ADDRESS
SK BIT
VALUE
0
0
1
1
MARK TYPE
ENCOUNTERED
Normal Data
Deleted Data
Normal Data
Deleted Data
SECTOR
READ?
Table 25 describes the effect of the SK bit on
the Read Deleted Data command execution and
results.
Except where noted in Table 25, the C or R
value of the sector address is automatically
incremented (see Table 26).
RESULTS
Yes
CM BIT OF
ST2 SET?
Yes
DESCRIPTION
OF RESULTS
Address not
incremented.
Next sector not
searched for.
Yes
No
Normal
termination.
No
Yes
Normal
termination.
Sector not read
("skipped").
Yes
No
Normal
termination.
Read A Track
This command is similar to the Read Data
command except that the entire data field is
read continuously from each of the sectors of a
track. Immediately after encountering a pulse
on the nINDEX pin, the FDC starts to read
all data fields on the track as continuous blocks
of data without regard to logical sector numbers.
If the FDC finds an error in the ID or DATA CRC
check bytes, it continues to read data from the
track and sets the appropriate error bits at the
end of the command. The FDC compares the
ID information read from each sector with the
specified value in the command
and sets the ND flag of Status Register 1
to a "1" if there is no comparison. Multi-track or
skip operations are not allowed with this
command. The MT and SK bits (bits D7 and D5
of the first command byte respectively) should
always be set to "0".
This command terminates when the EOT
specified number of sectors has not been read.
If the FDC does not find an ID Address Mark on
the diskette after the second occurrence of a
pulse on the IDX pin, then it sets the IC code in
Status Register 0 to "01" (abnormal
termination), sets the MA bit in Status Register
1 to "1", and terminates the command.
59
Page 60
Table 24 - Result Phase Table
MT
0
HEAD
0
1
FINAL SECTOR
TRANSFERRED TO HOST
Less than EOT NC NC R + 1 NC
Equal to EOT C + 1 NC 01 NC
Less than EOT NC NC R + 1 NC
ID INFORMATION AT RESULT PHASE
C H R N
Equal to EOT C + 1 NC 01 NC
0
1
1
Less than EOT NC NC R + 1 NC
Equal to EOT NC LSB 01 NC
Less than EOT NC NC R + 1 NC
Equal to EOT C + 1 LSB 01 NC
NC: No Change, the same value as the one at the beginning of command execution.
LSB: Least Significant Bit, the LSB of H is complemented.
Write Data
After the Write Data command has been issued,
the FDC loads the head (if it is in the unloaded
state), waits the specified head load time if
unloaded (defined in the Specify command),
and begins reading ID fields. When the sector
address read from the diskette matches the
sector address specified in the command, the
FDC reads the data from the host via the FIFO
and writes it to the sector's data field.
After writing data into the current sector, the
FDC computes the CRC value and writes it into
the CRC field at the end of the sector transfer.
The Sector Number stored in "R" is incremented
by one, and the FDC continues writing to the
next data field. The FDC continues this "MultiSector Write Operation". Upon receipt of a
terminal count signal or if a FIFO over/under run
occurs while a data field is being written, then
the remainder of the data field is filled with
zeros.
The FDC reads the ID field of each sector and
checks the CRC bytes. If it detects a CRC error
in one of the ID fields, it sets the IC code in
Status Register 0 to "01" (abnormal
termination), sets the DE bit of Status Register 1
to "1", and terminates the Write Data command.
The Write Data command operates in much the
same manner as the Read Data command. The
following items are the same. Please refer to
the Read Data Command for details:
!
Transfer Capacity
!
EN (End of Cylinder) bit
!
ND (No Data) bit
!
Head Load, Unload Time Interval
!
ID information when the host terminates the
command
!
Definition of DTL when N = 0 and when N
does not = 0
Write Deleted Data
This command is almost the same as the Write
Data command except that a Deleted Data
Address Mark is written at the beginning of the
Data Field instead of the normal Data Address
Mark. This command is typically used to mark
a bad sector containing an error on the floppy
disk.
60
Page 61
Verify
The Verify command is used to verify the data
stored on a disk. This command acts exactly
like a Read Data command except that no data
is transferred to the host. Data is read from the
disk and CRC is computed and checked against
the previously-stored value.
terminated by setting the EC bit to "0" and the
EOT value equal to the final sector to be
checked. If EC is set to "0", DTL/SC should be
programmed to 0FFH. Refer to Table 26 and
Table 27 for information concerning the values
of MT and EC versus SC and EOT value.
Definitions:
Because data is not transferred to the host, TC
(pin 25) cannot be used to terminate this
# Sectors Per Side = Number of formatted
sectors per each side of the disk.
command. By setting the EC bit to "1", an
implicit TC will be issued to the FDC. This
implicit TC will occur when the SC value has
decremented to 0 (an SC value of 0 will verify
# Sectors Remaining = Number of formatted
sectors left which can be read, including side 1
of the disk if MT is set to "1".
256 sectors). This command can also be
Table 25 - Verify Command Result Phase Table
MT EC SC/EOT VALUE TERMINATION RESULT
0 0 SC = DTL
EOT < # Sectors Per Side
0 0 SC = DTL
EOT > # Sectors Per Side
0 1 SC < # Sectors Remaining AND
EOT < # Sectors Per Side
0 1 SC > # Sectors Remaining OR
EOT > # Sectors Per Side
1 0 SC = DTL
EOT < # Sectors Per Side
1 0 SC = DTL
EOT > # Sectors Per Side
1 1 SC < # Sectors Remaining AND
EOT < # Sectors Per Side
1 1 SC > # Sectors Remaining OR
EOT > # Sectors Per Side
Success Termination
Result Phase Valid
Unsuccessful Termination
Result Phase Invalid
Successful Termination
Result Phase Valid
Unsuccessful Termination
Result Phase Invalid
Successful Termination
Result Phase Valid
Unsuccessful Termination
Result Phase Invalid
Successful Termination
Result Phase Valid
Unsuccessful Termination
Result Phase Invalid
NOTE: If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors
on Side 0, verifying will continue on Side 1 of the disk.
61
Page 62
Format A Track
The Format command allows an entire track to
be formatted. After a pulse from the IDX pin is
detected, the FDC starts writing data on the disk
including gaps, address marks, ID fields, and
data fields per the IBM System 34 or 3740
format (MFM or FM respectively). The particular
values that will be written to the gap and data
field are controlled by the values programmed
into N, SC, GPL, and D which are specified by
the host during the command phase. The data
field of the sector is filled with the data byte
specified by D. The ID field for each sector is
supplied by the host; that is, four data bytes per
sector are needed by the FDC for C, H, R, and
N (cylinder, head, sector number and sector size
respectively).
FORMAT FIELDS
SYSTEM 34 (DOUBLE DENSITY) FORMAT
GAP4a
80x
4E
SYNC
IAM GAP1
12x
00
3xC2FC 3xA1FE 3xA1FB
50x
4E
SYNC
12x
00
IDAM C
HDS
Y
L
After formatting each sector, the host must send
new values for C, H, R and N to the FDC for the
next sector on the track. The R value (sector
number) is the only value that must be changed
by the host after each sector is formatted. This
allows the disk to be formatted with
nonsequential sector addresses (interleaving).
This incrementing and formatting continues for
the whole track until the FDC encounters a pulse
on the IDX pin again and it terminates the
command.
Table 28 contains typical values for gap fields
which are dependent upon the size of the sector
and the number of sectors on each track. Actual
values can vary due to drive electronics.
NOC
E
C
GAP2
R
22x
C
4E
SYNC
12x
00
DATA
AM
DATACRCGAP3 GAP 4b
F8
GAP4a
40x
FF
GAP4a
80x
4E
SYSTEM 3740 (SINGLE DENSITY) FORMAT
SYNC
IAM GAP1
6x
00
FC FE FB or
26x
FF
SYNC
6x
00
IDAM C
HDS
NOC
Y
E
L
C
GAP2
R
11x
C
FF
PERPENDICULAR FORMAT
SYNC
IAM GAP1
12x
00
3xC2FC 3xA1FE 3xA1FB
50x
4E
SYNC
12x
00
IDAM C
HDS
NOC
Y
E
L
C
GAP2
R
41x
C
4E
62
SYNC
6x
00
SYNC
12x
00
DATA
AM
DATACRCGAP3 GAP 4b
F8
DATA
AM
DATACRCGAP3 GAP 4b
F8
Page 63
Table 26 - Typical Values for Formatting
FORMAT SECTOR SIZE N SC GPL1 GPL2
128
128
512
FM
5.25"
Drives
MFM
3.5"
Drives
GPL1 = suggested GPL values in Read and Write commands to avoid splice point
between data field and ID field of contiguous sections.
GPL2 = suggested GPL value in Format A Track command.
*PC/AT values (typical)
**PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives.
NOTE: All values except sector size are in hex.
FM
MFM
1024
2048
4096
...
256
256
512*
1024
2048
4096
...
128
256
512
256
512**
1024
00
00
02
03
04
05
...
01
01
02
03
04
05
...
12
10
08
04
02
01
12
10
09
04
02
01
0
1
2
1
2
3
0F
09
05
0F
09
05
07
10
18
46
C8
C8
0A
20
2A
80
C8
C8
07
0F
1B
0E
1B
35
09
19
30
87
FF
FF
0C
32
50
F0
FF
FF
1B
2A
3A
36
54
74
63
Page 64
CONTROL COMMANDS
Control commands differ from the other
commands in that no data transfer takes place.
Three commands generate an interrupt when
complete: Read ID, Recalibrate, and Seek. The
other control commands do not generate an
interrupt.
Read ID
The Read ID command is used to find the
present position of the recording heads. The
FDC stores the values from the first ID field it is
able to read into its registers. If the FDC does
not find an ID address mark on the diskette after
the second occurrence of a pulse on the
nINDEX pin, it then sets the IC code in Status
Register 0 to "01" (abnormal termination), sets
the MA bit in Status Register 1 to "1", and
terminates the command.
The following commands will generate an
interrupt upon completion. They do not return
any result bytes. It is highly recommended that
control commands be followed by the Sense
Interrupt Status command. Otherwise, valuable
interrupt status information will be lost.
Recalibrate
This command causes the read/write head
within the FDC to retract to the track 0 position.
The FDC clears the contents of the PCN counter
and checks the status of the nTR0 pin from the
FDD. As long as the nTR0 pin is low, the DIR
pin remains 0 and step pulses are issued. When
the nTR0 pin goes high, the SE bit in Status
Register 0 is set to "1" and the command is
terminated. If the nTR0 pin is still low after 79
step pulses have been issued, the FDC sets the
SE and the EC bits of Status Register 0 to "1"
and terminates the command. Disks capable of
handling more than 80 tracks per side may
require more than one Recalibrate command to
return the head back to physical Track 0.
The Recalibrate command does not have a
result phase. The Sense Interrupt Status
command must be issued after the Recalibrate
command to effectively terminate it and to
provide verification of the head position (PCN).
During the command phase of the recalibrate
operation, the FDC is in the BUSY state, but
during the execution phase it is in a NON-BUSY
state. At this time, another Recalibrate
command may be issued, and in this manner
parallel Recalibrate operations may be done on
up to four drives at once.
Upon power up, the software must issue a
Recalibrate command to properly initialize all
drives and the controller.
Seek
The read/write head within the drive is moved
from track to track under the control of the Seek
command. The FDC compares the PCN, which
is the current head position, with the NCN and
performs the following operation if there is a
difference:
PCN < NCN: Direction signal to drive set to
"1" (step in) and issues step
pulses.
PCN > NCN: Direction signal to drive set to
"0" (step out) and issues step
pulses.
The rate at which step pulses are issued is
controlled by SRT (Stepping Rate Time) in the
Specify command. After each step pulse is
issued, NCN is compared against PCN, and
when NCN = PCN the SE bit in Status Register
0 is set to "1" and the command is terminated.
During the command phase of the seek or
recalibrate operation, the FDC is in the BUSY
state, but during the execution phase it is in the
NON-BUSY state. At this time, another Seek or
Recalibrate command may be issued, and in
this manner, parallel seek operations may be
done on up to four drives at once.
64
Page 65
Note that if implied seek is not enabled, the read
and write commands should be preceded by:
1) Seek command - Step to the proper track
2) Sense Interrupt Status command Terminate the Seek command
3) Read ID - Verify head is on proper track
4) Issue Read/Write command.
The Seek command does not have a result
phase. Therefore, it is highly recommended that
the Sense Interrupt Status command be issued
after the Seek command to terminate it and to
provide verification of the head position (PCN).
The H bit (Head Address) in ST0 will always
return to a "0". When exiting POWERDOWN
mode, the FDC clears the PCN value and the
status information to zero. Prior to issuing the
POWERDOWN command, it is highly
recommended that the user service all pending
interrupts through the Sense Interrupt Status
command.
Table 27 - Interrupt Identification
SE IC INTERRUPT DUE TO
0
11
Polling
1
00
Normal termination of Seek
or Recalibrate command
Abnormal termination of
1
01
Seek or Recalibrate
command
The Seek, Relative Seek, and Recalibrate
commands have no result phase. The Sense
Interrupt Status command must be issued
immediately after these commands to terminate
them and to provide verification of the head
position (PCN). The H (Head Address) bit in
ST0 will always return a "0". If a Sense Interrupt
Status is not issued, the drive will continue to be
BUSY and may affect the operation of the next
command.
Sense Drive Status
Sense Interrupt Status
An interrupt signal on FINT pin is generated by
the FDC for one of the following reasons:
1. Upon entering the Result Phase of:
a. Read Data command
b. Read A Track command
c. Read ID command
d. Read Deleted Data command
e. Write Data command
f. Format A Track command
g. Write Deleted Data command
h. Verify command
2. End of Seek, Relative Seek, or Recalibrate
command
3. FDC requires a data transfer during the
execution phase in the non-DMA mode
The Sense Interrupt Status command resets the
interrupt signal and, via the IC code and SE bit
of Status Register 0, identifies the cause of the
interrupt.
Sense Drive Status obtains drive status
information. It has not execution phase and
goes directly to the result phase from the
command phase. Status Register 3 contains
the drive status information.
Specify
The Specify command sets the initial values for
each of the three internal times. The HUT
(Head Unload Time) defines the time from the
end of the execution phase of one of the
read/write commands to the head unload state.
The SRT (Step Rate Time) defines the time
interval between adjacent step pulses. Note that
the spacing between the first and second step
pulses may be shorter than the remaining step
pulses. The HLT (Head Load Time) defines the
time between when the Head Load signal goes
high and the read/write operation starts.
65
Page 66
The values change with the data rate speed
selection and are documented in Table 30. The
Table 28 - Drive Control Delays (ms)
HUT SRT
2M 1M 500K 300K 250K 2M 1M 500K 300K 250K
0
64
E
F
00
01
02
7F
7F
128
1
4
..
..
56
112
60
120
2M 1M 500K 300K 250K
64
0.5
1
..
..
63
63.5
256
8
16
..
224
240
426
26.7
..
..
373
400
128
1
2
..
126
127
values are the same for MFM and FM.
512
32
..
448
480
256
2
4
..
252
254
4
3.75
..
0.5
0.25
HLT
8
7.5
..
1
0.5
16
15
..
2
1
426
3.3
6.7
..
420
423
26.7
25
..
3.33
1.67
32
30
..
4
2
512
4
8
.
504
508
The choice of DMA or non-DMA operations is
made by the ND bit. When this bit is "1", the
non-DMA mode is selected, and when ND is "0",
the DMA mode is selected. In DMA mode, data
transfers are signaled by the FDRQ pin. NonDMA mode uses the RQM bit and the FINT pin
to signal data transfers.
Configure
The Configure command is issued to select the
special features of the FDC. A Configure
command need not be issued if the default
values of the FDC meet the system
requirements.
Configure Default Values:
EIS - No Implied Seeks
EFIFO - FIFO Disabled
POLL - Polling Enabled
FIFOTHR - FIFO Threshold Set to 1 Byte
PRETRK - Pre-Compensation Set to Track 0
EIS - Enable Implied Seek. When set to "1", the
FDC will perform a Seek operation before
executing a read or write command. Defaults to
no implied seek.
EFIFO - A "1" disables the FIFO (default). This
means data transfers are asked for on a byteby-byte basis. Defaults to "1", FIFO disabled.
The threshold defaults to "1".
POLL - Disable polling of the drives. Defaults to
"0", polling enabled. When enabled, a single
interrupt is generated after a reset. No polling is
performed while the drive head is loaded and
the head unload delay has not expired.
FIFOTHR - The FIFO threshold in the execution
phase of read or write commands. This is
programmable from 1 to 16 bytes. Defaults to
one byte. A "00" selects one byte; "0F" selects
16 bytes.
66
Page 67
PRETRK - Pre-Compensation Start Track
Number. Programmable from track 0 to 255.
Defaults to track 0. A "00" selects track 0; "FF"
selects track 255.
Version
The Version command checks to see if the
controller is an enhanced type or the older type
(765A). A value of 90 H is returned as the result
byte.
Relative Seek
The command is coded the same as for Seek,
except for the MSB of the first byte and the DIR
bit.
DIR Head Step Direction Control
DIR ACTION
01Step Head Out
Step Head In
RCN Relative Cylinder Number that
determines how many tracks to step the
head in or out from the current track
number.
The Relative Seek command differs from the
Seek command in that it steps the head the
absolute number of tracks specified in the
command instead of making a comparison
against an internal register. The Seek
command is good for drives that support a
maximum of 256 tracks. Relative Seeks cannot
be overlapped with other Relative Seeks. Only
one Relative Seek can be active at a time.
Relative Seeks may be overlapped with Seeks
and Recalibrates. Bit 4 of Status Register 0
(EC) will be set if Relative Seek attempts to step
outward beyond Track 0.
As an example, assume that a floppy drive has
300 useable tracks. The host needs to read
track 300 and the head is on any track (0-255).
If a Seek command is issued, the head will stop
at track 255. If a Relative Seek command is
issued, the FDC will move the head the
specified number of tracks, regardless of the
internal cylinder position register (but will
increment the register). If the head was on track
40 (d), the maximum track that the FDC could
position the head on using Relative Seek will be
295 (D), the initial track + 255 (D). The
maximum count that the head can be moved
with a single Relative Seek command is 255
(D).
The internal register, PCN, will overflow as the
cylinder number crosses track 255 and will
contain 39 (D). The resulting PCN value is thus
(RCN + PCN) mod 256. Functionally, the FDC
starts counting from 0 again as the track
number goes above 255 (D). It is the user's
responsibility to compensate FDC functions
(precompensation track number) when
accessing tracks greater than 255. The FDC
does not keep track that it is working in an
"extended track area" (greater than 255). Any
command issued will use the current PCN value
except for the Recalibrate command, which only
looks for the TRACK0 signal. Recalibrate will
return an error if the head is farther than 79 due
to its limitation of issuing a maximum of 80 step
pulses. The user simply needs to issue a
second Recalibrate command. The Seek
command and implied seeks will function
correctly within the 44 (D) track (299-255) area
of the "extended track area". It is the user's
responsibility not to issue a new track position
that will exceed the maximum track that is
present in the extended area.
To return to the standard floppy range (0-255) of
tracks, a Relative Seek should be issued to
cross the track 255 boundary.
A Relative Seek can be used instead of the
normal Seek, but the host is required to
calculate the difference between the current
head location and the new (target) head
location. This may require the host to issue a
Read ID command to ensure that the head is
physically on the track that software assumes it
to be. Different FDC commands will return
different cylinder results which may be difficult
67
Page 68
to keep track of with software without the Read
ID command.
Perpendicular Mode
The Perpendicular Mode command should be
issued prior to executing Read/Write/Format
commands that access a disk drive with
perpendicular recording capability. With this
command, the length of the Gap2 field and VCO
enable timing can be altered to accommodate
the unique requirements of these drives. Table
31 describes the effects of the WGATE and
GAP bits for the Perpendicular Mode command.
Upon a reset, the FDC will default to the
conventional mode (WGATE = 0, GAP = 0).
Selection of the 500 Kbps and 1 Mbps
perpendicular modes is independent of the
actual data rate selected in the Data Rate Select
Register. The user must ensure that these two
data rates remain consistent.
The Gap2 and VCO timing requirements for
perpendicular recording type drives are dictated
by the design of the read/write head. In the
design of this head, a pre-erase head precedes
the normal read/write head by a distance of 200
micrometers. This works out to about 38 bytes
at a 1 Mbps recording density. Whenever the
write head is enabled by the Write Gate signal,
the pre-erase head is also activated at the same
time. Thus, when the write head is initially
turned on, flux transitions recorded on the media
for the first 38 bytes will not be preconditioned
with the pre-erase head since it has not yet been
activated. To accommodate this head activation
and deactivation time, the Gap2 field is
expanded to a length of 41 bytes. The format
field shown on page 61 illustrates the change in
the Gap2 field size for the perpendicular format.
On the read back by the FDC, the controller
must begin synchronization at the beginning of
the sync field. For the conventional mode, the
internal PLL VCO is enabled (VCOEN)
approximately 24 bytes from the start of the
Gap2 field. But, when the controller operates in
the 1 Mbps perpendicular mode (WGATE = 1,
GAP = 1), VCOEN goes active after 43 bytes to
accommodate the increased Gap2 field size.
For both cases, and approximate two-byte
cushion is maintained from the beginning of the
sync field for the purposes of avoiding write
splices in the presence of motor speed variation.
For the Write Data case, the FDC activates
Write Gate at the beginning of the sync field
under the conventional mode. The controller
then writes a new sync field, data address mark,
data field, and CRC as shown in Figure 4. With
the pre-erase head of the perpendicular drive,
the write head must be activated in the Gap2
field to insure a proper write of the new sync
field. For the 1 Mbps perpendicular mode
(WGATE = 1, GAP = 1), 38 bytes will be written
in the Gap2 space. Since the bit density is
proportional to the data rate, 19 bytes will be
written in the Gap2 field for the 500 Kbps
perpendicular mode (WGATE = 1, GAP =0).
It should be noted that none of the alterations in
Gap2 size, VCO timing, or Write Gate timing
affect normal program flow. The information
provided here is just for background purposes
and is not needed for normal operation. Once
the Perpendicular Mode command is invoked,
FDC software behavior from the user standpoint
is unchanged.
The perpendicular mode command is enhanced
to allow specific drives to be designated
Perpendicular recording drives. This
enhancement allows data transfers between
Conventional and Perpendicular drives without
having to issue Perpendicular mode commands
between the accesses of the different drive
types, nor having to change write precompensation values.
68
Page 69
When both GAP and WGATE bits of the
PERPENDICULAR MODE COMMAND are both
programmed to "0" (Conventional mode), then
D0, D1, D2, D3, and D4 can be programmed
independently to "1" for that drive to be set
automatically to Perpendicular mode. In this
mode the following set of conditions also apply:
1. The GAP2 written to a perpendicular drive
during a write operation will depend upon the
programmed data rate.
2. The write pre-compensation given to a
perpendicular mode drive wil be 0ns.
3. For D0-D3 programmed to "0" for
conventional mode drives any data written
will be at the currently programmed write
pre-compensation.
Table 29 - Effects of WGATE and GAP Bits
WGATE GAP MODE
0
0
0
Conventional
1
Perpendicular
(500 Kbps)
1
0
Reserved
(Conventional)
1
1
Perpendicular
(1 Mbps)
Note: Bits D0-D3 can only be overwritten when
OW is programmed as a "1".
If either GAP or WGATE is a "1" then
D0-D3 are ignored.
Software and hardware resets have the
following effect on the PERPENDICULAR
MODE COMMAND:
1. "Software" resets (via the DOR or DSR
registers) will only clear GAP and WGATE
bits to "0". D0-D3 are unaffected and retain
their previous value.
2. "Hardware" resets will clear all bits (GAP,
WGATE and D0-D3) to "0", i.e all
conventional mode.
PORTION OF
GAP 2
LENGTH OF
GAP2 FORMAT
FIELD
22 Bytes
22 Bytes
22 Bytes
41 Bytes
WRITTEN BY
WRITE DATA
OPERATION
0 Bytes
19 Bytes
0 Bytes
38 Bytes
LOCK
In order to protect systems with long DMA
latencies against older application software that
can disable the FIFO the LOCK Command has
been added. This command should only be
used by the FDC routines, and application
software should refrain from using it. If an
application calls for the FIFO to be disabled
then the CONFIGURE command should be
used.
The LOCK command defines whether the
EFIFO, FIFOTHR, and PRETRK parameters of
the CONFIGURE command can be RESET by
the DOR and DSR registers. When the LOCK
bit is set to logic "1" all subsequent "software
RESETS by the DOR and DSR registers will not
change the previously set parameters to their
default values. All "hardware" RESET from the
RESET pin will set the LOCK bit to logic "0" and
return the EFIFO, FIFOTHR, and PRETRK to
69
Page 70
their default values. A status byte is returned
immediately after issuing a LOCK command.
This byte reflects the value of the LOCK bit set
by the command byte.
ENHANCED DUMPREG
The DUMPREG command is designed to
support system run-time diagnostics and
application software development and debug.
To accommodate the LOCK command and the
enhanced PERPENDICULAR MODE command
the eighth byte of the DUMPREG command has
been modified to contain the additional data
from these two commands.
COMPATIBILITY
The FDC37C669 was designed with software
compatibility in mind. It is a fully backwardscompatible solution with the older generation
765A/B disk controllers. The FDC also
implements on-board registers for compatibility
with the PS/2, as well as PC/AT and PC/XT,
floppy disk controller subsystems. After a
hardware reset of the FDC, all registers,
functions and enhancements default to a PC/AT,
PS/2 or PS/2 Model 30 compatible operating
mode, depending on how the IDENT and MFM
bits are configured by the system bios.
70
Page 71
PARALLEL PORT FLOPPY DISK CONTROLLER
In this mode, the Floppy Disk Control signals
are available on the parallel port pins. When
this mode is selected, the parallel port is not
available. There are two modes of operation,
PPFD1 and PPFD2. These modes can be
selected in Configuration Register 4. PPFD1
has only drive 1 on the parallel port pins; PPFD2
has drive 0 and 1 on the parallel port pins.
PPFD1: Drive 0 is on the FDC pins
Drive 1 is on the Parallel port pins
PPFD2: Drive 0 is on the Parallel port pins
Drive 1 is on the Parallel port pins
When the PPFDC is selected the following pins
are set as follows:
1. nDACK: Assigned to the parallel port device
during configuration.
2. PDRQ (assigned to the parallel port): not
ECP = high-Z, ECP & dmaEn = 0, ECP &
not dmaEn = high-Z
3. IRQ assigned to the parallel port: not active,
this is hi-Z or Low depending on settings.
The following parallel port pins are read as
follows by a read of the parallel port register:
1. Data Register (read) = last Data Register
(write)
2. Control Register are read as "cable not
connected" STROBE, AUTOFD and SLC =
0 and nINIT = 1;
3. Status Register reads: nBUSY = 0, PE = 0,
SLCT = 0, nACK = 1, nERR = 1.
The following FDC pins are all in the high
impedence state when the PPFDC is actually
selected by the drive select register:
1. nWDATA, DENSEL, nHDSEL, nWGATE,
nDIR, nSTEP, nDS1, nDS0, nMTRO,
nMTR1.
2. If PPFDx is selected, then the parallel port
can not be used as a parallel port until
"Normal" mode is selected.
The FDC signals are muxed onto the Parallel
Port pins as shown in Table 32.
71
Page 72
Table 30 - FDC Parallel Port Pins
CONNECTOR
PIN # CHIP PIN # SPP MODE PIN DIRECTION FDC MODE PIN DIRECTION
1 77 nSTB I/O (nDS0) I/(0)
2 71 PD0 I/O nINDEX I
3 70 PD1 I/O nTRKO I
4 69 PD2 I/O nWP I
5 68 PD3 I/O nRDATA I
6 66 PD4 I/O nDSKCHG I
7 65 PD5 I/O nMEDIA_ID0 I
8 64 PD6 I/O (nMTR0) I/(0)
9 63 PD7 I/O nMEDIA_ID1 I
10 62 nACK I nDS1 0
11 61 BUSY I nMTR1 0
12 60 PE I nWDATA 0
13 59 SLCT I nWGATE 0
14 76 nAFD I/O nDENSEL 0
15 75 nERR I nHDSEL 0
16 74 nINIT I/O nDIR 0
17 73 nSLIN I/O nSTEP 0
These pins are outputs in mode PPFD2. Inputs in mode PPFD1
72
Page 73
SERIAL PORT (UART)
The FDC37C669 incorporates two full function
UARTs. They are compatible with the
NS16450, the 16450 ACE registers and the
NS16550A. The UARTs perform serial-toparallel conversion on received characters and
parallel-to-serial conversion on transmit
characters. The data rates are independently
programmable from 115.2K baud down to 50
baud. The character options are programmable
for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky
or no parity; and prioritized interrupts. The
UARTs each contain a programmable baud rate
generator that is capable of dividing the input
clock or crystal by a number from 1 to 65535.
The UARTs are also capable of supporting the
MIDI data rate. Refer to the FDC37C669
Configuration Registers for information on
Table 31 - Addressing the Serial Port
DLAB* A2 A1 A0 REGISTER NAME
0 0 0 0 Receive Buffer (read)
0 0 0 0 Transmit Buffer (write)
0 0 0 1 Interrupt Enable (read/write)
X 0 1 0 Interrupt Identification (read)
X 0 1 0 FIFO Control (write)
X 0 1 1 Line Control (read/write)
X 1 0 0 Modem Control (read/write)
X 1 0 1 Line Status (read/write)
X 1 1 0 Modem Status (read/write)
X 1 1 1 Scratchpad (read/write)
1 0 0 0 Divisor LSB (read/write)
1 0 0 1 Divisor MSB (read/write)
disabling, power down and changing the base
address of the UARTs. The interrupt from a
UART is enabled by programming OUT2 of that
UART to a logic "1". OUT2 being a logic "0"
disables that UART's interrupt.
REGISTER DESCRIPTION
Addressing of the accessible registers of the
Serial Port is shown below. The base
addresses of the serial ports are defined by the
configuration registers (see Configuration
section). The Serial Port registers are located at
sequentially increasing addresses above these
base addresses. The FDC37C669 contains two
serial ports, each of which contain a register set
as described below.
*NOTE: DLAB is Bit 7 of the Line Control Register
73
Page 74
The following section describes the operation of
the registers.
RECEIVE BUFFER REGISTER (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data
byte. Bit 0 is the least significant bit, which is
transmitted and received first. Received data is
double buffered; this uses an additional shift
register to receive the serial data stream and
convert it to a parallel 8 bit word which is
transferred to the Receive Buffer register. The
shift register is not accessible.
TRANSMIT BUFFER REGISTER (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY
This register contains the data byte to be
transmitted. The transmit buffer is double
buffered, utilizing an additional shift register (not
accessible) to convert the 8 bit data word to a
serial format. This shift register is loaded from
the Transmit Buffer when the transmission of
the previous byte is complete.
INTERRUPT ENABLE REGISTER (IER)
Address Offset = 1H, DLAB = 0, READ/WRITE
The lower four bits of this register control the
enables of the five interrupt sources of the Serial
Port interrupt. It is possible to totally disable the
interrupt system by resetting bits 0 through 3 of
this register. Similarly, setting the appropriate
bits of this register to a high, selected interrupts
can be enabled. Disabling the interrupt system
inhibits the Interrupt Identification Register and
disables any Serial Port interrupt out of the
FDC37C669. All other system functions operate
in their normal manner, including the Line
Status and MODEM Status Registers. The
contents of the Interrupt Enable Register are
described below.
Bit 0
This bit enables the Received Data Available
Interrupt (and timeout interrupts in the FIFO
mode) when set to logic "1".
Bit 1
This bit enables the Transmitter Holding
Register Empty Interrupt when set to logic "1".
Bit 2
This bit enables the Received Line Status
Interrupt when set to logic "1". The error
sources causing the interrupt are Overrun,
Parity, Framing and Break. The Line Status
Register must be read to determine the source.
Bit 3
This bit enables the MODEM Status Interrupt
when set to logic "1". This is caused when one
of the Modem Status Register bits changes
state.
Bits 4 through 7
These bits are always logic "0".
FIFO CONTROL REGISTER (FCR)
Address Offset = 2H, DLAB = X, WRITE
This is a write only register at the same location
as the IIR. This register is used to enable and
clear the FIFOs, set the RCVR FIFO trigger
level. Note: DMA is not supported.
Bit 0
Setting this bit to a logic "1" enables both the
XMIT and RCVR FIFOs. Clearing this bit to a
logic "0" disables both the XMIT and RCVR
FIFOs and clears all bytes from both FIFOs.
When changing from FIFO Mode to non-FIFO
(16450) mode, data is automatically cleared
from the FIFOs. This bit must be a 1 when
other bits in this register are written to or they
will not be properly programmed.
Bit 1
Setting this bit to a logic "1" clears all bytes in
the RCVR FIFO and resets its counter logic to 0.
The shift register is not cleared. This bit is selfclearing.
74
Page 75
Bit 2
Setting this bit to a logic "1" clears all bytes in
the XMIT FIFO and resets its counter logic to 0.
The shift register is not cleared. This bit is selfclearing.
Bit 3
Writing to this bit has no effect on the operation
of the UART. The RXRDY and TXRDY pins are
not available on this chip.
Bit 4,5
Reserved
Bit 6,7
These bits are used to set the trigger level for
the RCVR FIFO interrupt.
RCVR FIFO
Bit 7 Bit 6
Trigger Level
(BYTES)
0 0 1
0 1 4
1 0 8
1 1 14
3. Transmitter Holding Register Empty
4. MODEM Status (lowest priority)
Information indicating that a prioritized interrupt
is pending and the source of that interrupt is
stored in the Interrupt Identification Register
(refer to Interrupt Control Table). When the
CPU accesses the IIR, the Serial Port freezes all
interrupts and indicates the highest priority
pending interrupt to the CPU. During this CPU
access, even if the Serial Port records new
interrupts, the current indication does not
change until access is completed. The contents
of the IIR are described below.
Bit 0
This bit can be used in either a hardwired
prioritized or polled environment to indicate
whether an interrupt is pending. When bit 0 is a
logic "0", an interrupt is pending and the
contents of the IIR may be used as a pointer to
the appropriate internal service routine. When
bit 0 is a logic "1", no interrupt is pending.
Bits 1 and 2
These two bits of the IIR are used to identify the
highest priority interrupt pending as indicated by
the Interrupt Control Table.
INTERRUPT IDENTIFICATION REGISTER
(IIR)
Address Offset = 2H, DLAB = X, READ
By accessing this register, the host CPU can
determine the highest priority interrupt and its
source. Four levels of priority interrupt exist.
They are in descending order of priority:
1. Receiver Line Status (highest priority)
2. Received Data Ready
Bit 3
In non-FIFO mode, this bit is a logic "0". In
FIFO mode this bit is set along with bit 2 when a
timeout interrupt is pending.
Bits 4 and 5
These bits of the IIR are always logic "0".
Bits 6 and 7
These two bits are set when the FIFO
CONTROL Register bit 0 equals 1.
75
Page 76
Table 32 - Interrupt Control Table
FIFO
MODE
ONLY
BIT 3 BIT 2 BIT 1 BIT 0
INTERRUPT
IDENTIFICATION
REGISTER
PRIORITY
LEVEL
INTERRUPT SET AND RESET FUNCTIONS
INTERRUPT
TYPE
INTERRUPT
SOURCE
RESET CONTROL
0 0 0 1 - None None 0 1 1 0 Highest Receiver Line
Status
Overrun Error,
Parity Error,
Reading the Line
Status Register
Framing Error or
Break Interrupt
0 1 0 0 Second Received Data
Available
Receiver Data
Available
Read Receiver
Buffer or the FIFO
drops below the
trigger level.
1 1 0 0 Second Character
Timeout
Indication
No Characters
Have Been
Removed From
Reading the
Receiver Buffer
Register
or Input to the
RCVR FIFO
during the last 4
Char times and
there is at least 1
char in it during
this time
0 0 1 0 Third Transmitter
Holding
Register
Empty
Transmitter
Holding Register
Empty
Reading the IIR
Register (if Source
of Interrupt) or
Writing the
Transmitter
Holding Register
0 0 0 0 Fourth MODEM
Status
Clear to Send or
Data Set Ready
or Ring Indicator
Reading the
MODEM Status
Register
or Data Carrier
Detect
INTERRUPT
76
Page 77
LINE CONTROL REGISTER (LCR)
BIT 0
WORD LENGTH
Address Offset = 3H, DLAB = 0, READ/WRITE
This register contains the format information of
the serial line. The bit definitions are:
checked (receive data) between the last data
word bit and the first stop bit of the serial data.
(The parity bit is used to generate an even or
odd number of 1s when the data word bits and
the parity bit are summed).
Bits 0 and 1
These two bits specify the number of bits in
each transmitted or received serial character.
The encoding of bits 0 and 1 is as follows:
BIT 1
0
0
1
1
0
1
0
1
5 Bits
6 Bits
7 Bits
8 Bits
The Start, Stop and Parity bits are not included
in the word length.
Bit 2
This bit specifies the number of stop bits in each
transmitted or received serial character. The
following table summarizes the information.
NUMBER OF
BIT 2 WORD LENGTH
STOP BITS
0 -- 1
1 5 bits 1.5
1 6 bits 2
1 7 bits 2
1 8 bits 2
Bit 4
Even Parity Select bit. When bit 3 is a logic "1"
and bit 4 is a logic "0", an odd number of logic
"1"'s is transmitted or checked in the data word
bits and the parity bit. When bit 3 is a logic "1"
and bit 4 is a logic "1" an even number of bits is
transmitted and checked.
Bit 5
Stick Parity bit. When bit 3 is a logic "1" and bit
5 is a logic "1", the parity bit is transmitted and
then detected by the receiver in the opposite
state indicated by bit 4.
Bit 6
Set Break Control bit. When bit 6 is a logic "1",
the transmit data output (TXD) is forced to the
Spacing or logic "0" state and remains there
(until reset by a low level bit 6) regardless of
other transmitter activity. This feature enables
the Serial Port to alert a terminal in a
communications system.
Bit 7
Divisor Latch Access bit (DLAB). It must be set
high (logic "1") to access the Divisor Latches of
the Baud Rate Generator during read or write
operations. It must be set low (logic "0") to
access the Receiver Buffer Register, the
Transmitter Holding Register, or the Interrupt
Enable Register.
Note: The receiver will ignore all stop bits
beyond the first, regardless of the number used
in transmitting.
Bit 3
Parity Enable bit. When bit 3 is a logic "1", a
parity bit is generated (transmit data) or
MODEM CONTROL REGISTER (MCR)
Address Offset = 4H, DLAB = X,
READ/WRITE
This 8 bit register controls the interface with the
MODEM or data set (or device emulating a
MODEM). The contents of the MODEM control
register are described below.
77
Page 78
Bit 0
This bit controls the Data Terminal Ready
(nDTR) output. When bit 0 is set to a logic
"1", the nDTR output is forced to a logic "0".
When bit 0 is a logic "0", the nDTR output is
forced to a logic "1".
Bit 1
This bit controls the Request To Send (nRTS)
output. Bit 1 affects the nRTS output in a
manner identical to that described above for bit
0.
Bit 2
This bit controls the Output 1 (OUT1) bit. This
bit does not have an output pin and can only be
read or written by the CPU.
Bit 3
Output 2 (OUT2). This bit is used to enable an
UART interrupt. When OUT2 is a logic "0", the
serial port interrupt output is forced to a high
impedance state - disabled. When OUT2 is a
logic "1", the serial port interrupt outputs are
enabled.
Bit 4
This bit provides the loopback feature for
diagnostic testing of the Serial Port. When bit 4
is set to logic "1", the following occur:
1. The TXD is set to the Marking State(logic
"1").
2. The receiver Serial Input (RXD) is
disconnected.
3. The output of the Transmitter Shift Register
is "looped back" into the Receiver Shift
Register input.
4. All MODEM Control inputs (nCTS, nDSR,
nRI and nDCD) are disconnected.
5. The four MODEM Control outputs (nDTR,
nRTS, OUT1 and OUT2) are internally
connected to the four MODEM Control inputs
(nDSR, nCTS, RI and DCD) respectively.
6. The Modem Control output pins are forced
inactive high.
7. Data that is transmitted is immediately
received.
This feature allows the processor to verify the
transmit and receive data paths of the Serial
Port. In the diagnostic mode, the receiver and
the transmitter interrupts are fully operational.
The MODEM Control Interrupts are also
operational but the interrupts' sources are now
the lower four bits of the MODEM Control
Register instead of the MODEM Control inputs.
The interrupts are still controlled by the Interrupt
Enable Register.
Bits 5 through 7
These bits are permanently set to logic zero.
LINE STATUS REGISTER (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE
Bit 0
Data Ready (DR). It is set to a logic "1"
whenever a complete incoming character has
been received and transferred into the Receiver
Buffer Register or the FIFO. Bit 0 is reset to a
logic "0" by reading all of the data in the Receive
Buffer Register or the FIFO.
Bit 1
Overrun Error (OE). Bit 1 indicates that data in
the Receiver Buffer Register was not read before
the next character was transferred into the
register, thereby destroying the previous
character. In FIFO mode, an overrunn error will
occur only when the FIFO is full and the next
character has been completely received in the
shift register, the character in the shift register is
overwritten but not transferred to the FIFO. The
OE indicator is set to a logic "1" immediately
upon detection of an overrun condition, and
reset whenever the Line Status Register is read.
Bit 2
Parity Error (PE). Bit 2 indicates that the
received data character does not have the
correct even or odd parity, as selected by the
even parity select bit. The PE is set to a logic
"1" upon detection of a parity error and is reset
to a logic "0" whenever the Line Status Register
is read. In the FIFO mode this error is
associated with the particular character in the
FIFO it applies to. This error is indicated when
78
Page 79
the associated character is at the top of the
FIFO.
Bit 3
Framing Error (FE). Bit 3 indicates that the
received character did not have a valid stop bit.
Bit 3 is set to a logic "1" whenever the stop bit
following the last data bit or parity bit is detected
as a zero bit (Spacing level). The FE is reset to
a logic "0" whenever the Line Status Register is
read. In the FIFO mode this error is associated
with the particular character in the FIFO it
applies to. This error is indicated when the
associated character is at the top of the FIFO.
The Serial Port will try to resynchronize after a
framing error. To do this, it assumes that the
framing error was due to the next start bit, so it
samples this 'start' bit twice and then takes in
the 'data'.
Bit 4
Break Interrupt (BI). Bit 4 is set to a logic "1"
whenever the received data input is held in the
Spacing state (logic "0") for longer than a full
word transmission time (that is, the total time of
the start bit + data bits + parity bits + stop bits).
The BI is reset after the CPU reads the contents
of the Line Status Register. In the FIFO mode
this error is associated with the particular
character in the FIFO it applies to. This error is
indicated when the associated character is at
the top of the FIFO. When break occurs only
one zero character is loaded into the FIFO.
Restarting after a break is received, requires the
serial data (RXD) to be logic "1" for at least 1/2
bit time.
Note: Bits 1 through 4 are the error conditions
that produce a Receiver Line Status Interrupt
whenever any of the corresponding conditions
are detected and the interrupt is enabled.
Bit 5
Transmitter Holding Register Empty (THRE).
Bit 5 indicates that the Serial Port is ready to
accept a new character for transmission. In
addition, this bit causes the Serial Port to issue
an interrupt when the Transmitter Holding
Register interrupt enable is set high. The THRE
bit is set to a logic "1" when a character is
transferred from the Transmitter Holding
Register into the Transmitter Shift Register. The
bit is reset to logic "0" whenever the CPU loads
the Transmitter Holding Register. In the FIFO
mode this bit is set when the XMIT FIFO is
empty, it is cleared when at least 1 byte is
written to the XMIT FIFO. Bit 5 is a read only
bit.
Bit 6
Transmitter Empty (TEMT). Bit 6 is set to a
logic "1" whenever the Transmitter Holding
Register (THR) and Transmitter Shift Register
(TSR) are both empty. It is reset to logic "0"
whenever either the THR or TSR contains a data
character. Bit 6 is a read only bit. In the FIFO
mode this bit is set whenever the THR and TSR
are both empty,
Bit 7
This bit is permanently set to logic "0" in the 450
mode. In the FIFO mode, this bit is set to a
logic "1" when there is at least one parity error,
framing error or break indication in the FIFO.
This bit is cleared when the LSR is read if there
are no subsequent errors in the FIFO.
MODEM STATUS REGISTER (MSR)
Address Offset = 6H, DLAB = X, READ/WRITE
This 8 bit register provides the current state of
the control lines from the MODEM (or peripheral
device). In addition to this current state
information, four bits of the MODEM Status
Register (MSR) provide change information.
These bits are set to logic "1" whenever a
control input from the MODEM changes state.
They are reset to logic "0" whenever the
MODEM Status Register is read.
79
Page 80
Bit 0
Delta Clear To Send (DCTS). Bit 0 indicates
that the nCTS input to the chip has changed
state since the last time the MSR was read.
Bit 1
Delta Data Set Ready (DDSR). Bit 1 indicates
that the nDSR input has changed state since
the last time the MSR was read.
Bit 2
Trailing Edge of Ring Indicator (TERI). Bit 2
indicates that the nRI input has changed from
logic "0" to logic "1".
Bit 3
Delta Data Carrier Detect (DDCD). Bit 3
indicates that the nDCD input to the chip has
changed state.
NOTE:Whenever bit 0, 1, 2, or 3 is set to a logic
"1", a MODEM Status Interrupt is generated.
Bit 4
This bit is the complement of the Clear To Send
(nCTS) input. If bit 4 of the MCR is set to logic
"1", this bit is equivalent to nRTS in the MCR.
Bit 5
This bit is the complement of the Data Set
Ready (nDSR) input. If bit 4 of the MCR is set
to logic "1", this bit is equivalent to DTR in the
MCR.
Bit 6
This bit is the complement of the Ring Indicator
(nRI) input. If bit 4 of the MCR is set to logic
"1", this bit is equivalent to OUT1 in the MCR.
to logic "1", this bit is equivalent to OUT2 in the
MCR.
SCRATCHPAD REGISTER (SCR)
Address Offset =7H, DLAB =X, READ/WRITE
This 8 bit read/write register has no effect on the
operation of the Serial Port. It is intended as a
scratchpad register to be used by the
programmer to hold data temporarily.
PROGRAMMABLE BAUD RATE GENERATOR
(AND DIVISOR LATCHES DLH, DLL)
The Serial Port contains a programmable Baud
Rate Generator that is capable of taking any
clock input (DC to 3 MHz) and dividing it by any
divisor from 1 to 65535. This output frequency
of the Baud Rate Generator is 16x the Baud
rate. Two 8 bit latches store the divisor in 16 bit
binary format. These Divisor Latches must be
loaded during initialization in order to insure
desired operation of the Baud Rate Generator.
Upon loading either of the Divisor Latches, a 16
bit Baud counter is immediately loaded. This
prevents long counts on initial load. If a 0 is
loaded into the BRG registers the output divides
the clock by the number 3. If a 1 is loaded the
output is the inverse of the input oscillator. If a
two is loaded the output is a divide by 2 signal
with a 50% duty cycle. If a 3 or greater is
loaded the output is low for 2 bits and high for
the remainder of the count. The input clock to
the BRG is the 24 MHz crystal divided by 13,
giving a 1.8462 MHz clock.
Table 33 shows the baud rates possible with a
1.8462 MHz crystal.
Bit 7
This bit is the complement of the Data Carrier
Detect (nDCD) input. If bit 4 of the MCR is set
Effect Of The Reset on Register File
The Reset Function Table (Table 34) details the
effect of the Reset input on each of the registers
of the Serial Port.
80
Page 81
FIFO INTERRUPT MODE OPERATION
When the RCVR FIFO and receiver interrupts
are enabled (FCR bit 0 = "1", IER bit 0 = "1"),
RCVR interrupts occur as follows:
A. The receive data available interrupt will be
issued when the FIFO has reached its
programmed trigger level; it is cleared as
soon as the FIFO drops below its
programmed trigger level.
B. The IIR receive data available indication also
occurs when the FIFO trigger level is
reached. It is cleared when the FIFO drops
below the trigger level.
B. Character times are calculated by using the
RCLK input for a clock signal (this makes
the delay proportional to the baudrate).
C. When a timeout interrupt has occurred it is
cleared and the timer reset when the CPU
reads one character from the RCVR FIFO.
D. When a timeout interrupt has not occurred
the timeout timer is reset after a new
character is received or after the CPU reads
the RCVR FIFO.
When the XMIT FIFO and transmitter interrupts
are enabled (FCR bit 0 = "1", IER bit 1 = "1"),
XMIT interrupts occur as follows:
C. The receiver line status interrupt (IIR=06H),
has higher priority than the received data
available (IIR=04H) interrupt.
D. The data ready bit (LSR bit 0)is set as soon
as a character is transferred from the shift
register to the RCVR FIFO. It is reset when
the FIFO is empty.
When RCVR FIFO and receiver interrupts are
enabled, RCVR FIFO timeout interrupts occur
as follows:
A. A FIFO timeout interrupt occurs if all the
following conditions exist:
- At least one character is in the FIFO
- The most recent serial character received
was longer than 4 continuous character
times ago. (If 2 stop bits are programmed,
the second one is included in this time
delay.)
- The most recent CPU read of the FIFO
was longer than 4 continuous character
times ago.
This will cause a maximum character
received to interrupt issued delay of 160
msec at 300 BAUD with a 12 bit character.
A. The transmitter holding register interrupt
(02H) occurs when the XMIT FIFO is empty;
it is cleared as soon as the transmitter
holding register is written to (1 of 16
characters may be written to the XMIT FIFO
while servicing this interrupt) or the IIR is
read.
B. The transmitter FIFO empty indications will
be delayed 1 character time minus the last
stop bit time whenever the following occurs:
THRE=1 and there have not been at least
two bytes at the same time in the transmitter
FIFO since the last THRE=1. The transmitter
interrupt after changing FCR0 will be
immediate, if it is enabled.
Character timeout and RCVR FIFO trigger level
interrupts have the sme priority as the current
received data available interrupt; XMIT FIFO
empty has the same priority as the current
transmitter holding register empty interrupt.
FIFO POLLED MODE OPERATION
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or
3 or all to zero puts the UART in the FIFO
Polled Mode of operation. Since the RCVR and
81
Page 82
XMITTER are controlled separately, either one
or both can be in the polled mode of operation.
mode, the IIR is not affected since EIR bit
2=0.
- Bit 5 indicates when the XMIT FIFO is
In this mode, the user's program will check
RCVR and XMITTER status via the LSR. LSR
definitions for the FIFO Polled Mode are as
follows:
empty.
- Bit 6 indicates that both the XMIT FIFO and
shift register are empty.
- Bit 7 indicates whether there are any errors
in the RCVR FIFO.
- Bit 0=1 as long as there is one byte in the
RCVR FIFO.
- Bits 1 to 4 specify which error(s) have
occurred. Character error status is handled
the same way as when in the interrupt
There is no trigger level reached or timeout
condition indicated in the FIFO Polled Mode,
however, the RCVR and XMIT FIFOs are still
fully capable of holding characters.
Table 33 - Baud Rates Using 1.8462 MHz Clock (24 MHz/13)
DESIRED
BAUD RATE
DIVISOR USED TO
GENERATE 16X CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL*
50 2307 0.03 X
75 1538 0.03 X
110 1049 0.005 X
134.5 858 0.01 X
150 769 0.03 X
300 384 0.16 X
600 192 0.16 X
1200 96 0.16 X
1800 64 0.16 X
2000 58 0.5 X
2400 48 0.16 X
3600 32 0.16 X
4800 24 0.16 X
7200 16 0.16 X
9600 12 0.16 X
19200 6 0.16 X
38400 3 0.16 X
57600 2 1.6 X
115200 1 0.16 X
230400 32770 0.16 1
460800 32769 0.16 1
CROC:
BIT 7 OR 6
82
Page 83
Table 34 - Reset Function Table
REGISTER/SIGNAL
Interrupt Enable Register RESET All bits low
Interrupt Identification Reg. RESET Bit 0 is high; Bits 1 thru 7 low
FIFO Control RESET All bits low
Line Control Reg. RESET All bits low
MODEM Control Reg. RESET All bits low
Line Status Reg. RESET All bits low except 5, 6 high
MODEM Status Reg. RESET Bits 0 - 3 low; Bits 4 - 7 input
TXD1, TXD2 RESET High
INTRPT (RCVR errs) RESET/Read LSR Low
INTRPT (RCVR Data Ready) RESET/Read RBR Low
INTRPT (THRE) RESET/ReadIIR/Write THR Low
OUT2B RESET High
RTSB RESET High
DTRB RESET High
OUT1B RESET High
RCVR FIFO RESET/FCR1*FCR0/FCR0 All Bits Low
XMIT FIFO RESET/FCR1*FCR0/FCR0 All Bits Low
RESET CONTROL
RESET STATE
83
Page 84
Table 35 - Register Summary for an Individual UART Channel
REGISTER
ADDRESS* REGISTER NAME
ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
ADDR = 2 Interrupt Ident. Register (Read Only) IIR "0" if Interrupt
ADDR = 2 FIFO Control Register (Write Only) FCR FIFO Enable RCVR FIFO
ADDR = 3 Line Control Register LCR
ADDR = 4 MODEM Control Register MCR Data
ADDR = 5 Line Status Register LSR
ADDR = 6 MODEM Status Register MSR
ADDR = 7
ADDR = 0
DLAB = 1
ADDR = 1
DLAB = 1
Receive Buffer Register (Read Only) RBR Data Bit 0
Transmitter Holding Register (Write
Only)
Interrupt Enable Register IER Enable
Scratch Register (Note 4) SCR Bit 0 Bit 1
Divisor Latch (LS) DDL Bit 0 Bit 1
Divisor Latch (MS) DLM Bit 8 Bit 9
REGISTER
SYMBOL BIT 0 BIT 1
Data Bit 1
(Note 1)
THR Data Bit 0 Data Bit 1
Enable
Received
Data
Available
Interrupt
(ERDAI)
Pending
Word Length
Select Bit 0
(WLS0)
Terminal
Ready (DTR)
Data Ready
(DR)
Delta Clear to
Send (DCTS)
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
Interrupt ID
Bit
Reset
Word Length
Select Bit 1
(WLS1)
Request to
Send (RTS)
Overrun
Error (OE)
Delta Data
Set Ready
(DDSR)
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
84
Page 85
Table 35 - Register Summary for an Individual UART Channel (continued)
BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
Data Bit 2
Data Bit 2
Enable
Receiver Line
Status
Interrupt
(ELSI)
Interrupt ID
Bit
Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7
Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7
Enable
0 0 0
MODEM
Status
Interrupt
(EMSI)
Interrupt ID
Bit (Note 5)
0 0 FIFOs
Enabled
(Note 5)
XMIT FIFO
Reset
DMA Mode
Select
Reserved Reserved RCVR Trigger
LSB
(Note 6)
Number of
Stop Bits
Parity Enable
(PEN)
Even Parity
Select (EPS)
Stick Parity Set Break
(STB)
OUT1
(Note 3)
Parity Error
(PE)
Trailing Edge
Ring Indicator
(TERI)
Bit 2
Bit 2
Bit 10
OUT2
Loop 0 0 0
(Note 3)
Framing Error
(FE)
Delta Data
Carrier Detect
Break
Interrupt (BI)
Clear to Send
(CTS)
Transmitter
Holding
Register
(THRE)
Data Set
Ready (DSR)
Transmitter
Empty
(TEMT) (Note
2)
Ring Indicator
(RI)
(DDCD)
Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 11 Bit 12 Bit 13 Bit 14 Bit 15
0
FIFOs
Enabled
(Note 5)
RCVR Trigger
MSB
Divisor Latch
Access Bit
(DLAB)
Error in
RCVR FIFO
(Note 5)
Data Carrier
Detect (DCD)
Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
85
Page 86
86
NOTES ON SERIAL PORT OPERATION
FIFO MODE OPERATION:
GENERAL
The RCVR FIFO will hold up to 16 bytes
regardless of which trigger level is selected.
TX AND RX FIFO OPERATION
The Tx portion of the UART transmits data
through TXD as soon as the CPU loads a byte
into the Tx FIFO.
The UART will prevent
loads to the Tx FIFO if it currently holds 16
characters.
Loading to the Tx FIFO will again
be enabled as soon as the next character is
transferred to the Tx shift register. These
capabilities account for the largely autonomous
operation of the Tx.
The UART starts the above operations typically
with a Tx interrupt. The chip issues a Tx
interrupt whenever the Tx FIFO is empty and the
Tx interrupt is enabled, except in the following
instance. Assume that the Tx FIFO is empty
and the CPU starts to load it. When the first
byte enters the FIFO the Tx FIFO empty
interrupt will transition from active to inactive.
Depending on the execution speed of the service
routine software, the UART may be able to
transfer this byte from the FIFO to the shift
register before the CPU loads another byte. If
this happens, the Tx FIFO will be empty again
and typically the UART's interrupt line would
transition to the active state. This could cause a
system with an interrupt control unit to record a
Tx FIFO empty condition, even though the CPU
is currently servicing that interrupt.
Therefore, after the first byte has been
loaded into the FIFO the UART will wait one
serial character transmission time before
issuing a new Tx FIFO empty interrupt.
This one character Tx interrupt delay will
remain active until at least two bytes have
been loaded into the FIFO, concurrently.
When the Tx FIFO empties after this
condition, the Tx interrupt will be activated
without a one character delay.
Rx support functions and operation are quite
different from those described for the
transmitter. The Rx FIFO receives data until the
number of bytes in the FIFO equals the selected
interrupt trigger level. At that time if Rx
interrupts are enabled, the UART will issue an
interrupt to the CPU. The Rx FIFO will continue
to store bytes until it holds 16 of them. It will
not accept any more data when it is full. Any
more data entering the Rx shift register will set
the Overrun Error flag. Normally, the FIFO
depth and the programmable trigger levels will
give the CPU ample time to empty the Rx FIFO
before an overrun occurs.
One side-effect of having a Rx FIFO is that the
selected interrupt trigger level may be above the
data level in the FIFO. This could occur when
data at the end of the block contains fewer bytes
than the trigger level. No interrupt would be
issued to the CPU and the data would remain in
the UART.
To prevent the software from
having to check for this situation the chip
incorporates a timeout interrupt.
The timeout interrupt is activated when there is
a least one byte in the Rx FIFO, and neither the
CPU nor the Rx shift register has accessed the
Rx FIFO within 4 character times of the last
byte. The timeout interrupt is cleared or reset
when the CPU reads the Rx FIFO or another
character enters it.
These FIFO related features allow optimization
of CPU/UART transactions and are especially
useful given the higher baud rate capability (256
kbaud).
Page 87
87
INFRARED INTERFACE
The FDC37C669's infrared interface provides
a two-way wireless communications port using
infrared as a transmission medium. Two
infrared implementations have been provided in
the FDC37C669, IrDA and Amplitude Shift
Keyed IR.
IrDA allows serial communication at baud rates
up to 115K Baud. Each word is sent serially
beginning with a zero value start bit. A zero is
signaled by sending a single infrared pulse at
the beginning of the serial bit time. A one is
signaled by sending no infrared pulse during the
bit time. Please refer to the AC timing for the
parameters of these pulses and the IrDA
waveform.
The Amplitude Shift Keyed infrared allows serial
communication at baud rates up to 19.2K Baud.
Each word is sent serially beginning with a zero
value start bit. A zero is signaled by sending a
500kHz waveform for the duration of the serial
bit time. A one is signaled by sending no
transmission the bit time. Please refer to the
AC timing for the parameters of the ASKIR
waveform.
If the Half Duplex option is chosen, there is a
time-out when the direction of the transmission
is changed. This time-out starts at the last bit
transferred during a transmission and blocks the
receiver input until the time-out expires. If the
transmit buffer is loaded with more data before
the time-out expires, the timer is restarted after
the new byte is transmitted. If data is loaded
into the transmit buffer while a character is
being received, the transmission will not start
until the time-out expires after the last receive
bit has been received. If the start bit of another
character is received during this time-out, the
timer is restarted after the new character is
received. The time-out is four character times.
A character time is defined as 10 bit times
regardless of the actual word length being used.
Page 88
88
PARALLEL PORT
The FDC37C669 incorporates an IBM XT/AT
compatible parallel port. The FDC37C669
supports the optional PS/2 type bi-directional
parallel port (SPP), the Enhanced Parallel Port
(EPP) and the Extended Capabilities Port (ECP)
parallel port modes. Refer to the FDC37C669
Configuration Registers and FDC37C669
Hardware Configuration description for
information on disabling, power down, changing
the base address of the parallel port, and
selecting the mode of operation.
DATA PORT BASE ADDRESS + 00H
STATUS PORT BASE ADDRESS + 01H
CONTROL PORT BASE ADDRESS + 02H
EPP ADDR PORT BASE ADDRESS + 03H
The bit map of these registers is:
D0 D1 D2 D3 D4 D5 D6 D7 Note
DATA PORT PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 1
STATUS
PORT
CONTROL
PORT
EPP ADDR
PORT
EPP DATA
PORT 0
EPP DATA
PORT 1
EPP DATA
PORT 2
EPP DATA
PORT 3
TMOUT 0 0 nERR SLCT PE nACK nBUSY 1
STROBE AUTOFD nINIT SLC IRQE PCD 0 0 1
PD0 PD1 PD2 PD3 PD4 PD5 PD6 AD7 2,3
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2,3
The FDC37C669 also incorporates SMSC's
ChiProtect circuitry, which prevents possible
damage to the parallel port due to printer powerup.
The functionality of the Parallel Port is achieved
through the use of eight addressable ports,
with their associated registers and control
gating. The control and data port are read/write
by the CPU, the status port is read/write in the
EPP mode. The address map of the Parallel
Port is shown below:
EPP DATA PORT 0 BASE ADDRESS + 04H
EPP DATA PORT 1 BASE ADDRESS + 05H
EPP DATA PORT 2 BASE ADDRESS + 06H
EPP DATA PORT 3 BASE ADDRESS + 07H
Note 1: These registers are available in all modes.
Note 2: These registers are only available in EPP mode.
Note 3: For EPP mode, IOCHRDY must be connected to the ISA bus.
Page 89
89
Table 36 - Parallel Port Connector
HOST
CONNECTOR
1 77 nStrobe nWrite nStrobe
2-9 71-68, 66-63 PData<0:7> PData<0:7> PData<0:7>
10 62 nAck Intr nAck
11 61 Busy nWait Busy, PeriphAck(3)
12 60 PE (NU) PError,
13 59 Select (NU) Select
14 76 nAutofd nDatastb nAutoFd,
15 75 nError (NU) nFault(1)
16 74 nInit (NU) nInit(1)
17 73 nSelectin nAddrstrb nSelectIn(1,3)
(1) = Compatible Mode
(3) = High Speed Mode
Note: For the cable interconnection required for ECP support and the Slave Connector pin
numbers, refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev.
1.09, Jan. 7, 1993. This document is available from Microsoft.
PIN NUMBER STANDARD EPP ECP
nAckReverse(3)
HostAck(3)
nPeriphRequest(3)
nReverseRqst(3)
Page 90
90
IBM XT/AT COMPATIBLE, BI-DIRECTIONAL
AND EPP MODES
DATA PORT
ADDRESS OFFSET = 00H
BIT 3 nERR - nERROR
The level on the nERROR input is read by the
CPU as bit 3 of the Printer Status Register. A
logic O means an error has been detected; a
logic 1 means no error has been detected.
The Data Port is located at an offset of '00H'
from the base address. The data register is
cleared at initialization by RESET. During a
WRITE operation, the Data Register latches the
contents of the data bus with the rising edge of
the nIOW input. The contents of this register
are buffered (non inverting) and output onto the
PD0 - PD7 ports. During a READ operation in
SPP mode, PD0 - PD7 ports are buffered (not
latched) and output to the host CPU.
STATUS PORT
ADDRESS OFFSET = 01H
The Status Port is located at an offset of '01H'
from the base address. The contents of this
register are latched for the duration of an nIOR
read cycle. The bits of the Status Port are
defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates
that a 10 usec time out has occured on the EPP
bus. A logic O means that no time out error has
occured; a logic 1 means that a time out error
has been detected. This bit is cleared by a
RESET. Writing a one to this bit clears the time
out status bit. On a write, this bit is self clearing
and does not require a write of a zero. Writing a
zero to this bit has no effect.
BIT 4 SLCT - PRINTER SELECTED STATUS
The level on the SLCT input is read by the CPU
as bit 4 of the Printer Status Register. A logic 1
means the printer is on line; a logic 0 means it is
not selected.
BIT 5 PE - PAPER END
The level on the PE input is read by the CPU as
bit 5 of the Printer Status Register. A logic 1
indicates a paper end; a logic 0 indicates the
presence of paper.
BIT 6 nACK - nACKNOWLEDGE
The level on the nACK input is read by the
CPU as bit 6 of the Printer Status Register. A
logic 0 means that the printer has received a
character and can now accept another. A logic
1 means that it is still processing the last
character or has not received the data.
BIT 7 nBUSY - nBUSY
The complement of the level on the nBUSY
input is read by the CPU as bit 7 of the Printer
Status Register. A logic 0 in this bit means that
the printer is busy and cannot accept a new
character. A logic 1 means that it is ready to
accept the next character.
CONTROL PORT
ADDRESS OFFSET = 02H
BITS 1, 2
- are not implemented as register bits,
during a read of the Printer Status Register
these bits are a low level.
The Control Port is located at an offset of '02H'
from the base address. The Control Register is
initialized by the RESET input, bits 0 to 5 only
being affected; bits 6 and 7 are hard wired low.
Page 91
91
BIT 0 STROBE - STROBE
This bit is inverted and output onto the
nSTROBE output.
BIT 1 AUTOFD - AUTOFEED
This bit is inverted and output onto the
nAUTOFD output. A logic 1 causes the
printer to generate a line feed after each line is
printed. A logic 0 means no autofeed.
BIT 2 nINIT - nINITIATE OUTPUT
This bit is output onto the nINIT output without
inversion.
BIT 3 SLCTIN - PRINTER SELECT INPUT
This bit is inverted and output onto the nSLCTIN
output. A logic 1 on this bit selects the printer; a
logic 0 means the printer is not selected.
BIT 4 IRQE - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a
high level may be used to enable interrupt
requests from the Parallel Port to the CPU. An
interrupt request is generated on the IRQ port by
a positive going nACK input. When the IRQE bit
is programmed low the IRQ is disabled.
BIT 5 PCD - PARALLEL CONTROL DIRECTION
Parallel Control Direction is valid in extended
mode only (CR#1<3>=0). In printer mode, the
direction is always out regardless of the state of
this bit. In bi-directional mode, a logic 0 means
that the printer port is in output mode (write); a
logic 1 means that the printer port is in input
mode (read).
Bits 6 and 7 during a read are a low level, and
cannot be written.
EPP ADDRESS PORT
ADDRESS OFFSET = 03H
The EPP Address Port is located at an offset of
'03H' from the base address. The address
register is cleared at initialization by RESET.
During a WRITE operation, the contents of DB0DB7 are buffered (non inverting) and output onto
the PD0 - PD7 ports, the leading edge of nIOW
causes an EPP ADDRESS WRITE cycle to be
performed, the trailing edge of IOW latches
the data for the duration of the EPP write cycle.
During a READ operation, PD0 - PD7 ports are
read, the leading edge of IOR causes an EPP
ADDRESS READ cycle to be performed and the
data output to the host CPU, the deassertion of
ADDRSTB latches the PData for the duration of
the IOR cycle. This register is only available in
EPP mode.
EPP DATA PORT 0
ADDRESS OFFSET = 04H
The EPP Data Port 0 is located at an offset of
'04H' from the base address. The data register
is cleared at initialization by RESET. During a
WRITE operation, the contents of DB0-DB7 are
buffered (non inverting) and output onto the PD0
- PD7 ports, the leading edge of nIOW causes
an EPP DATA WRITE cycle to be performed,
the trailing edge of IOW latches the data for the
duration of the EPP write cycle. During a READ
operation, PD0 - PD7 ports are read, the leading
edge of IOR causes an EPP READ cycle to be
performed and the data output to the host CPU,
the deassertion of DATASTB latches the PData
for the duration of the IOR cycle. This register
is only available in EPP mode.
EPP DATA PORT 1/ADDRESS OFFSET = 05H
The EPP Data Port 1 is located at an offset of
'05H' from the base address. Refer to EPP
DATA PORT 0 for a description of operation.
This register is only available in EPP mode.
EPP DATA PORT 2/ADDRESS OFFSET = 06H
The EPP Data Port 2 is located at an offset of
'06H' from the base address. Refer to EPP
DATA PORT 0 for a description of operation.
This register is only available in EPP mode.
EPP DATA PORT 3
ADDRESS OFFSET = 07H
Page 92
92
The EPP Data Port 3 is located at an offset of
'07H' from the base address. Refer to EPP
DATA PORT 0 for a description of operation.
This register is only available in EPP mode.
EPP 1.9 OPERATION
data) is shown in timing diagram EPP 1.9 Write
Data or Address cycle. IOCHRDY is driven
active low at the start of each EPP write and is
released when it has been determined that the
write cycle can complete. The write cycle can
complete under the following circumstances:
When the EPP mode is selected in the
configuration register, the standard and bidirectional modes are also available. If no EPP
Read, Write or Address cycle is currently
executing, then the PDx bus is in the standard or
bi-directional mode, and all output signals
(STROBE, AUTOFD, INIT) are as set by the
SPP Control Port and direction is controlled by
PCD of the Control port.
In EPP mode, the system timing is closely
coupled to the EPP timing. For this reason, a
watchdog timer is required to prevent system
lockup. The timer indicates if more than 10usec
have elapsed from the start of the EPP cycle
(nIOR or nIOW asserted) to nWAIT being
deasserted (after command). If a time-out
occurs, the current EPP cycle is aborted and the
time-out condition is indicated in Status bit 0.
During an EPP cycle, if STROBE is active, it
overrides the EPP write signal forcing the PDx
bus to always be in a write mode and the
nWRITE signal to always be asserted.
Software Constraints
Before an EPP cycle is executed, the software
must ensure that the control register bit PCD is
a logic "0" (i.e. a 04H or 05H should be written
to the Control port). If the user leaves PCD as a
logic "1", and attempts to perform an EPP write,
the chip is unable to perform the write (because
PCD is a logic "1") and will appear to perform an
EPP read on the parallel bus, no error is
indicated.
EPP 1.9 Write
The timing for a write operation (address or
1. If the EPP bus is not ready (nWAIT is active
low) when nDATASTB or nADDRSTB goes
active then the write can complete when
nWAIT goes inactive high.
2. If the EPP bus is ready (nWAIT is inactive
high) then the chip must wait for it to go
active low before changing the state of
nDATASTB, nWRITE or nADDRSTB. The
write can complete once nWAIT is
determined inactive.
Write Sequence of operation
1. The host selects an EPP register, places
data on the SData bus and drives nIOW
active.
2. The chip drives IOCHRDY inactive (low).
3. If WAIT is not asserted, the chip must wait
until WAIT is asserted.
4. The chip places address or data on PData
bus, clears PDIR, and asserts nWRITE.
5. Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus contains valid
information, and the WRITE signal is valid.
6. Peripheral deasserts nWAIT, indicating
that any setup requirements have been
satisfied and the chip may begin the
termination phase of the cycle.
7. a) The chip deasserts nDATASTB or
nADDRSTRB, this marks the
beginning of the termination phase. If
it has not already done so, the
peripheral should latch the information
byte now.
b) The chip latches the data from the
SData bus for the PData bus and
asserts (releases) IOCHRDY allowing
the host to complete the write
cycle.
Page 93
93
8. Peripheral asserts nWAIT, indicating to the
host that any hold time requirements have
been satisfied and acknowledging the
termination of the cycle.
9. Chip may modify nWRITE and nPDATA in
preparation for the next cycle.
EPP 1.9 Read
The timing for a read operation (data) is shown
in timing diagram EPP Read Data cycle.
IOCHRDY is driven active low at the start of
each EPP read and is released when it has been
determined that the read cycle can complete.
The read cycle can complete under the following
circumstances:
1. If the EPP bus is not ready (nWAIT is
active low) when nDATASTB goes active
then the read can complete when nWAIT
goes inactive high.
2. If the EPP bus is ready (nWAIT is inactive
high) then the chip must wait for it to go
active low before changing the state of
WRITE or before nDATASTB goes active.
The read can complete once nWAIT is
determined inactive.
Read Sequence of Operation
1. The host selects an EPP register and drives
nIOR active.
2. The chip drives IOCHRDY inactive (low).
3. If WAIT is not asserted, the chip must wait
until WAIT is asserted.
4. The chip tri-states the PData bus and
deasserts nWRITE.
5. Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR
is set and the nWRITE signal is valid.
6. Peripheral drives PData bus valid.
7. Peripheral deasserts nWAIT, indicating
that PData is valid and the chip may
begin the termination phase of the cycle.
8. a) The chip latches the data from the
PData bus for the SData bus,
deasserts nDATASTB or nADDRSTRB,
this marks the beginning of the
termination phase.
b) The chip drives the valid data onto the
SData bus and asserts (releases)
IOCHRDY allowing the host to
complete the read cycle.
9. Peripheral tri-states the PData bus and
asserts nWAIT, indicating to the host that
the PData bus is tri-stated.
10. Chip may modify nWRITE, PDIR and
nPDATA in preparation for the next cycle.
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the
configuration register, the standard and bidirectional modes are also available. If no EPP
Read, Write or Address cycle is currently
executing, then the PDx bus is in the standard or
bi-directional mode, and all output signals
(STROBE, AUTOFD, INIT) are as set by the
SPP Control Port and direction is controlled by
PCD of the Control port.
In EPP mode, the system timing is closely
coupled to the EPP timing. For this reason, a
watchdog timer is required to prevent system
lockup. The timer indicates if more than 10usec
have elapsed from the start of the EPP cycle
(nIOR or nIOW asserted) to the end of the
cycle nIOR or nIOW deasserted). If a time-out
occurs, the current EPP cycle is aborted and the
time-out condition is indicated in Status bit 0.
Software Constraints
Before an EPP cycle is executed, the software
must ensure that the control register bits D0, D1
and D3 are set to zero. Also, bit D5 (PCD) is a
logic "0" for an EPP write or a logic "1" for and
EPP read.
EPP 1.7 Write
The timing for a write operation (address or
data) is shown in timing diagram EPP 1.7 Write
Page 94
94
Data or Address cycle. IOCHRDY is driven
active low when nWAIT is active low during the
EPP cycle. This can be used to extend the cycle
time. The write cycle can complete when
nWAIT is inactive high.
Write Sequence of Operation
1. The host sets PDIR bit in the control
register to a logic "0". This asserts
nWRITE.
2. The host selects an EPP register, places
data on the SData bus and drives nIOW
active.
3. The chip places address or data on PData
bus.
4. Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus contains valid
information, and the WRITE signal is valid.
5. If nWAIT is asserted, IOCHRDY is
deasserted until the peripheral deasserts
nWAIT or a time-out occurs.
6. When the host deasserts nI0W the chip
deasserts nDATASTB or nADDRSTRB and
latches the data from the SData bus for the
PData bus.
7. Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
EPP 1.7 Read
The timing for a read operation (data) is shown
in timing diagram EPP 1.7 Read Data cycle.
IOCHRDY is driven active low when nWAIT is
active low during the EPP cycle. This can be
used to extend the cycle time. The read cycle
can complete when nWAIT is inactive high.
Read Sequence of Operation
1. The host sets PDIR bit in the control
register to a logic "1". This deasserts
nWRITE and tri-states the PData bus.
2. The host selects an EPP register and drives
nIOR active.
3. Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR
is set and the nWRITE signal is valid.
4. If nWAIT is asserted, IOCHRDY is
deasserted until the peripheral deasserts
nWAIT or a time-out occurs.
5. The Peripheral drives PData bus valid.
6. The Peripheral deasserts nWAIT,
indicating that PData is valid and the chip
may begin the termination phase of the
cycle.
7. When the host deasserts nI0R the chip
deasserts nDATASTB or nADDRSTRB.
8. Peripheral tri-states the PData bus.
9. Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
Page 95
95
Table 37 - EPP Pin Descriptions
EPP
SIGNAL EPP NAME TYPE EPP DESCRIPTION
nWRITE nWrite O This signal is active low. It denotes a write operation.
PD<0:7> Address/Data I/O Bi-directional EPP byte wide address and data bus.
INTR Interrupt I This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
WAIT nWait I This signal is active low. It is driven inactive as a positive
acknowledgement from the device that the transfer of data
is completed. It is driven active as an indication that the
device is ready for the next transfer.
DATASTB nData Strobe O This signal is active low. It is used to denote data read or
write operation.
RESET nReset O This signal is active low. When driven active, the EPP
device is reset to its initial operational mode.
ADDRSTB nAddress
Strobe
PE Paper End I Same as SPP mode.
SLCT Printer
Selected
Status
nERR Error I Same as SPP mode.
PDIR Parallel Port
Direction
O This signal is active low. It is used to denote address read
or write operation.
I Same as SPP mode.
O This output shows the direction of the data transfer on the
parallel port bus. A low means an output/write condition and
a high means an input/read condition. This signal is
normally a low (output/write) unless PCD of the control
register is set or if an EPP read cycle is in progress.
Note 1: SPP and EPP can use 1 common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP
cycle. For correct EPP read cycles, PCD is required to be a low.
Page 96
96
EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of
which are listed below. The individual features
are explained in greater detail in the remainder
of this section.
High performance half-duplex forward and
•
reverse channel
Interlocked handshake, for fast reliable
•
transfer
Optional single byte RLE compression for
•
improved throughput (64:1)
Channel addressing for low-cost peripherals
•
Maintains link and data layer separation
•
Permits the use of active output drivers
•
Permits the use of adaptive signal timing
•
Peer-to-peer capability
•
PWord
A port word; equal in size to the
width of the ISA interface. For this
implementation, PWord is always 8
bits.
1
0
A high level.
A low level.
These terms may be considered synonymous:
PeriphClk, nAck
•
HostAck, nAutoFd
•
PeriphAck, Busy
•
nPeriphRequest, nFault
•
nReverseRequest, nInit
•
nAckReverse, PError
•
Xflag, Select
•
ECPMode, nSelectln
•
HostClk, nStrobe
•
Vocabulary
Reference Document:
The following terms are used in this document:
IEEE 1284 Extended Capabilities Port Protocol
assert
When a signal asserts it
transitions to a "true" state, when a
signal deasserts it transitions to a
and ISA Interface Standard, Rev 1.09, Jan 7,
1993. This document is available from
Microsoft.
"false" state.
forward
reverse
Host to Peripheral communication.
Peripheral to Host communication.
The bit map of the Extended Parallel Port
registers is:
D7 D6 D5 D4 D3 D2 D1 D0 Note
data PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
ecpAFifo Addr/RL
Address or RLE field 2
E
dsr nBusy nAck PError Select nFault 0 0 0 1
dcr 0 0
Direction
ackIntEn SelectIn nInit autofd strobe 1
cFifo Parallel Port Data FIFO 2
ecpDFifo ECP Data FIFO 2
tFifo Test FIFO 2
cnfgA 0 0 0 1 0 0 0 0
cnfgB
ecr MODE
compress intrValue
0 0 0 0 0 0
nErrIntrEn
dmaEn
serviceIntr
full empty
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
Page 97
97
ISA IMPLEMENTATION STANDARD
This specification describes the standard ISA
interface to the Extended Capabilities Port
(ECP). All ISA devices supporting ECP must
meet the requirements contained in this section
or the port will not be supported by Microsoft.
For a description of the ECP Protocol, please
refer to the IEEE 1284 Extended Capabilities
Port Protocol and ISA Interface Standard, Rev.
1.09, Jan.7, 1993. This document is available
from Microsoft.
Description
The port is software and hardware compatible
with existing parallel ports so that it may be
used as a standard LPT port if ECP is not
required. The port is designed to be simple and
requires a small number of gates to implement.
It does not do any "protocol" negotiation, rather
it provides an automatic high burst-bandwidth
channel that supports DMA for ECP in both the
forward and reverse directions.
Small FIFOs are employed in both forward and
reverse directions to smooth data flow and
improve the maximum bandwidth requirement.
The size of the FIFO is 16 bytes deep. The port
supports an automatic handshake for the
standard parallel port to improve compatibility
mode transfer speed.
The port also supports run length encoded
(RLE) decompression (required) in hardware.
Compression is accomplished by counting
identical bytes and transmitting an RLE byte
that indicates how many times the next byte is
to be repeated. Decompression simply
intercepts the RLE byte and repeats the
following byte the specified number of times.
Hardware support for compression is optional.
Page 98
98
Table 38 - ECP Pin Descriptions
NAME TYPE DESCRIPTION
nStrobe O During write operations nStrobe registers data or address into the slave
on the asserting edge (handshakes with Busy).
PData 7:0 I/O Contains address or data or RLE data.
nAck I Indicates valid data driven by the peripheral when asserted. This signal
handshakes with nAutoFd in reverse.
PeriphAck (Busy) I This signal deasserts to indicate that the peripheral can accept data.
This signal handshakes with nStrobe in the forward direction. In the
reverse direction this signal indicates whether the data lines contain
ECP command information or data. The peripheral uses this signal to
flow control in the forward direction. It is an "interlocked" handshake
with nStrobe. PeriphAck also provides command information in the
reverse direction.
PError
(nAckReverse)
I Used to acknowledge a change in the direction the transfer (asserted =
forward). The peripheral drives this signal low to acknowledge
nReverseRequest. It is an "interlocked" handshake with
nReverseRequest. The host relies upon nAckReverse to determine
when it is permitted to drive the data bus.
Select I Indicates printer on line.
nAutoFd
(HostAck)
O Requests a byte of data from the peripheral when asserted,
handshaking with nAck in the reverse direction. In the forward direction
this signal indicates whether the data lines contain ECP address or
data. The host drives this signal to flow control in the reverse direction.
It is an "interlocked" handshake with nAck. HostAck also provides
command information in the forward phase.
nFault
(nPeriphRequest)
I Generates an error interrupt when asserted. This signal provides a
mechanism for peer-to-peer communication. This signal is valid only in
the forward direction. During ECP Mode the peripheral is permitted
(but not required) to drive this pin low to request a reverse transfer. The
request is merely a "hint" to the host; the host has ultimate control over
the transfer direction. This signal would be typically used to generate
an interrupt to the host CPU.
nInit O Sets the transfer direction (asserted = reverse, deasserted = forward).
This pin is driven low to place the channel in the reverse direction. The
peripheral is only allowed to drive the bi-directional data bus while in
ECP Mode and HostAck is low and nSelectIn is high.
nSelectIn O Always deasserted in ECP mode.
Page 99
99
Register Definitions
The register definitions are based on the
standard IBM addresses for LPT. All of the
standard printer ports are supported. The
additional registers attach to an upper bit
decode of the standard LPT port definition to
Table 39 - ECP Register Definitions
NAME ADDRESS (Note 1) ECP MODES FUNCTION
data +000h R/W 000-001 Data Register
ecpAFifo +000h R/W 011 ECP FIFO (Address)
dsr +001h R/W All Status Register
dcr +002h R/W All Control Register
cFifo +400h R/W 010 Parallel Port Data FIFO
ecpDFifo +400h R/W 011 ECP FIFO (DATA)
tFifo +400h R/W 110 Test FIFO
cnfgA +400h R 111 Configuration Register A
cnfgB +401h R/W 111 Configuration Register B
ecr +402h R/W All Extended Control Register
Note 1: These addresses are added to the parallel port base address as selected by configuration
register or jumpers.
Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.
avoid conflict with standard ISA devices. The
port is equivalent to a generic parallel port
interface and may be operated in that mode.
The port registers vary depending on the mode
field in the ecr. The table below lists these
dependencies. Operation of the devices in
modes other that those specified is undefined.
Table 40 - Mode Descriptions
MODE DESCRIPTION*
000 SPP mode
001 PS/2 Parallel Port mde
010 Parallel Port Data FIFO mode
011 ECP Parallel Port mode
100 EPP mode (If this option is enabled in the configuration registers)
101 (Reserved)
110 Test mode
111 Configuration mode
*Refer to ECR Register Description
Page 100
100
DATA and ecpAFifo PORT
ADDRESS OFFSET = 00H
Modes 000 and 001 (Data Port)
BIT 5 PError
The level on the PError input is read by the CPU
as bit 5 of the Device Status Register. Printer
Status Register.
The Data Port is located at an offset of '00H'
from the base address. The data register is
cleared at initialization by RESET. During a
WRITE operation, the Data Register latches the
contents of the data bus on the rising edge of
the nIOW input. The contents of this register
are buffered (non inverting) and output onto the
PD0 - PD7 ports. During a READ operation,
PD0 - PD7 ports are read and output to the host
CPU.
Mode 011 (ECP FIFO - Address/RLE)
A data byte written to this address is placed in
the FIFO and tagged as an ECP Address/RLE.
The hardware at the ECP port transmits this
byte to the peripheral automatically. The
operation of this register is only defined for the
forward direction (direction is 0). Refer to the
ECP Parallel Port Forward Timing Diagram,
located in the Timing Diagrams section of this
data sheet.
DEVICE STATUS REGISTER (dsr)
ADDRESS OFFSET = 01H
The Status Port is located at an offset of '01H'
from the base address. Bits 0 - 2 are not
implemented as register bits, during a read of
the Printer Status Register these bits are a low
level. The bits of the Status Port are defined as
follows:
BIT 3 nFault
The level on the nFault input is read by the CPU
as bit 3 of the Device Status Register.
BIT 6 nAck
The level on the nAck input is read by the
CPU as bit 6 of the Device Status Register.
BIT 7 nBusy
The complement of the level on the BUSY input
is read by the CPU as bit 7 of the Device Status
Register.
DEVICE CONTROL REGISTER (dcr)
ADDRESS OFFSET = 02H
The Control Register is located at an offset of
'02H' from the base address. The Control
Register is initialized to zero by the RESET
input, bits 0 to 5 only being affected; bits 6 and
7 are hard wired low.
BIT 0 STROBE - STROBE
This bit is inverted and output onto the
nSTROBE output.
BIT 1 AUTOFD - AUTOFEED
This bit is inverted and output onto the
nAUTOFD output. A logic 1 causes the printer
to generate a line feed after each line is printed.
A logic 0 means no autofeed.
BIT 2 nINIT - nINITIATE OUTPUT
This bit is output onto the nINIT output without
inversion.
BIT 3 SELECTIN
This bit is inverted and output onto the nSLCTIN
output. A logic 1 on this bit selects the printer; a
logic 0 means the printer is not selected.
BIT 4 Select
The level on the Select input is read by the CPU
as bit 4 of the Device Status Register.
BIT 4 ackIntEn - INTERRUPT REQUEST
ENABLE
The interrupt request enable bit when set to a
high level may be used to enable interrupt
Loading...